JPS58188396A - Thin film shift register integrated circuit - Google Patents

Abstract

PURPOSE:To extend the operating frequency range and to stabilize the output amplitude, by connecting plural thin film FETs of common gate in series and forming an IC with the FET train regarded as one FET. CONSTITUTION:A basic circuit corresponding to one-bit is formed with thin FETs 801-804 connected in series. In a shift register formed with the basic circuits connected in cascade, when a data 1 is read in a cell 806 of the 3rd stage, a potential G3 overshoots largely at a high level of a clock phi2 at the same time with the rise of the clock phi2 and the potential is kept until the phi2 is dropped. Thus, the potential at an output terminal F3 reaches the high level of the phi2 at a high speed. Thus, the upper limit of the operating frequency of the shift register is improved and the output amplitude is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift-cis-4 Toyoko circuit of the Pootstrup effect type, and particularly to a shift register 81 circuit formed as a thin integrated circuit using polycrystalline silicon or amorphous silicon. -In recent years, a liquid crystal display (liquid crystal display consisting of an active matrix substrate with a TIT array and a liquid crystal display body) has been developed as a 111IIIi transistor (hereinafter abbreviated as TPT) as a gate switching element. Active matrix M using one TPT play that is being done in various places
However, TPT has the advantage that it is a low-cost, simple manufacturing process, and easy to increase the area compared to a transistor matrix substrate in which a monocrystalline silicon base is gradually incorporated. Transistor characteristics are inferior to those of single-crystal silicon MO8 transistors (for example, low carrier mobility Ln, low ftk
*It has the disadvantage that it is difficult to build a drive circuit into an active matrix board because of the high EE. -One purpose of the present invention is to apply it to an active matrix board. We propose a thin-transistor shift register integrated circuit that overcomes the above-mentioned drawbacks and has excellent performance. Conventionally, single-conductivity type M08 transistors are used in single-crystal silicon-based MOP integrated circuits. In order to obtain a sufficiently loud logic amplitude and a sufficiently fast response speed when the shift register integration port #I-format is released, the Pootstrap effect using an MO8 capacitor whose valley value changes depending on the gate voltage is applied. The solidification of the shift register in the form of a shift register is well known. ・Part 1-(a) is formed on a single-crystal silicon substrate. ? 111r is shown (in this gA+, the conduction type of the transistor is MOS) MO8 transistor 101tfllBi
When this clock is high, the output data of the 1-1 stage is inserted through 1k101f.
The substrate of the MO8 capacitor 105 is reversed only when the voltage is 1, and the 105 operates as a Pootstrap cylinder.Furthermore, the clock of the terminal B1 becomes low and the 1st capacitor C
When the clock input to 1 becomes high, the potential of @pa1 becomes smaller than the high level of the clock signal (e < t-Pa) 1. , Promote conduction of the MOS transistor 102 - Due to the stiffness, the 11S' position of the terminal D1 becomes 1l
When the primary h-bit U-k which reaches the high level at the FI speed is reversed and B1 becomes high and C1 becomes low, M08) The transistor 105 becomes conductive and the output terminals D1 and F
The potential of l becomes low. At the same time, data is transferred to node D1+1, and the potential of D1+1 becomes high. Terminal E1-1 is connected to terminal Di+IK, and the aforementioned Dl drops to low. In the same period as the node Gi
The charge held in K is transferred to the first stage) M2S) → MOS transistor 1D4 of transistor 101 and 1-11 anchor 1
It is discharged through f and G10'1 becomes low.
(b) shows the -1 tube of the shift register 1g1- which is constructed based on the above-mentioned basic structure, and 11th (c) is a timing chart of the signals of each part of the shift register 1g1-. Il? In FIG. 1(C), φI and φT are clock signals, 5PVis J-to pulses, G, F, and G.

Fm, Gm, and Fm respectively indicate the reliability of terminals with the same symbol in wL181'1(b).Second and first, they indicate the voltage-electricity fN characteristics of the fiMO8 transistor formed on a single-crystal silicon substrate. In Figure 1, Vos is the gate-to-source voltage, IDIVj is the gate-to-drain W current, 201 MO day transistor cutoff @ Castle, 2 o2 Fih Shio l! +, axis area, 202 ke residual ash inversion area, Vll ke threshold 'I4! rI
fte, 204, 205, 2061d, respectively, the drain-north voltage Vn- is Vng = V, (to), V
ll8 = Vl (V), Vns x Vl(
V) is the voltage-1 current characteristic when (69, V
l<Vl (Vm) From FIG. Drain III-E dependence is small. (2) In the weak inversion region 202, r, f, and if of ma between the drain and source are small. (3) L-threshold voltage is low and gear 11A The amplitude of the vibration is large. For example 3, the channel length = 20 μm 1 channel width W-1
The stress of a thin film transistor with a size of 0 μm - Shows -911 of the Tomijin characteristic - This data is based on experiments conducted by Mr. Mizude - The horizontal axis of this graph is the gate voltage Vos with respect to the source. , and the thin axis is the one song between the drain and source, which is the town style ID8 - 304-1305
13o613o71308FiSotI 1゛ field of train for each source Vns f Vng = 1 (
V), Vng = 5 (V), VD! + =
10 (V) +vns = 20 (V), Vn
When g -50 (V), the actual value of the warehouse is +, b, 5
o1tt thin-discipline transistor's IIT area area 302
Fil [y, transfer mtii't,! *S o std strong anti-ash area f ・3rd and 11th, crystalline silicon MO8 transistor and sintered fc, case of thin film transistor'
ell? F II tAt% 41 is (1)
(2) In weak inversion region 302, as VGw increases, The award of 8 is gradual. (3) L6 Tsukudadenou, i.e. area 302 and porcelain area 303
'I'lf at the boundary is high and the carrier shift #] is small,
It can be seen that it is 5-year-old. As a result, thin film transistors often have poor current characteristics compared to single-crystal silicon MOS transistors. Thin film shift register integrated circuit with thin film shift register integrated circuit has some drawbacks, 1st 4V, 11th H(a) single crystal silicon S,! ('+ 8 Tran・'unstar 101
The waveforms 1r of various parts of the shift register integrated port D, which are replaced by 104 thin film transistors, are shown. φl of Y4.

φ1 and SP are 11th and 11J (C) respectively.
,φl.

Same signal waveform as FIP・Gs, I's in Figure 4
Figure 1: Nodes J, Gs in (a) + (b)
, Fm's Shin-4a type, and the actual image is from an actual thin-film shift register Ju111, and the dotted line is from a normally operating shift register collection book.The amplitude of the output signal of the previous stage is sufficiently large. The amplitude of the data input to VCfldam will be as low as 401, and the potential of Gs will be sufficiently high between 1 and 2. Because of the IN flow, that is, the OFF leaf, in the [7 and disconnection region of the thin film tone sensor corresponding to tpl and 101, the potential of GI +j (lower axis direction'1
Due to the above reasons, the signal waveform of the output node F, 404, 40, has a small amplitude and slow speed, as shown in the signal waveform 403.
5. The instability inside the throat is caused by the OFF leaf of the thin film transistor corresponding to 101. ・406 to 409 are
Ant with a feeding pulse that does not break during normal movement,
The reason for the ζ straw border is due to the increase in vDII of the thin film transistor corresponding to 1102. F
11-7. This kind of malfunction pulse is also a factor that completely determines the lower limit of the operating frequency of the shift register, and the OFF leaf becomes large and the lower limit of the machine becomes high.The purpose of the present invention is to The purpose of the present invention is to compensate for the operational shortcomings of the thin-film shift register integrated circuit caused by the imperfection of the electron-W flow characteristics of the thin-film transistor as described above, and to obtain a thin-film shift register integrated circuit with excellent performance. It is in. IJ'F, figure r
Converting the electrons of the present invention into one fiber using kl - Theory 5 and 1
This is a basic S-shaped f7r diagram of a wooden kidney shell. The gist of the present invention is to construct a transistor array in which a gate is common and a plurality of Kasumi thin film transistors are connected to each other in a row, as in the case of CAN10FF of a transistor array.
In addition to improving the ratio, this transistor array is treated as one transistor and integrated into a thin film shift register. It is frustrating to improve the performance of the thin shift register integrated circuit 1 by horizontal transfer.
In 8. D and G are tran nos 1m each
l? −(When considered as a 1p+ transistor, it shows the negative source, drain, and gate, and represents the number of thin film transistors connected to N[++lIK − In this way, r*
[Power I] The transistor array has a very strong and OFF% property.The reason for this is explained using the example of the N-82's Sakai connection using Fig. 6. 1 (PL) is the friend of N-2 in the 5th si 1, the 0th 6th 'Q' (a)
, the potentials of El, D, G, and X are Vs and V, respectively.
Number 1゜2-1 in the diagram, 6 arrivals, t+, Va, Vx
Attached to two thin film transistors, the channel &? Assuming Lt and Ls, the 61st!1 (b) is the same IN (a) transistor replaced by one transistor Kt11 in terms of scale, and the channel length is Ls + L3, which is #I. - Drain voltage 1 of transistor 1 [Vns+.

Gate 1 voltage VG1 and transistor 2 drain voltage I
fVD” *Gate wealth U+:VG!+2 is given by the following formula: 1V[Ib+ = Vx −Vs V(181=V(1−Vs) VD82 =: VD −VI VGI2 = VG −VX Current flowing through transistor 1 One can V at point X so that ′v6η1.
! takes hold, this eclipse, on the 7th (Vx (Vu is established,
As a result, the drain electrons VD -Vs will be divided into 2' transistors and applied to V (therefore, the drain voltage 1 should decrease), or the drain electrons 1 and 1 and the channel In a rivalry in which a short intercourse is established in the darkness with the length, the drain current mFite force O is increased by the amount of channel length compared to the sixth one (b).
) and the transistor shown in Whale 6-1 (b), the t-flow Tsukuda becomes strange.In fact, the region 3 based on ash
02 and area 305, this relationship is established and ON
The current is not ffPL - that is, it does not matter how the channel length is divided into water chambers fk, l1ll. However, the situation is different in the 7'j region 301 shown in Figure 3. This is because thin film transistors When operating in the next region 501 shown in Section 5-1, as the gate voltage becomes smaller ζ, the dependence on the channel length of the drain 11a disappears;
In other words, as the gate 1w pressure is reduced and the thin film transistor operates in a thermally disconnected state, the oyy current becomes independent of the channel length. The effect due to the difference in channel length between (a) and (b) is as follows: (b) has a 6Joyyll current by the amount that the drain 11' is reduced by 71fi for each transistor. The more negative the gate 1 pressure is biased, the more pronounced it becomes.
The physical properties of the phenomenon of 90 yen and 90 yen are as follows: #t1.6. When the transistor is in the ON state, a channel is carved on the surface of the semiconductor thin film. Even if the channel is divided into As a result, the power to the FN of each individual is increased.
'W concentration can be weakened and the junction leakage current, that is, the oyyl' current can be reduced. Lt=TJI
= 10 prn, W+ = Wm = 10 μ
This is the transistor characteristic of m-to-haze ψ. This transistor is roughly equivalent to the transistor shown in Pole 5 I. This data is also the result obtained by the Mizude V people. Songs 701 and 702. , 703, 704, and 705 respectively, the drain 11 pressure Vt+g with respect to the source is VDII
= 1(V), Vns = 5i), Vns =
10(V).

VDII = 2(I M , VDII -30(V
6) Figure 8(a) shows the first stage of the shift register. 11(a), each transistor 101, 102, 1045°104
] Self-connected thin film transistor 8
01, 802, 805, and 804, and the basic circuit obtained by connecting the two thin film transistors in series to the basic circuit #111-
Friends line up to list their accomplishments! # The number of m-transistors to be integrated can be any number - Also, it is not necessary that every transistor row is by more than one thin film transistor;
If the transistor array is made up of V thin transistors, then the present invention is applicable to the present invention.
) is a diagram of a shift register constructed by vertically connecting basic circuits, and its basic operation is;ir 11'VI
K 7F L 7'c shift register and all (similar, 1st evening 1 (c), 8th night 1 (a), (b)
The signal waveforms of each part of the shift register shown in K are constant -t・φ
l, φ嘗 are paired clock signals, and P is a start pulse.Next, referring to Fig. 8(b), take fHIK of the cell 806 in the third stage to obtain the effect of the i invention. Reveal. By changing the basic construction method to Fig. 8 1 (+!L), Masukatsu transistor row 801t71OFF
The leakage current is reduced by gluttony, so at t3 8chen1(
c) As per 810〈Data 1 is a beast in the G field, and when it is absorbed, it is a warehouse, and at the same time as clock φ1 is raised, G, as per 811〈The high level of clock φ, or higher. Human creation <open knee t,, φ3 falls down 2) 4
The low level of the small voltage terminal Fl reaches the high level of the clock signal at a high speed as if it were connected to the stone 812 that holds the potential.

That is, by setting the water valve to the right shore, the frequency of the shift register's operating frequency C is increased, and the output amplitude is increased to 6.0, and the OF F +1 of the thin film transistor array 802 is increased.
- 406 Noki 4 in Figure 4 because the flow is greatly reduced.
As shown in 09, the operating pulse is suppressed, and the lower limit of the wave number of the shift register is low. A's other dormitory
A stroke 9 1 (a) indicating 1 is a group A corresponding to 1 focus of the first stage of a bootstrap effect type shift register,
91v (b) The terminal 911 connected to the throat hood,
912°9M3,914. and 915, respectively, with lock credentials φ1. φ Zeng, φ Todoroki.

By applying φ4 and sp, the shift register changes to *
In the first stage, the shift register cell 910 of the fifth stage in FIG. 9, 1(b) is turned on, and 1clt is lost - the lock signal φ is low, and the X/41Wj K ffi is turned on.

When data 1 is included in IA, thin film MO8 capantor 9
05 C1) Substrate Pi)'P; Surface is reversed and 9
051 The primary φ, which forms a refreshing valley habit, rises to low/4 to high, and at the same time, due to the bootstrap young fruit of eaves 4905, D117') - becomes the high level of the clock signal b0. Thick overshoot makes the conduction of the transistor arrays 901 and 903 (b: f false 90) and at the same time as 905 turns on, the node 92s and the output 1 child y
The iK addition is rapidly charged and the hw*, K
The potential of Fs and Fs is the potential r of the clock signal...
+ stands up - at this time 4 t', 2 #3 shift register cell ill Ill M OS key V passer 9
The substrate of 05 is reversed - a slow period V just before φ1 falls from high to low (φ, Vi becomes high and Wr was seen in allb+A+Ds which turns on the thin film transistor array 902 of the second stage cell. 902 for electricity
Through the discharge σ, about 1M of El falls - φ凰 falls from high to low, φ■ falls from low)・At the same time as it rises to A, the 1st position of the output 1 child Fm is standing. The signal waveforms of each part of Garu Ichiki 961 (c) are shown. Also in Kinomi h%l, thin film transistor arrays are constructed once a month.
If the node D1/h overshoots, the true 1-1st stage thin film transistor array 901, 902 OF F I
The key is to keep the node D1 at a stable high potential as the 11ηI decreases and the OFF leakage current of the thin film transistor array 1] 903 is reduced, thereby reducing the output terminal FiK error. As mentioned above, by applying this wisdom, preventing the occurrence of rusu is one death.
A thin film shift register integrated circuit with a wide operating frequency range, stable output, and narrow width is actually practiced. (active player) +1 It is possible to create a #movement movement to Kusuki.

[Brief explanation of drawings]

The first part 1(a) to (8) is a conventional shift register integration 1.
A picture of how to catch a mackerel. No. 21 &' tJ single-connected comb 1 con MO8) Falling King of Ranjisme - ㅅ1- with W style characteristics! SI) Figures 6(a) and 6(b) are diagrams showing the characteristics of the thin film transistor array when the thin film transistor array is ridged. PJ, 8 vll (a) and (c) show implementation-1 of this book Ua, and Figures 9 and 7 (a) to (C) show another implementation II of this book Ua. Source Suwa Seikosha Co., Ltd. Agent Agent Tsutomu Mogami Fig. 1 S) Fig. 4 Fig. 5 G p (Ren Fig. 6 Fig. 7 Ai, enemyiC2 Fig. 9 0° 2 Fig. 2 Procedure supplement 11 Mi fortune telling (method) % formula % 2 8 ladle of invention, Thin film shift register integration-path (t generation to do lllllII!lll1LIa role Tsuneya Nakamura 4th generation person)

Claims (1)

[Claims] In a bootstrap-effect type shift register integration system in which a MO8 capacitor whose capacitance changes depending on the gate voltage and a plurality of MO transistors 4f are configured as a basic unit, the substrate of the 111 MO8 capacitor and the The source, drain, and substrate of a multi-F(m) MO8 transistor are formed of a thin film, and at least one of the plurality of thin 1% 11 MO8 transistors has a common gate. I-7!r! Membrane MO8) Run]/
Stars continued to watch for the first time in a row of thin film transformers.
Continuous shift register integrated circuit with 1r% gap