CN101042937B - Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display - Google Patents

Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display Download PDF

Info

Publication number
CN101042937B
CN101042937B CN 200710101724 CN200710101724A CN101042937B CN 101042937 B CN101042937 B CN 101042937B CN 200710101724 CN200710101724 CN 200710101724 CN 200710101724 A CN200710101724 A CN 200710101724A CN 101042937 B CN101042937 B CN 101042937B
Authority
CN
China
Prior art keywords
gate line
potential
signal
shift register
circuit
Prior art date
Application number
CN 200710101724
Other languages
Chinese (zh)
Other versions
CN101042937A (en
Inventor
张峻荣
张立勋
郑咏泽
陈世烽
陈静茹
Original Assignee
友达光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友达光电股份有限公司 filed Critical 友达光电股份有限公司
Priority to CN 200710101724 priority Critical patent/CN101042937B/en
Publication of CN101042937A publication Critical patent/CN101042937A/en
Application granted granted Critical
Publication of CN101042937B publication Critical patent/CN101042937B/en

Links

Abstract

This invention discloses one displacement register, which comprises one first frequency signal pull down module, one second frequency signal pull down module, one first main pull down module, one second pull down module and one discharge circuit, wherein, when the first and second pull down modules generate abnormal circuit to make the register not capable of discharge, the discharge circuit can proceed to lower the register circuit bias effect.

Description

可降低偏压效应的移位寄存器、控制电路及液晶显示器 Bias effect reduces the shift register, control circuit and a liquid crystal display

技术领域 FIELD

[0001] 本发明涉及一种移位寄存器,尤其是指一种利用一放电电路来降低偏压效应(Stress)与增加输出级(Output Stage)稳态时间的移位寄存器。 [0001] The present invention relates to a shift register, more particularly to a use of a discharge circuit to reduce the bias effect (Stress) and increase the output stage (Output Stage) Stability Time shift register.

背景技术 Background technique

[0002] 功能先进的显示器渐成为现今消费电子产品的重要特色,其中液晶显示器已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记型计算机屏幕所广泛应用具有高分辨率彩色屏幕的显示器。 [0002] features advanced display gradually become an important feature of today's consumer electronics products, including liquid crystal displays have gradually become a variety of electronic devices such as mobile phones, personal digital assistants (PDA), digital camera, computer screen or wide screen notebook computer application display has a high resolution color screen.

[0003] 移位寄存器(shift register)为液晶显示面板的驱动电路中的一重要结构,其用以驱动液晶显示面板中各级显示电路,因此移位寄存器的电路设计对液晶显示面板的效能具有决定性的影响。 [0003] The shift register (shift register) is an important driving circuit structure of the liquid crystal display panel, which circuits for driving the liquid crystal display panel levels, and therefore the shift register circuit design performance of the liquid crystal display panel having a decisive impact.

[0004] 请参阅图1,图1为先前技术的液晶显示器中单级移位寄存器10的电路结构图。 [0004] Referring to FIG. 1, FIG. 1 is a prior art circuit configuration diagram of a liquid crystal display in a single stage of the shift register 10. 该移位寄存器(shift register) 10主要包含一CK频率信号拉低模块(CK pull-down module) 12、一XCK频率信号拉低模块(XCK pull-downmodule) 14与一主要拉低模块(key pull-down module) 16。 The shift register (shift register) 10 mainly includes a down clock signal CK module (CK pull-down module) 12, a clock signal XCK pulled down module 14 with a major (key pull module (XCK pull-downmodule) -down module) 16. CK频率信号与XCK频率信号的相位差为180度。 Clock signal CK and XCK frequency signal phase difference is 180 degrees. CK频率信号拉低模块12由五个晶体管T109、T110、Till、T112、T113组成,当CK频率信号为高电位时(即XCK频率信号为低电位时),晶体管T112与T110被打开,使节点Q(即栅极线,gate line) 与晶体管T102的栅极的电位经由晶体管T110拉低至VSS电位。 CK module 12 by a frequency signal down five transistors T109, T110, Till, T112, T113 composition, when the clock signal CK is high (i.e., the frequency signal XCK is low), transistors T112 and T110 is turned on, so that node gate Q (i.e. gate line, gate line) of the transistor T102 is pulled down to the VSS potential the potential via the transistor T110. XCK频率信号拉低模块14 由六个晶体管T103、T104、T105、T106、T107、T108组成,当XCK频率信号为高电位时(即CK频率信号为低电位时),晶体管T104与T106被打开,使节点Q与晶体管T102的栅极的电位经由晶体管T106拉低至VSS电位。 XCK frequency signal down module 14 composed of six transistors T103, T104, T105, T106, T107, T108 composition, when the clock signal XCK is high (i.e., the frequency signal CK is low), transistors T104 and T106 is turned on, of the node Q and the potential of the gate of the transistor T102 is pulled down to the VSS potential via the transistor T106. 主要拉低模块16由两个晶体管T116、T117组成, 用以在晶体管T101输出一输出信号到节点Q后,迅速将节点Q与晶体管T102的栅极的电位经由晶体管T117拉低至VSS电位。 The main module 16 is pulled down by the two transistors T116, T117 composition, for outputting an output signal of the transistor T101 to node Q, Q quickly gate node of the transistor T102 is pulled down to the VSS potential the potential via the transistor T117. 移位寄存器10另包含一晶体管T121,用以控制输出下一级的驱动节点N+1ST。 The shift register 10 further comprises a transistor T121, the node N + 1ST for driving a control output lower.

[0005] 在先前技术的移位寄存器10中,输出节点N ST负责将驱动信号输出到面板内的相应像素,驱动节点N+1ST则负责将驱动信号输出到下一级移位寄存器。 [0005] In the prior art shift register 10, the output node N ST is responsible for driving the output signal to the corresponding pixels in the panel, the driving node N + 1ST is responsible for outputting the drive signal to the next stage of the shift register. 然而,由于先前技术的移位寄存器10的电路结构,CK频率信号拉低模块12或XCK频率信号拉低模块14可能会随着工作时间的增加,导致其中的晶体管因为偏压效应(Stress)而失效,使整个移位寄存器产生电路误动作,进而导致所对应的面板内像素无法正常运作。 However, since the prior art circuit configuration of the shift register 10, CK signal low frequency clock signal XCK module 12 or module 14 may be pulled with increasing operating time, which results in transistor bias effect because (Stress) and fails, the whole shift register generating circuit malfunction, leading to the inner panel corresponding to the pixel is not working properly.

[0006] 因此,有必要提出一种移位寄存器,其可在CK频率信号拉低模块或XCK频率信号拉低模块发生故障时,仍能有效地降低输出级的偏压效应,使输出级的输出信号迅速到达稳态,以增加输出级稳态时间。 [0006] Accordingly, it is necessary to provide a shift register, which may be modules or down frequency signal XCK pulled low frequency signal CK module failure, can still effectively reduce the bias effect of the output stage, the output stage quickly reach a steady state output signal, the output stage to increase the steady-state time.

发明内容 SUMMARY

[0007] 因此,本发明的主要目的在于提供一种利用一放电电路来降低偏压效应与增加输出级稳态时间的移位寄存器。 [0007] Accordingly, the main object of the present invention is to provide a use of a discharge circuit to reduce the bias effect and increase the output time stage static shift register. [0008] 依据本发明的上述目的,本发明提供一种单级移位寄存器,其包含一包含一第一频率信号拉低模块、一第二频率信号拉低模块、一第一主要拉低模块、一第二主要拉低模块与一放电电路。 [0008] In accordance with the above object of the present invention, the present invention provides a single-stage shift register, comprising a first frequency signal comprises a down module, a second frequency signal down module, a first main module down , down a second primary module and a discharge circuit. 当该第一频率信号拉低模块或第二频率信号拉低模块发生电路异常而使移位寄存器电路无法正常放电时,该放电电路可持续对该移位寄存器电路进行放电,以降低移位寄存器电路的偏压效应。 When the first module or the second frequency signal low frequency signal generating circuit when the module is abnormal down the shift register circuit can not normally discharge, the discharge circuit of the shift register circuit sustainable discharged to reduce the shift register circuit bias effect. 另外,该放电电路的放电速度远小于移位寄存器电路被充电至高电位时的充电速度,故不会影响移位寄存器电路在进行充电时的正常运作。 Further, a discharge rate of the discharge circuit is much smaller than the charging speed of the shift register circuit is charged to a high potential, it will not affect the normal operation of the shift register circuit when charging is performed.

[0009] 该放电电路可为一等效二极管电路,该等效二极管电路可利用栅极与漏极电性连接的一晶体管来实现,其中该晶体管的栅极通道的长度可远小于宽度,以使该放电电路的放电速度远小于移位寄存器电路被充电至高电位时的充电速度。 [0009] The discharging circuit may be a diode equivalent circuit, the equivalent diode circuit may be implemented using a transistor with a gate connected to the drain, wherein the gate length of the transistor channel can be much less than the width of the the discharge speed of the discharge circuit is much smaller than the charging speed of the shift register circuit is charged to a high potential.

[0010] 该放电电路可利用电阻或电容来调节该放电电路的放电速度。 [0010] The discharge circuit discharging speed can be adjusted using the discharge circuit of the resistance or capacitance.

[0011] 本发明的移位寄存器可在第一频率信号拉低模块或第二频率信号拉低模块发生故障时,仍能持续对移位寄存器电路进行放电,可有效地降低输出级的偏压效应,进而使输出级的输出信号迅速到达稳态,使输出级的稳态时间增加。 [0011] The shift register module of the present invention may be down or the second frequency signal in a first frequency signal down a module fails, the shift register circuit can still continue to discharge, can effectively reduce the bias of the output stage effect, the output stage and thus quickly reach a steady state of the output signal, the output stage of the steady-state time increases.

附图说明 BRIEF DESCRIPTION

[0012] 图1为先前技术的单级移位寄存器的电路结构图; [0012] FIG. 1 is a circuit configuration diagram of the previous single-stage shift register technology;

[0013] 图2为一液晶显示器的功能方块图; [0013] FIG. 2 is a functional block diagram of a liquid crystal display;

[0014] 图3为本发明的单级移位寄存器的电路结构图; [0014] FIG 3 a circuit configuration diagram of a single stage of the shift register of the present invention;

[0015] 图4为图3中该移位寄存器各节点的信号时序图; [0015] FIG. 3 FIG. 4 is a signal timing diagram of the shift register of each node;

[0016] 图5为一放电电路的电路示意图; [0016] FIG. 5 is a schematic circuit diagram of a discharge circuit;

[0017] 图6a与图6b为该放电电路的其它实施例的电路示意图。 [0017] The circuit schematic of FIG. 6a and FIG. 6b for discharging circuit other embodiments.

[0018] 其中,附图标记: [0018] wherein reference numerals:

[0019] 200液晶显示器 212液晶显示面板 [0019] 200 liquid crystal display device 212 liquid crystal display panel

[0020] 214栅极驱动器 216源极驱动器 [0020] The gate driver 214 source driver 216

[0021] 220像素单元 222晶体管 [0021] The pixel unit 222 of the transistor 220

[0022] 30移位寄存器 32第一频率信号拉低模块 [0022] 30 of the first shift register 32 signal low frequency module

[0023] 34第二频率信号拉低模块36第一主要拉低模块 [0023] 34 second signal low frequency module 36 of the first main module down

[0024] 38第二主要拉低模块C62、C64电容 [0024] 38 down a second module mainly C62, C64 capacitor

[0025] R60电阻 D300放电电路 [0025] R60 resistor discharging circuit D300

[0026] T301-T334 晶体管 T501-T631 晶体管 [0026] T301-T334 transistors T501-T631 transistor

[0027] T602、T604晶体管 CK第一频率信号 [0027] T602, T604 transistor a first clock signal CK

[0028] XCK第二频率信号 Q、N节点 [0028] XCK second frequency signal Q, N node

具体实施方式 Detailed ways

[0029] 请参阅图2,图2为一液晶显示器200的功能方块图。 [0029] Please refer to FIG. 2, FIG. 2 is a functional block diagram of a liquid crystal display device 200. 液晶显示器200包含一液晶显示面板212、一栅极驱动器(Gate Driver) 214以及一源极驱动器(Source Driver) 216。 The liquid crystal display 200 comprises a liquid crystal display panel 212, a gate driver (Gate Driver) 214 and a source driver (Source Driver) 216. 液晶显示面板212包含多个像素,而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元220构成。 The liquid crystal display panel 212 includes a plurality of pixels, and each pixel includes three pixel units respectively represent red, green and blue (RGB) 220 constituting the three primary colors. 栅极驱动器214输出扫描信号使得每一列的晶体管222依序开启,同时源极驱动器216则输出对应的数据信号至一整列的像素单元220使其充电到各自所需的 The gate driver 214 outputs a scan signal that sequentially each column transistor 222 is turned on, while the source driver 216 outputs data signals to the pixel corresponding to an entire column of cells 220 so as to charge the respective desired

5电压,以显示不同的灰阶。 5 voltage to the different gray scale display. 当同一列充电完毕后,栅极驱动器214便将该列的扫描信号关闭,然后栅极驱动器214再输出扫描信号将下一列的晶体管222打开,再由源极驱动器216 对下一列的像素单元220进行充放电。 When fully charged the same column, the gate driver 214 then the scan signal turns column, and the gate driver 214 then outputs the scan signal to the next column transistor 222 is opened, then the pixel unit 216 next column of the source driver 220 charging and discharging. 如此依序下去,直到液晶显示面板212的所有像素单元220都充电完成,再重头从第一列开始充电。 Sequentially so on until all the pixels of the liquid crystal display panel 212 of the unit 220 are charged, the charging is started over again from the first column. 在目前的液晶显示面板设计中,栅极驱动器214的控制电路等效上为移位寄存器(ShiftRegister),其目的即每隔一固定间隔输出扫描信号至液晶显示面板212。 Panel design, the gate driver control circuit 214 is equivalent to the shift register (ShiftRegister), i.e., it is an object every fixed interval scanning signal to the liquid crystal display panel 212 in the current liquid crystal display.

[0030] 请参阅图3,图3为本发明的一单级移位寄存器30的电路结构图。 [0030] Referring to FIG. 3, a single-stage shift register circuit of FIG. 3 of the present invention. FIG. 30 configuration. 移位寄存器30 为应用于一液晶显示器中以实现上述的栅极驱动器的控制电路。 The shift register 30 is applied to a liquid crystal display to achieve the above-described control of the gate driver circuit. 移位寄存器30包含一第一频率信号拉低模块32、一第二频率信号拉低模块34、一第一主要拉低模块36、一第二主要拉低模块38与一放电电路D300。 The shift register 30 comprises a first frequency signal down module 32, a second signal low frequency module 34, down a first main module 36, a second module 38 with a down main discharge circuit D300. 该第一频率信号与第二频率信号的相位差为180度,该第一频率信号可为一CK频率信号,该第二频率信号可为一XCK频率信号。 The first phase difference signal and the second clock signal frequency is 180 degrees, the first clock signal may be a clock signal CK, the second clock signal may be a clock signal XCK.

[0031] 第一频率信号拉低模块32由五个晶体管T309、T310、T312、T313、T332组成,当第一频率信号为高电位时(即第二频率信号为低电位时),晶体管T312与T310被打开,使节点Q (即栅极线,gate line)与晶体管T302、T331的栅极的电位经由晶体管T310拉低至VSS 电位。 [0031] a first signal low frequency module 32 by the five transistors T309, T310, T312, T313, T332 composition, when the first clock signal is high (i.e., a second clock signal is low), transistor T312 and T310 is turned on, so that node Q (namely, the gate line, gate line) of the transistor T302, T331 potential of the gate potential is pulled down to VSS via the transistor T310. 第二频率信号拉低模块34包含一晶体管T303,当第二时信号为高电位时(即第一频率信号为低电位时),晶体管T303被打开,使节点PIXEL N的电位经由晶体管T303拉低至VSS电位。 Second frequency signal down module 34 comprises a transistor T303, when the second signal is high (i.e., a first clock signal is low), transistor T303 is turned on, the potential of the node PIXEL N down via the transistor T303 to the VSS level. 第一主要拉低模块36由两个晶体管T315、T316组成,用以在第N+1级驱动信号ST N+1输入到晶体管T315、T316的栅极时,使晶体管T315、T316打开,而将节点PIXEL N 的电位经由晶体管T315拉低至VSS电位,并将晶体管T302、T331的栅极电位(节点Q)经由晶体管T316拉低至VSS电位。 The first module 36 consists of two main transistors down the T315, T316 composition for the stage N + 1 N + 1 driving signal ST is input to the transistor the T315, T316 of the gate, the transistor the T315, T316 opened, and the PIXEL N down the potential of the node via the transistor T315 to the VSS level, and the transistors T302, T331 gate potential (node ​​Q) is pulled down to a potential VSS via the transistor T316. 第二主要拉低模块38由两个晶体管T333、T334组成,用以在第N+2级驱动信号ST N+2输入到晶体管T333、T334的栅极时,使晶体管T333、T334打开,而将晶体管T302、T331的栅极电位(节点Q)经由晶体管T333拉低至VSS电位,并将节点STN的电位经由晶体管T334拉低至VSS电位。 The second main module 38 down by two transistors T333, T334 composition for the stage N + 2 N + 2 a drive signal ST is input to the transistors T333, T334 of the gate, the transistors T333, T334 opened, and the transistors T302, T331 gate potential (node ​​Q) via the transistor T333 down to the VSS level, and is pulled down to the potential of the node STN potential VSS via the transistor T334.

[0032] 放电电路D300可视为一等效二极管电路,其利用等效二极管电路将节点Q以顺向偏压的形式连接到VSS电位。 [0032] D300 discharge circuit can be regarded as an equivalent diode circuit, which utilizes a diode equivalent circuit of the node Q is connected to the cis form to the bias potential VSS. 换句话说,放电电路D300利用一等效二极管电路对节点Q进行放电,使节点Q的电位(即晶体管T302、T331的栅极电位)不会因电荷累积而产生偏压效应。 In other words, a discharge circuit D300 using an equivalent diode circuit discharges the node Q, the potential of the node Q (i.e. transistor the T302, T331 gate potential) is not generated by the charge accumulation bias effect. 特别是当第一频率信号拉低模块32或第二频率信号拉低模块34发生电路异常而使节点Q的电位无法正常放电时,放电电路D300可确保晶体管T302、T331不会被打开而维持移位寄存器电路的正常运作。 In particular, when the first frequency signal or the second frequency down module 32 module 34 signal low potential generating circuit node Q of the abnormality can not be normally discharged, the discharge circuit ensures D300 transistors T302, T331 can not be maintained open shift normal operation of the bit register circuit. 请参阅图4,图4为移位寄存器30的各节点的信号时序图。 Please refer to FIG. 4, FIG. 4 is a signal timing diagram of the shift register 30 of the respective nodes. 其中节点Q的电位在时间T2之后即呈低电位,放电电路D300可在时间T3后持续释放节点Q的电荷,使节点Q可保持低电位。 Wherein the potential of the node Q i.e. after the time T2 was low, the discharge circuit D300 sustained release of the node Q may be charged after time T3, the node Q can be kept low.

[0033] 请参阅图5,图5为放电电路D300的电路示意图。 [0033] Referring to FIG. 5, FIG. 5 is a circuit diagram of a discharge circuit D300. 放电电路D300可将一晶体管T520的栅极(Gate)与漏极(Drain)电性导通,即可在节点Q与电位VSS之间形成一呈顺向偏压的二极管电路。 D300 gate discharge circuit may (Gate) a transistor T520 and the drain (Drain) is electrically conductive, it can be formed form a forward biased diode circuit between the node Q and the potential VSS. 然而,当正常的驱动信号(如第N-1级驱动信号ST N-1)输入到晶体管T502、T531的栅极时,节点Q必须保持在高电位,使移位寄存器可正常运作。 However, when a normal driving signal (e.g., the N-1 stage driver signal ST N-1) is input to the gate of the transistor T502, T531, the node Q must be maintained at high level, the shift register can operate normally. 因此,晶体管T520在导通时的放电速度须远小于节点Q被充电至高电位时的充电速度,使节点Q在正常充电时可忽略晶体管T520的放电速度。 Thus, the transistor T520 is turned on when the discharge rate is much less than the required rate when the charging node Q is charged to a high potential of the node Q negligible during normal charging rate discharge transistor T520. 故晶体管T520其栅极通道的长度须远大于宽度。 Therefore, the transistor T520 having a gate length to be much greater than the width of the channel. 在本发明的实施例中,宽长比(Width/Length)设置为约6/240,亦即宽长比约为1/40。 In an embodiment of the present invention, the aspect ratio (Width / Length) is set to about 6/240, i.e. an aspect ratio of about 1/40. 如此一来,节点Q在正常充电时即不会受到晶体管T520的放电速度影响,而可维持移位寄 As a result, the node Q i.e. discharge rate will not be affected transistor T520 during normal charging, and the shift register may be maintained

6存器电路的正常运作;当节点Q须维持在低电位时,则可利用晶体管T520持续进行放电,以降低节点Q的偏压效应并增加移位寄存器输出级的稳态时间。 Normal operation of the memory circuit 6; when the node Q to be maintained at a low level, the transistor T520 may be continued using the discharge, the node Q to reduce the bias effect and increase the time of the steady-state output stage of the shift register.

[0034] 请参阅图6a与图6b,为放电电路D300的其它实施例的电路示意图。 [0034] Referring to FIGS. 6a and 6b, the other embodiments of the discharge circuit is a circuit schematic D300. 在图6a中, 晶体管T602的漏极与源极(Source)之间电性连接一电容C62,电容C62可用以降低整体放电电路的放电速率,以调节放电电路的放电速率。 In Figure 6a, the drain of the transistor T602 and the source electrode between (Source) is electrically connected to a capacitor C62, capacitor C62 may be used to reduce the overall discharge rate of the discharge circuit to adjust the rate of discharge circuit. 在图6b中,晶体管T604的漏极与节点Q(或节点N、Q+N)之间电性连接一电阻R60,并在节点Q与电位VSS之间电性连接一电容C64,电阻R60与电容C64同样可用以降低整体放电电路的放电速率,以调节放电电路的放电速率。 In Figure 6b, the electrical connection between the drain of the transistor Q and the node (or node N, Q + N) T604 is connected to a resistor R60, and between the node Q and the potential VSS is electrically connected to a capacitor C64, and resistor R60 Similarly capacitor C64 may be used to reduce the overall discharge rate of the discharge circuit to adjust the rate of discharge circuit.

[0035] 相较于先前技术,本发明的移位寄存器可在第一频率信号拉低模块或第二频率信号拉低模块发生故障时,仍能持续对节点Q进行放电,可有效地降低输出级的偏压效应,进而使输出级的输出信号迅速到达稳态,使输出级的稳态时间增加。 [0035] Compared to the prior art, the present invention may be a shift register module defect down signal at a first frequency or a second frequency signal down module, still continuing to discharge the node Q, the output can be effectively reduced bias effect level, the output stage and thus quickly reach a steady state of the output signal, the output stage of the steady-state time increases.

[0036] 以上所述仅为本发明的较佳实施方式,本领域的普通技术人员依本发明的精神所作的等效修饰或变化,皆涵盖于后附的权利要求书范围内。 [0036] appended claim above are merely preferred embodiments of the present invention, equivalent modifications and variations to those of ordinary skill in the art made under this spirit of the invention, it is encompassed within the scope of claims.

Claims (21)

  1. 一种移位寄存器,其特征在于,包含:一第一频率信号拉低模块与一栅极线电性连接,用以当一第一频率信号为高电位时,使该栅极线的电位拉低至一低电位;一第二频率信号拉低模块与该栅极线电性连接,用以当一第二频率信号为高电位时,使该栅极线的电位拉低至该低电位;一主要拉低模块与该栅极线电性连接,用以当该栅极线输出一驱动信号后,将该栅极线的电位拉低至该低电位;及一放电电路与该栅极线电性连接,用以将该栅极线连接到该低电位,藉以持续对该栅极线进行放电,并且,该放电电路的放电速度小于该栅极线充电至高电位时的充电速度。 A shift register, wherein, comprising: a first signal low frequency module and a gate line is electrically connected to a first frequency when the signal is at a high potential, the potential of the gate line pull up to a low potential; a second signal low frequency module is connected to the gate line electrically to a second frequency when the signal is at a high potential, the potential of the gate line is pulled down to the low potential; a main module is connected to the down gate line electrically to the gate line when outputting a drive signal pulled down to the potential of the gate line of the low potential; and a discharge circuit and the gate line is electrically connected to the gate line connected to the low level, thereby continuously discharging the gate line, and the discharging speed of the charge-discharge circuit is less than the speed at which the gate line-charged high.
  2. 2.根据权利要求1所述的移位寄存器,其特征在于,该放电电路包含一等效二极管电路,将该栅极线以顺向偏压方式电性连接到该低电位。 The shift register according to claim 1, wherein the discharge circuit comprising an equivalent diode circuit, connected to the gate line to electrically forward biased manner to the low potential.
  3. 3.根据权利要求2所述的移位寄存器,其特征在于,该等效二极管电路为栅极与漏极呈电性连接的晶体管。 3. The shift register according to claim 2, wherein the diode circuit equivalent to the transistor gate and the drain was connected electrically.
  4. 4.根据权利要求3所述的移位寄存器,其特征在于,该晶体管的栅极通道的长度大于宽度的40倍。 The shift register according to claim 3, wherein the channel length of the gate of the transistor is greater than 40 times the width.
  5. 5.根据权利要求1所述的移位寄存器,其特征在于,该放电电路包含电阻或电容组件以调节放电速度。 5. The shift register according to claim 1, wherein the discharge circuit comprises a resistor or capacitor assembly to adjust the rate of discharge.
  6. 6.根据权利要求1所述的移位寄存器,其特征在于,该低电位为一 VSS电位。 The shift register according to claim 1, wherein a potential of the low potential VSS.
  7. 7.根据权利要求1所述的移位寄存器,其特征在于,该第一频率信号与第二频率信号的相位差为180度。 The shift register according to claim 1, wherein the first phase difference signal and the second clock signal frequency is 180 degrees.
  8. 8. —种控制电路应用于一液晶显示器中,其特征在于,包含:多级移位寄存器,其中每一级移位寄存器包含:一第一频率信号拉低模块,用以当一第一频率信号为高电位时,使一栅极线的电位拉低至一低电位;一第二频率信号拉低模块,用以当一第二频率信号为高电位时,使该栅极线的电位拉低至该低电位;一主要拉低模块,用以当该栅极线输出一驱动信号后,将该栅极线的电位拉低至该低电位;及一放电电路,用以将该栅极线连接到该低电位,藉以持续对该栅极线进行放电,并且, 该放电电路的放电速度小于该栅极线充电至高电位时的充电速度。 8. - The control circuit is applied to a kind of liquid crystal displays, characterized by comprising: shift register stages, wherein each stage of the shift register comprising: a first frequency signal down a module for a first frequency when the when the signal is high potential, the potential of a gate line is pulled down to a low potential; a second signal low frequency modules for a second frequency when the signal is at a high potential, the potential of the gate line pull up to the low potential; down a main module, when the gate line for outputting a drive signal pulled down to the potential of the gate line of the low potential; and a discharge circuit for the gate line is connected to the low level, thereby continuously discharging the gate line, and the discharging speed of the charge-discharge circuit is less than the speed at which the gate line-charged high.
  9. 9.根据权利要求8所述的控制电路,其特征在于,该放电电路为一等效二极管电路,将该栅极线以顺向偏压方式电性连接到该低电位。 9. The control circuit of claim 8, wherein the discharge circuit is a diode equivalent circuit along the gate line connected to the low potential to the electrically biased manner.
  10. 10.根据权利要求9所述的控制电路,其特征在于,该等效二极管电路为栅极与漏极呈电性连接的晶体管。 The control circuit of claim 9, wherein the transistor is electrically equivalent diode circuit was connected to the gate and drain.
  11. 11.根据权利要求10所述的控制电路,其特征在于,该晶体管的栅极通道的长度大于宽度的40倍。 The control circuit of claim 10, wherein the channel length of the gate of the transistor is greater than 40 times the width.
  12. 12.根据权利要求8所述的控制电路,其特征在于,该放电电路包含电阻或电容组件以调节放电速度。 The control circuit of claim 8, wherein the discharge circuit comprises a resistor or capacitor assembly to adjust the rate of discharge.
  13. 13.根据权利要求8所述的控制电路,其特征在于,该低电位为一 VSS电位。 The control circuit of claim 8, wherein a potential of the low potential VSS.
  14. 14.根据权利要求8所述的控制电路,其特征在于,该第一频率信号与第二频率信号的相位差为180度。 The control circuit of claim 8, wherein the first phase difference signal and the second clock signal frequency is 180 degrees.
  15. 15. 一种液晶显示器,其特征在于,包含:一液晶显示面板,包含多个像素单元;一栅极驱动器,用以输出扫描信号以驱动该像素单元,该栅极驱动器包含一控制电路, 该控制电路包含复数级移位寄存器,其中每一级移位寄存器包含:一第一频率信号拉低模块,用以当一第一频率信号为高电位时,使一栅极线的电位拉低至一低电位;一第二频率信号拉低模块,用以当一第二频率信号为高电位时,使该栅极线的电位拉低至该低电位;一主要拉低模块,用以当该栅极线输出一驱动信号后,将该栅极线的电位拉低至该低电位;及一放电电路,用以将该栅极线连接到该低电位,藉以持续对该栅极线进行放电,并且, 该放电电路的放电速度小于该栅极线充电至高电位时的充电速度;以及一源极驱动器,用以输出对应的数据信号至该像素单元。 A liquid crystal display comprising: a liquid crystal display panel comprising a plurality of pixel units; a gate driver for outputting the scan signals to drive the pixel unit, the gate driver comprising a control circuit, which the control circuit comprises a plurality of shift register stages, wherein each stage of the shift register comprising: a first frequency signal down a module for a first frequency when the signal is at a high potential, the potential of the gate line is pulled down to a a low potential; a second signal low frequency modules for a second frequency when the signal is at a high potential, the potential of the gate line is pulled down to the low potential; down a main module for when the after a gate line driving signal output, the potential of the gate line is pulled down to the low potential; and a discharge circuit for connecting the gate line to the low level, thereby discharging the gate line continuous and, discharging speed of the discharge circuit is smaller than the charging speed at the gate line charging to a high potential; and a source driver for outputting data signals corresponding to the pixel unit.
  16. 16.根据权利要求15所述的液晶显示器,其特征在于,该放电电路为一等效二极管电路,将该栅极线以顺向偏压方式电性连接到该低电位。 16. The liquid crystal display according to claim 15, wherein the discharge circuit is a diode equivalent circuit along the gate line connected to the low potential to the electrically biased manner.
  17. 17.根据权利要求16所述的液晶显示器,其特征在于,该等效二极管电路为栅极与漏极呈电性连接的晶体管。 17. The liquid crystal display according to claim 16, wherein the diode circuit equivalent to the transistor gate and the drain was connected electrically.
  18. 18.根据权利要求17所述的液晶显示器,其特征在于,该晶体管的栅极通道的长度大于宽度的40倍。 18. The liquid crystal display according to claim 17, wherein the channel length of the gate of the transistor is greater than 40 times the width.
  19. 19.根据权利要求15所述的液晶显示器,其特征在于,该放电电路包含电阻或电容组件以调节放电速度。 19. The liquid crystal display according to claim 15, wherein the discharge circuit comprises a resistor or capacitor assembly to adjust the rate of discharge.
  20. 20.根据权利要求15所述的液晶显示器,其特征在于,该低电位为一 VSS电位。 20. The liquid crystal display according to claim 15, wherein a potential of the low potential VSS.
  21. 21.根据权利要求15所述的液晶显示器,其特征在于,该第一频率信号与第二频率信号的相位差为180度。 21. The liquid crystal display according to claim 15, wherein the first phase difference signal and the second clock signal frequency is 180 degrees.
CN 200710101724 2007-04-24 2007-04-24 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display CN101042937B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200710101724 CN101042937B (en) 2007-04-24 2007-04-24 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200710101724 CN101042937B (en) 2007-04-24 2007-04-24 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display

Publications (2)

Publication Number Publication Date
CN101042937A CN101042937A (en) 2007-09-26
CN101042937B true CN101042937B (en) 2010-10-13

Family

ID=38808349

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200710101724 CN101042937B (en) 2007-04-24 2007-04-24 Displacement register capable of reducing voltage bias effective voltage, control circuit and liquid crystal display

Country Status (1)

Country Link
CN (1) CN101042937B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847445B (en) 2009-03-27 2012-11-21 北京京东方光电科技有限公司 Shift register and grid line driving device thereof
US8605029B2 (en) * 2009-06-25 2013-12-10 Sharp Kabushiki Kaisha Shift register, display device provided with same, and method of driving shift register
US8537094B2 (en) * 2010-03-24 2013-09-17 Au Optronics Corporation Shift register with low power consumption and liquid crystal display having the same
CN102201207B (en) * 2010-03-25 2013-01-02 联咏科技股份有限公司 Method and device for eliminating bias voltage of source driving device of liquid crystal display (LCD)
CN104376826B (en) * 2014-11-20 2017-02-01 深圳市华星光电技术有限公司 Shifting register unit, grid driving circuit and displaying device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000155550A (en) 1998-10-21 2000-06-06 Lg Philips Lcd Co Ltd Shift register
CN1767070A (en) 2005-09-07 2006-05-03 友达光电股份有限公司 Shift register circuit
CN1929031A (en) 2006-09-25 2007-03-14 友达光电股份有限公司 Shifting register reducing bias voltage effect

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000155550A (en) 1998-10-21 2000-06-06 Lg Philips Lcd Co Ltd Shift register
CN1767070A (en) 2005-09-07 2006-05-03 友达光电股份有限公司 Shift register circuit
CN1929031A (en) 2006-09-25 2007-03-14 友达光电股份有限公司 Shifting register reducing bias voltage effect

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CN 1889191 A,全文.

Also Published As

Publication number Publication date
CN101042937A (en) 2007-09-26

Similar Documents

Publication Publication Date Title
US6928135B2 (en) Shift register for pulse-cut clock signal
US6300928B1 (en) Scanning circuit for driving liquid crystal display
US7436923B2 (en) Shift register circuit and image display apparatus containing the same
US9105520B2 (en) Pulse output circuit, shift register and display device
CN100442343C (en) Liquid crystal display apparatus
KR100446460B1 (en) Method and driving circuit for driving liquid crystal display, and portable electronic device
US7627076B2 (en) Shift register circuit and image display apparatus having the same
TWI410944B (en) Shift register of a display device
US6339631B1 (en) Shift register
KR100910562B1 (en) Device of driving display device
US7403586B2 (en) Shift register and image display apparatus containing the same
US7688302B2 (en) Shift register and display device using same
CN100508072C (en) Shift register and method for driving the same
US7136058B2 (en) Display apparatus, digital-to-analog conversion circuit and digital-to-analog conversion method
US7545305B2 (en) Data driver and display device
US10283070B2 (en) Gate driving circuit and display apparatus having the same
US9087596B2 (en) Gate driving circuit on array applied to charge sharing pixel
US7633477B2 (en) Gate driver using a multiple power supplies voltages and having a shift resister
JP5473686B2 (en) Scan line drive circuit
US20080101529A1 (en) Shift register and image display apparatus containing the same
JP5424948B2 (en) Shift register driving method, shift register, and liquid crystal display device including the same
US7528820B2 (en) Driving circuit including shift register and flat panel display device using the same
US20060232577A1 (en) Circuit for signal amplification and use of the same in active matrix devices
US8098791B2 (en) Shift register
CN100389452C (en) Shift register circuit and method of improving stability and grid line driving circuit

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C14 Granted