KR100493385B1 - Circuit for bi-directional driving liquid crystal display panel - Google Patents

Circuit for bi-directional driving liquid crystal display panel Download PDF

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Publication number
KR100493385B1
KR100493385B1 KR20020080711A KR20020080711A KR100493385B1 KR 100493385 B1 KR100493385 B1 KR 100493385B1 KR 20020080711 A KR20020080711 A KR 20020080711A KR 20020080711 A KR20020080711 A KR 20020080711A KR 100493385 B1 KR100493385 B1 KR 100493385B1
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KR
South Korea
Prior art keywords
clock signal
switching
gate
drain
mos
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KR20020080711A
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Korean (ko)
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KR20040053584A (en
Inventor
박재덕
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엘지.필립스 엘시디 주식회사
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Priority to KR20020080711A priority Critical patent/KR100493385B1/en
Publication of KR20040053584A publication Critical patent/KR20040053584A/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0283Arrangement of drivers for different directions of scanning

Abstract

The present invention relates to a bidirectional driving circuit of a liquid crystal display panel capable of bidirectional driving regardless of the number of stages by varying the phase of a clock signal and a method of applying a start pulse. The present invention relates to a driving circuit of a liquid crystal display panel having a plurality of blocks. Each block may include a first switching device to which a source pulse or an output signal of a previous block is applied to a source and a gate, and a second switching source connected to a drain of the first switching device and a clock signal to a gate. A third switching device having a source connected to the drain of the second switching device and a drain connected to a power supply (Vss), a source connected to a power supply (Vdd), a gate connected to another clock signal, and a drain Is a fourth switching device connected to a gate of the third switching device, a source is connected to a drain of the fourth switching device, and a gate is connected to the fourth switching device. A fifth switching device connected to the drain of the second switching device and a source connection terminal of the third switching device and having a drain connected to the Vss terminal, a source connected to the another clock signal, and a gate connected to the drain of the second switching device; A sixth switching device having a drain connected to an output terminal, a source connected to the output terminal, a gate connected to a drain of the fourth switching device and a gate of a third switching device, and a drain connected to the Vss terminal. A seventh switching element, an eighth switching element having a source and a gate connected to an output terminal of a start pulse or the next block, a source connected to a drain of the eighth switching element and a gate connected to the another clock signal; The drain comprises a ninth switching element connected to the drain of the second switching element and the gate of the sixth switching element.

Description

Circuit for bi-directional driving liquid crystal display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a bidirectional driving circuit of a liquid crystal display panel capable of bidirectional driving regardless of the number of stages.

Recently, liquid crystal display devices have built-in driving circuits such as gate drive ICs and data drive ICs in liquid crystal display panels, and the driving directions are fixed. Therefore, different system manufacturers require different panels.

The circuit configuration of the poly-Si liquid crystal display panel in which the driving circuit is incorporated is as shown in FIG. 1.

1 is a circuit diagram illustrating a general polysilicon liquid crystal display panel.

The LCD panel includes a pixel array in which a plurality of gate lines G1 -Gm and data lines D1 -Dn vertically intersect each other, and a plurality of first shift registers for supplying scan signals to the gate lines. 11) and a buffer 12 and a plurality of second shift registers 13 and 14 for driving data lines by dividing each data line into k blocks and having one shift register and a buffer in each block. And a plurality of signal lines (S1-Sn) 15 for transferring driving signals output from the second shift register 13 and the buffer 14 to each data line, and the second shift register 13. And a plurality of switching elements 16 for sequentially applying the image signals of the signal lines S1-Sn to the data lines for each block by the driving signals output from the buffer 14.

As described above, the driving circuit of the polysilicon thin film transistor liquid crystal display panel, unlike the conventional amorphous silicon circuit, divides a plurality of data lines into m blocks while the gate lines are selected to reduce the number of contact lines between the external circuit and the panel. Supplies the display voltage to the data line.

Thus, since the gate lines and the data lines are sequentially driven by the shift registers to display an image, the shift registers are shifted only in one predetermined direction, and thus the freedom of the driving direction required by the system company cannot be provided.

A shift register of a conventional liquid crystal display panel will be described with reference to the accompanying drawings.

2 is a circuit configuration diagram of a shift register of a conventional liquid crystal display panel.

First, a gate or data start pulse VST, four first, second, third, and fourth clock signals CLK1, CLK2, CLK3, and CLK4 having different phases and a power supply voltage are provided at an input terminal of the shift register. Vdd, Vss) are input.

The circuit structure of the shift register is composed of a plurality of blocks (8 blocks), and the structure of each block is almost similar, but there is a difference in the part where the clock signal is applied.

First, the first block includes a first p-MOS TFT1 to which the start pulse VST is applied to a source and a gate, and a source is connected to a drain of the first p-MOS TFT1 and the fourth block. A second p-MOS TFT2 to which a clock signal CLK4 is applied to the gate, and a third p-MOS to which a source is connected to a drain of the second p-MOS TFT2 and whose drain is connected to the Vss terminal. TFT3), a source connected to the Vdd terminal, a gate connected to the third clock signal CLK3, and a drain connected to a gate of the third p-MOS TFT3; A fifth p-MOS TFT5 having a source connected to a drain of the fourth p-MOS TFT4, a gate connected to the start pulse VST, and a drain connected to a Vss terminal, and a source connected to the first A sixth p-MOS TFT6 connected to a clock signal CLK1, a gate connected to a drain of the second p-MOS TFT2, and a drain connected to an output terminal; And a seventh p-MOS TFT7 connected to an output terminal, a gate connected to a drain of the fourth p-MOS TFT4, and a drain connected to the Vss terminal.

Here, the contact of the drain of the first p-MOS (TFT1) and the source of the second p-MOS (TFT2) is grounded through the first capacitor (C1), the gate of the sixth p-MOS (TFT6) The gate and the drain of the sixth p-MOS TFT6 are connected to the Vss terminal through the second capacitor C2, and the gate of the seventh p-MOS TFT7 is connected to the Vss terminal. 4 is connected to the Vss terminal through a capacitor (C4).

The difference from the second to the eighth blocks is that of the clock signal applied to the source of the sixth p-MOS TFT6, the gate of the fourth p-MOS TFT4, and the gate of the second p-MOS TFT2, respectively. There is a difference, and the output terminal of the previous block is connected to the source and gate of the first p-MOS TFT1.

That is, the clock signal connections from the first block to the eighth block are as follows.

First, the clock signal applied to the source of the sixth p-MOS TFT6 includes the first clock signal CLK1 in the first and fifth blocks, the second clock signal CLK2 in the second and sixth blocks, and three. The third clock signal CLK3 is connected in the first and seventh blocks, and the fourth clock signal CLK4 is connected in the fourth and eighth blocks.

The clock signal applied to the gate of the fourth p-MOS TFT4 includes the third clock signal CLK3 in the first and fifth blocks, the fourth clock signal CLK4 in the second and sixth blocks, and the third and the fourth signal. The first clock signal CLK1 is connected in the seventh block, and the second clock signal CLK2 is connected in the fourth and eighth blocks.

The clock signal applied to the gate of the second p-MOS TFT2 includes the fourth clock signal CLK4 in the first and fifth blocks, the first clock signal CLK1 in the second and sixth blocks, and the third and The second clock signal CLK2 is connected in the seventh block, and the third clock signal CLK3 is connected in the fourth and eighth blocks.

The operation of the shift register of the conventional liquid crystal display panel configured as described above is as follows.

3 is an input and output waveform diagram of a conventional liquid crystal display panel shift register.

First, the operation of the first block will be described. When the low level signal of which the start pulse VST is switched on is input, the first p-MOS TFT1 is turned on, and the fourth clock signal CLK4 is turned on. Since the low level signal in the switched on state is input, the second p-MOS TFT2 is also turned on so that the load Q becomes the low level in the switched on state. Accordingly, the sixth p-MOS TFT6 is turned on and the first clock signal CLK1 is transmitted to the output terminal and output. At this time, since the load QB is at the high level of the switched-off state, the seventh p-MOS TFT7 is turned off and thus the Vss voltage is not transmitted to the output terminal.

In the same way, in the second block, since the output of the first block is low level and the first clock signal is low level, the second clock signal CLK2 applied to the source of the sixth p-MOS TFT6 is output.

In this manner, as shown in FIG. 3, the output is sequentially generated from the first block to the eighth block.

However, such a driving circuit of the conventional liquid crystal display panel has the following problems.

That is, in the conventional liquid crystal display panel in which the driving circuit is incorporated, the image can be scanned in only one direction originally designed, and it is impossible to scan in the opposite direction. In other words, since the output is generated first in the last block and the output is not generated last in the first block, when the LCD panel is created, the panel direction is arbitrarily set to landscape or portrait. Can not. Therefore, different system manufacturers require different panels.

The present invention has been made to solve such a problem, and the liquid crystal display panel capable of scanning in the forward direction and the reverse direction without forming a separate input pad, and capable of driving in both directions regardless of the stage of the driving circuit. Its purpose is to provide a bidirectional driving circuit.

The bidirectional driving circuit of the liquid crystal display panel of the present invention for achieving the above object is a driving circuit of a liquid crystal display panel having a plurality of blocks, wherein each block has a start pulse or a previous block at the source and gate. A first switching element to which an output signal is applied, a second switching element to which a source is connected to a drain of the first switching element, and a clock signal to a gate, a source to a drain of the second switching element, and a drain A third switching device connected to a power supply Vss terminal, a source connected to a power supply Vdd terminal, a gate connected to another clock signal, and a drain connected to a gate of the third switching device; A source is connected to the drain of the fourth switching device, a gate is connected to the drain connection of the second switching device and a source connection terminal of the third switching device, and the drain is Vs. a fifth switching device connected to an s stage, a sixth switching device having a source connected to the another clock signal, a gate connected to a drain of the second switching device, and a drain connected to an output terminal; A seventh switching device connected to the output terminal, the gate of which is connected to the drain of the fourth switching device and the third switching device, and the drain of which is connected to the Vss terminal, and a source and a gate of the output pulse of the start pulse or the next block. An eighth switching device connected to the gate, a source connected to a drain of the eighth switching device, a gate connected to the another clock signal, and a drain connected to the drain of the second switching device and the gate of the sixth switching device. It is characterized by being equipped with 9 switching elements.

Here, a first capacitor connected between the gate of the sixth switching device and the Vss terminal, a second capacitor connected between the gate and the drain of the sixth switching device, and between the gate of the seventh switching device and the Vss terminal. And further comprising a third capacitor connected to it.

The block is composed of five, the clock signal applied to the source of the sixth switching element is the first clock signal in the first and fifth blocks, the second clock signal in the second block, the third clock signal in the third block The fourth clock signal is applied in the fourth block, and the clock signals applied to the gates of the fourth switching element are the third clock signal in the first and fifth blocks, the fourth clock signal in the second block, and the third block. In the first clock signal, the second clock signal is applied in the fourth block, the clock signal applied to the gate of the second switching element is the fourth clock signal in the first and fifth blocks, the first clock in the second block Signal, the second clock signal in the third block, the third clock signal in the fourth block is applied, the clock signal applied to the gate of the ninth switching element is the first and the In the second block has a second clock signal, both characteristics As the fourth clock signals, four in the second block first clock signal from the third clock signal, and the third block from the second block is applied.

The block is composed of eight, the clock signal applied to the source of the sixth switching element is the first clock signal in the first and fifth blocks, the second clock signal in the second and sixth blocks, the third and seventh The third clock signal in the block, the fourth clock signal in the fourth and eighth blocks are connected, and the clock signal applied to the gate of the fourth switching element is the third clock signal in the first and fifth blocks, the second and the second clock signal. The fourth clock signal is connected in the sixth block, the first clock signal is connected in the third and seventh blocks, and the second clock signal is connected in the fourth and eighth blocks, and the clock signal applied to the gate of the second switching element is first. The fourth clock signal in the first and fifth blocks, the first clock signal in the second and sixth blocks, the second clock signal in the third and seventh blocks, four times And a third clock signal is connected in an eighth block, and the clock signal applied to the gate of the ninth switching element is a second clock signal in the first and fifth blocks, a third clock signal in the second and sixth blocks, The fourth clock signal in the third and seventh blocks and the first clock signal in the fourth and eighth blocks are connected.

The bidirectional driving circuit of the liquid crystal display panel according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

First, the applicant has applied for a patent for a bidirectional driving circuit of a liquid crystal display panel which enables bidirectional scanning by changing a clock signal phase and a start pulse application method. (See Korean Patent Application No. 2001-9965, US Patent Application No. 10 / 082,125)

4 is a configuration diagram of a bidirectional driving circuit (shift register) of a liquid crystal display panel previously filed by the present applicant.

First, as in the prior art, at the input of the shift register, four first, second, third, and fourth clock signals CLK1, CLK2, CLK3, and CLK4 having different phases from the gate or data start pulse VST are conventionally used. ) And power supply voltages Vdd and Vss are input.

The circuit structure of the shift register is composed of eight blocks, and the structure of each block is almost similar, but there is a difference in the part where the clock signal is applied.

First, the first block includes a first p-MOS TFT1 to which the start pulse VST is applied to a source and a gate, and a source is connected to a drain of the first p-MOS TFT1 and the fourth block. A second p-MOS TFT2 to which a clock signal CLK4 is applied to the gate, and a third p-MOS to which a source is connected to a drain of the second p-MOS TFT2 and whose drain is connected to the Vss terminal. TFT3), a source connected to the Vdd terminal, a gate connected to the third clock signal CLK3, and a drain connected to a gate of the third p-MOS TFT3; And a source is connected to the drain of the fourth p-MOS TFT4, a gate is connected to the drain of the second p-MOS TFT2 and a source connection terminal of the third p-MOS TFTF3, and the drain is Vss. A fifth p-MOS TFT5, a source is connected to the first clock signal CLK1, a gate is connected to a drain of the second p-MOS TFT2, and the drain is an output terminal. A sixth p-MOS (TF6) connected thereto, a source connected to the output terminal, a gate connected to a drain of the fourth p-MOS TFT4 and a gate of a third p-MOS TFT3, and the drain of the Vss A seventh p-MOS TFT7 connected to the stage and an eighth p-MOS TFT8 having a source and a gate connected to an output terminal of the next block and a drain connected to a drain of the first p-MOS TFT1. And a ninth p-MOS TFT9 connected in parallel with the second p-MOS TFT2 and having a gate connected to the second clock signal.

Here, the contact of the drain of the first p-MOS (TFT1) and the source of the second p-MOS (TFT2) and the drain of the eighth p-MOS (TFT8) are grounded through the capacitor (C1), and The gate of the 6 p-MOS TFT6 is connected to the Vss terminal through the second capacitor C2, the gate and the drain of the sixth p-MOS TFT6 are connected through the third capacitor C3, and the seventh The gate of the p-MOS TFT7 is connected to the Vss terminal through the fourth capacitor C4.

The differences from the second to the eighth blocks include the source of the sixth p-MOS TFT6, the gate of the fourth p-MOS TFT4, the gate of the second p-MOS TFT2, and the ninth p-MOS ( There is a difference in the clock signal applied to the gate of the TFT9, and the output terminal of the previous block is connected to the source and gate of the first p-MOS TFT1 and the source of the eighth p-MOS TFT8 of the last block, The start pulse VST is connected to the gate, and the eighth p-MOS TFT8 of the remaining blocks is connected to the output terminal of the next block.

That is, the clock signal connections from the first block to the eighth block are as follows.

First, the clock signal applied to the source of the sixth p-MOS TFT6 includes the first clock signal CLK1 in the first and fifth blocks, the second clock signal CLK2 in the second and sixth blocks, and three. The third clock signal CLK3 is connected in the fourth and seventh blocks, and the fourth clock signal CLK4 is connected in the fourth and eighth blocks.

The clock signal applied to the gate of the fourth p-MOS TFT4 includes the third clock signal CLK3 in the first and fifth blocks, the fourth clock signal CLK4 in the second and sixth blocks, the third and the like. The first clock signal CLK1 is connected in the seventh block, and the second clock signal CLK2 is connected in the fourth and eighth blocks.

The clock signal applied to the gate of the second p-MOS TFT2 includes the fourth clock signal CLK4 in the first and fifth blocks, the first clock signal CLK1 in the second and sixth blocks, the third and the like. The second clock signal CLK2 is connected in the seventh block, and the third clock signal CLK3 is connected in the fourth and eighth blocks.

The clock signal applied to the gate of the ninth p-MOS TFT9 includes the second clock signal CLK2 in the first and fifth blocks, the third clock signal CLK3 in the second and sixth blocks, the third and the like. The fourth clock signal CLK4 is connected in the seventh block, and the first clock signal CLK1 is connected in the fourth and eighth blocks.

The operation of the bidirectional shift register of the liquid crystal display panel is as follows.

5 is a diagram illustrating a forward input and output waveform of the liquid crystal display panel shift register of FIG. 4, and FIG. 6 is a diagram illustrating a reverse input and output waveform of the liquid crystal display panel shift register of FIG. 4.

First, when forward driving is desired, as shown in FIG. 5, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are repeatedly input in order, and when the start pulse is input, 4 Let the clock signal input.

On the other hand, when reverse driving is desired, as shown in FIG. 6, the fourth clock signal, the third clock signal, the second clock signal, and the first clock signal are repeatedly input in order, and when the start pulse is input, the first clock signal. To be entered.

Therefore, when the forward operation of the first block is described, when the start pulse VST is switched on (low level), the first p-MOS TFT1 is turned on, and at this time, the fourth clock signal ( Since the second p-MOS TFT2 is also turned on because the CLK4 is input in the switch-on state (low level), the load Q is in the switched-on state (low level). Therefore, the sixth p-MOS TFT6 is turned on and the first clock signal CLK1 is transmitted to the output terminal and output. At this time, since the load QB is in the switched off state (high level), the seventh p-MOS TFT7 is turned off, and thus the Vss voltage is not transmitted to the output terminal.

In the same way, in the second block, when the output of the first block is at the low level and the first clock signal is at the low level, the sixth p-MOS TFT6 is turned on, so that the second clock signal CLK2 is applied to the source. Is output.

In this manner, as shown in FIG. 5, the output is sequentially generated from the first block to the eighth block.

Conversely, in the reverse direction of operation, since the start pulse VST is input to the switch-on state (low level) signal and the first clock signal is input to the switch-on state (low level) signal, the first p in the first block is used. Since the MOS TFT1 is turned on but the second p-MOS TFT2 is not turned on, the sixth p-MOS TFT6 is not turned on and thus does not output the first clock signal. However, in the eighth block, since the first p-MOS TFT1 and the ninth p-MOS TFT9 are turned on at the same time, the sixth p-MOS TFT6 is turned on to output the fourth clock signal.

In this way, the eighth block is output first. Since the signal output from the eighth block is applied to the eighth p-MOS TFT8 of the seventh block, the fourth clock signal CLK4 becomes the low level of the switched-on state. The ninth p-MOS TFT8 and TFT9 are turned on and the sixth p-MOS TFT6 is turned on to output the third clock signal. In this way, when the start pulse is synchronized with the first clock signal and the clock signal is generated in the order from the fourth clock signal to the first clock signal, the signal is output in the reverse order from the eighth block to the first block signal.

In this way, the forward and reverse scans can be performed without the need for a separate signal or a pin, so that the panel can be mounted according to the system specifications for the manufactured liquid crystal display panel. In other words, it can be applied to both a portrait display or a landcape type display.

However, in the technology previously filed by the present applicant as described above, the shift register has a disadvantage in that the number of stages of the shift register must be a multiple of four. In other words, if the number of shift registers is not a multiple of 4, distortion of the output waveform of the last stage occurs.

FIG. 7 is a configuration diagram of a bidirectional driving circuit having five stages of a shift register in FIG. 4.

When the number of stages of the shift register is five, the first to fourth blocks are the same as in FIG. 4, and there is a difference only in the last fifth block.

That is, the fifth block includes a first p-MOS TFT1 having an output terminal of the previous block connected to a source and a gate, and a source connected to a drain of the first p-MOS TFT1 and having a fourth source. A second p-MOS TFT2 to which a clock signal CLK4 is applied to the gate, and a third p-MOS to which a source is connected to a drain of the second p-MOS TFT2 and whose drain is connected to the Vss terminal. TFT3), a source connected to the Vdd terminal, a gate connected to the third clock signal CLK3, and a drain connected to a gate of the third p-MOS TFT3; And a source is connected to the drain of the fourth p-MOS TFT4, a gate is connected to the drain of the second p-MOS TFT2 and a source connection terminal of the third p-MOS TFTF3, and the drain is Vss. A fifth p-MOS TFT5 connected to the source, a source connected to the first clock signal CLK1, a gate connected to a drain of the second p-MOS TFT2, and the drain connected to an output terminal ( A sixth p-MOS (TF6) connected to an output, a source connected to the output terminal, a gate connected to a drain of the fourth p-MOS (TFT4) and a gate of a third p-MOS (TFT3), and a drain A seventh p-MOS TFT7 connected to the Vss terminal, an eighth p- source having a source and a gate connected to the start pulse VST, and a drain connected to a drain of the first p-MOS TFT1; A MOS TFT8 and a ninth p-MOS TFT9 connected in parallel with the second p-MOS TFT2 and having a gate connected to the second clock signal are configured.

Here, the contact of the drain of the first p-MOS (TFT1) and the source of the second p-MOS (TFT2) and the drain of the eighth p-MOS (TFT8) are grounded through the capacitor (C1), and The gate of the 6 p-MOS TFT6 is connected to the Vss terminal through the second capacitor C2, the gate and the drain of the sixth p-MOS TFT6 are connected through the third capacitor C3, and the seventh The gate of the p-MOS TFT7 is connected to the Vss terminal through the fourth capacitor C4.

Thus, the operation of the bidirectional driving circuit composed of five stages of the shift register is as follows.

8 is a diagram illustrating a forward input and output waveform of the liquid crystal display panel shift register of FIG. 7 and FIG. 9 is a diagram illustrating a reverse input and output waveform of the liquid crystal display panel shift register of FIG. 7.

First, when forward driving is desired, as shown in FIG. 8, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are repeatedly input, and when the start pulse is input, 4 Let the clock signal input.

On the other hand, when the reverse driving is desired, as shown in FIG. 9, the fourth clock signal, the third clock signal, the second clock signal, and the first clock signal are repeatedly input in order, and when the start pulse is input, the second clock signal is input. To be entered.

As can be seen from Fig. 8, in the circuit composed of five shift registers, two output waveforms of the last fifth shift register appear when forward driving is applied.

This occurs because the fifth shift register has the same structure as the first shift register.

That is, in the first block, when the start pulse VST is switched on (low level), the first p-MOS TFT1 is turned on, and at this time, the fourth clock signal CLK4 is switched on. Since the state (low level) signal is input, the second p-MOS TFT2 is also turned on so that the load Q is in the switched on state (low level). Therefore, the sixth p-MOS TFT6 is turned on and the first clock signal CLK1 is transmitted to the output terminal and output. At this time, since the load QB is in the switched off state (high level), the seventh p-MOS TFT7 is turned off, and thus the Vss voltage is not transmitted to the output terminal.

At the same time, the start pulse (switch-on state (low level) is also input to the fifth block (shift register) through the eighth p-MOS TFT8, and at this time, the fourth clock signal CLK4 is switched on (low level). ), The second p-MOS TFT2 is also turned on so that the load Q is switched on (low level), so the sixth p-MOS TFT6 is turned on and the first clock signal is turned on. CLK1 is delivered to the output and output.

Therefore, two outputs are generated in the fifth block during forward driving.

Similarly, in the circuit composed of five shift registers, it can be observed from FIG. 9 that even when the reverse driving is applied, two output waveforms of the last first shift register appear.

As described above, the previously-applied technology can operate only when the shift register has a multiple of four. Therefore, a bidirectional driving circuit capable of driving in both directions regardless of the number of shift registers is proposed as follows.

10 is a bidirectional driving circuit diagram of a liquid crystal display device according to the present invention.

First, at the input of the shift register, a gate or data start pulse VST, four first, second, third and fourth clock signals CLK1, CLK2, CLK3, and CLK4 having different phases and a power supply. Voltages Vdd and Vss are input.

The circuit structure of the shift register is composed of five blocks, and the structure of each block is almost similar, but there is a difference in the part where the clock signal is applied.

First, the first block includes a first p-MOS TFT1 to which the start pulse VST is applied to a source and a gate, and a source is connected to a drain of the first p-MOS TFT1 and the fourth block. A second p-MOS TFT2 to which a clock signal CLK4 is applied to the gate, and a third p-MOS to which a source is connected to a drain of the second p-MOS TFT2 and whose drain is connected to the Vss terminal. TFT4 and a fourth p-MOS having a source connected to the power supply Vdd terminal, a gate connected to the third clock signal CLK3, and a drain connected to a gate of the third p-MOS TFT3. TFT4), a source is connected to the drain of the fourth p-MOS (TFT4), the gate is connected to the drain of the second p-MOS (TFT2) and the source connection terminal of the third p-MOS (FTF3), drain A fifth p-MOS TFT5 connected to the Vss terminal, a source connected to the first clock signal CLK1, a gate connected to a drain of the second p-MOS TFT2, and a drain connected to an output terminal ( A sixth p-MOS (TF6) connected to an output, a source connected to the output terminal, a gate connected to a drain of the fourth p-MOS (TFT4) and a gate of a third p-MOS (TFT3), and a drain A seventh p-MOS TFT7 connected to the Vss terminal, an eighth p-MOS TFT8 having a source and a gate connected to an output terminal of a next block, and a source of the eighth p-MOS TFT8; A ninth p-MOS TFT9 connected to a drain of the second clock signal and a drain connected to a drain of a second p-MOS TFT2 and a gate of a sixth p-MOS TFT6. It is provided with.

Here, the gate of the sixth p-MOS TFT6 is connected to the Vss terminal through the first capacitor C1, and the gate and the drain of the sixth p-MOS TFT6 are connected to each other through the second capacitor C2. The gate of the seventh p-MOS TFT7 is connected to the Vss terminal through the third capacitor C3.

The differences from the second to the fifth blocks include the source of the sixth p-MOS TFT6, the gate of the fourth p-MOS TFT4, the gate of the second p-MOS TFT2, and the ninth p-MOS ( There is a difference in the clock signal applied to the gate of the TFT9, and the output terminal of the previous block is connected to the source and gate of the first p-MOS TFT1 and the source of the eighth p-MOS TFT8 of the last block, The start pulse VST is connected to the gate, and the eighth p-MOS TFT8 of the remaining blocks is connected to the output terminal of the next block.

That is, the clock signal connections from the first to fifth blocks are as follows.

First, the clock signal applied to the source of the sixth p-MOS TFT6 is the first clock signal CLK1 in the first and fifth blocks, the second clock signal CLK2 in the second block, and the third block. The third clock signal CLK3 and the fourth clock signal CLK4 are applied in the fourth block.

The clock signal applied to the gate of the fourth p-MOS TFT4 is the third clock signal CLK3 in the first and fifth blocks, the fourth clock signal CLK4 in the second block, and the first block in the third block. The clock signal CLK1 and the second clock signal CLK2 are applied in the fourth block.

The clock signal applied to the gate of the second p-MOS TFT2 is the fourth clock signal CLK4 in the first and fifth blocks, the first clock signal CLK1 in the second block, and the second in the third block. The clock signal CLK2 is connected to the third clock signal CLK3 in the fourth block.

The clock signal applied to the gate of the ninth p-MOS TFT9 is the second clock signal CLK2 in the first and fifth blocks, the third clock signal CLK3 in the second block, and the fourth in the third block. The clock signal CLK4 is connected to the first clock signal CLK1 in the fourth block.

As described above, when composed of five blocks (shift registers), the source of the sixth p-MOS (TFT6) of each block, the gate of the fourth p-MOS (TFT4), the second p-MOS (TFT2) The clock signals applied to the gate of and the gate of the ninth p-MOS TFT9 are as described above.

And, if composed of eight blocks, although not shown in the figure, the source of the sixth p-MOS (TFT6), the gate of the fourth p-MOS (TFT4) of each block, the second p-MOS (TFT2) The clock signals applied to the gates of the gates and the gates of the ninth p-MOS TFT9 are equally applied to the first and fifth, second and sixth, third and seventh, and fourth and eighth gates.

The operation of the bidirectional shift register of the liquid crystal display panel is as follows.

FIG. 11 is a diagram illustrating a forward input and output waveform of the liquid crystal display panel shift register of FIG. 10 and FIG. 12 is a diagram illustrating a reverse input and output waveform of the liquid crystal display panel shift register of FIG. 10.

First, when forward driving is desired, as shown in FIG. 11, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are repeatedly input in order, and when the start pulse is input, 4 Let the clock signal input.

On the other hand, when reverse driving is desired, as shown in FIG. 12, the fourth clock signal, the third clock signal, the second clock signal, and the first clock signal are repeatedly input in order, and when the start pulse is input, the second clock signal is input. To be entered.

Therefore, when the forward operation of the first block is described, when the start pulse VST is switched on (low level), the first p-MOS TFT1 is turned on, and at this time, the fourth clock signal ( Since the second p-MOS TFT2 is also turned on because the CLK4 is input in the switch-on state (low level), the load Q is in the switched-on state (low level). Therefore, the sixth p-MOS TFT6 is turned on and the first clock signal CLK1 is transmitted to the output terminal and output. At this time, since the load QB is in the switched off state (high level), the seventh p-MOS TFT7 is turned off, and thus the Vss voltage is not transmitted to the output terminal.

In the same way, in the second block, when the output of the first block is at the low level and the first clock signal is at the low level, the sixth p-MOS TFT6 is turned on, so that the second clock signal CLK2 is applied to the source. Is output.

In the fifth block, which is the last block, when the start pulse VST is switched on (low level), the ninth p-MOS TFT9 is turned on even if the eighth p-MOS TFT8 is turned on. Since the second clock signal CLK2 is input to the switch off state (high level) signal, the ninth p-MOS TFT9 is also turned off, so that the load Q is in the switch off state (high level). Thus, the sixth p-MOS TFT6 is turned off. Therefore, in the fifth block, there is no output signal when the start signal is input, and since the output is generated only when the output of the previous block is applied to the first p-MOS TFT1, a normal output waveform is generated. .

In this manner, as illustrated in FIG. 11, output is sequentially generated from the first block to the fifth block.

Conversely, in the reverse direction of operation, since the start pulse VST is input to the switch-on state (low level) signal and the second clock signal is input to the switch-on state (low level) signal, the first p in the first block is used. Since the MOS TFT1 is turned on but the second p-MOS TFT2 is not turned on, the sixth p-MOS TFT6 is not turned on and thus does not output the first clock signal. However, in the fifth block, since the eighth p-MOS TFT1 and the ninth p-MOS TFT9 are turned on at the same time, the sixth p-MOS TFT6 is turned on to output the first clock signal.

In this way, the fifth block is output first. The signal output from the fifth block is applied to the eighth p-MOS TFT8 of the fourth block, and the first clock signal CLK1 becomes the low level of the switched-on state. The ninth p-MOS TFT8 and TFT9 are turned on and the sixth p-MOS TFT6 is turned on to output the fourth clock signal. In this way, if the start pulse is synchronized with the second clock signal and the clock signal is generated in the order from the first clock signal to the fourth and third clock signals, the signal is output in the reverse order from the fifth block to the first block. do.

As described above, the bidirectional driving circuit of the liquid crystal display panel according to the present invention has the following effects.

According to the present invention, since the shift register is operated in both directions, the liquid crystal display panel can be driven in both directions even when the same liquid crystal display panel is used.

Therefore, the system may be manufactured without limiting the position and orientation of the liquid crystal display panel in which the driving circuit is embedded, depending on the system company.

In addition, the LCD panel may be driven in both directions even without a separate input pin.

Since the operation is possible even if the number of stages of the driving circuit is not a multiple of four, the driving circuit can be driven in both directions regardless of the number of stages.

1 is a circuit diagram of a general liquid crystal display panel

2 is a circuit diagram illustrating a conventional liquid crystal display panel shift register.

3 is an input and output waveform diagram of a conventional liquid crystal display panel shift register.

4 is a circuit diagram illustrating a liquid crystal display panel shift register filed by the applicant.

5 is a diagram illustrating a forward input and output waveform of the LCD shift register according to FIG. 4.

6 is a diagram illustrating reverse input and output waveforms of the LCD shift register according to FIG. 4.

7 is a circuit diagram illustrating a liquid crystal display panel shift register having five stages in FIG. 4.

8 is a diagram illustrating a forward input and output waveform of the liquid crystal display panel shift register of FIG. 7.

FIG. 9 is a diagram illustrating reverse input and output waveforms of the liquid crystal display panel shift register of FIG. 7; FIG.

10 is a circuit diagram illustrating a liquid crystal display panel shift register according to an exemplary embodiment of the present invention.

11 is a diagram illustrating a forward input and output waveform of the liquid crystal display panel shift register of FIG. 10.

12 is a diagram illustrating reverse input and output waveforms of the liquid crystal display panel shift register of FIG. 10.

Claims (5)

  1. In a driving circuit of a liquid crystal display panel having a plurality of blocks,
    Each block,
    A first switching element to which a source pulse or an output signal of the previous block is applied to the source and the gate;
    A second switching device having a source connected to the drain of the first switching device and a clock signal applied to a gate;
    A third switching device having a source connected to a drain of the second switching device and a drain connected to a first input power source;
    A fourth switching device having a source connected to a second input power source, a gate connected to another clock signal, and a drain connected to a gate of the third switching device;
    A fifth switching device having a source connected to the drain of the fourth switching device, a gate connected to the drain connection of the second switching device and a source connection terminal of the third switching device, and a drain connected to the first input power source;
    A sixth switching device having a source connected to the another clock signal, a gate connected to a drain of the second switching device, and a drain connected to an output terminal;
    A seventh switching device having a source connected to the output terminal, a gate connected to a drain of the fourth switching device and a gate of a third switching device, and a drain connected to the first input power source;
    An eighth switching element having a source and a gate connected to an output terminal of the start pulse or the next block,
    A source connected to the drain of the eighth switching element, a gate connected to the another clock signal, and a drain having a ninth switching element connected to the drain of the second switching element and the gate of the sixth switching element. A bidirectional drive circuit of a liquid crystal display panel.
  2. The method of claim 1,
    A first capacitor connected between the gate of the sixth switching element and the first input power source;
    A second capacitor connected between the gate and the drain of the sixth switching element;
    And a third capacitor connected between the gate of the seventh switching element and the first input power source.
  3. The method of claim 1,
    The block is composed of five,
    The clock signal applied to the source of the sixth switching element is a first clock signal in the first and fifth blocks, a second clock signal in the second block, a third clock signal in the third block, and a fourth clock in the fourth block. Signal is applied,
    The clock signals applied to the gates of the fourth switching element are the third clock signal in the first and fifth blocks, the fourth clock signal in the second block, the first clock signal in the third block, and the second clock in the fourth block. Signal is applied,
    The clock signals applied to the gates of the second switching element are the fourth clock signal in the first and fifth blocks, the first clock signal in the second block, the second clock signal in the third block, and the third clock in the fourth block. Signal is applied,
    The clock signals applied to the gates of the ninth switching elements are the second clock signal in the first and fifth blocks, the third clock signal in the second block, the fourth clock signal in the third block, and the first clock in the fourth block. A bidirectional driving circuit of a liquid crystal display panel, characterized in that the signal is applied.
  4. The method of claim 1,
    The block consists of eight,
    The clock signal applied to the source of the sixth switching element includes a first clock signal in the first and fifth blocks, a second clock signal in the second and sixth blocks, a third clock signal in the third and seventh blocks, and four. The fourth clock signal is connected in the first and eighth blocks,
    The clock signal applied to the gate of the fourth switching element may be a third clock signal in the first and fifth blocks, a fourth clock signal in the second and sixth blocks, a first clock signal in the third and seventh blocks, and four. The second clock signal is connected in the first and eighth blocks,
    The clock signal applied to the gate of the second switching element may be a fourth clock signal in the first and fifth blocks, a first clock signal in the second and sixth blocks, a second clock signal in the third and seventh blocks, and four. The third clock signal is connected in the first and eighth blocks,
    The clock signal applied to the gate of the ninth switching element may be a second clock signal in the first and fifth blocks, a third clock signal in the second and sixth blocks, a fourth clock signal in the third and seventh blocks, and four. A bidirectional driving circuit of a liquid crystal display panel, characterized in that the first clock signal is connected in the first and eighth blocks.
  5. The method of claim 1,
    Wherein each switching element comprises a p-MOS.
KR20020080711A 2002-12-17 2002-12-17 Circuit for bi-directional driving liquid crystal display panel KR100493385B1 (en)

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KR20020080711A KR100493385B1 (en) 2002-12-17 2002-12-17 Circuit for bi-directional driving liquid crystal display panel
US10/453,651 US7038643B2 (en) 2002-12-17 2003-06-04 Bi-directional driving circuit for liquid crystal display device
JP2003188013A JP3955553B2 (en) 2002-12-17 2003-06-30 Bidirectional drive circuit for liquid crystal display panel
TW92119045A TWI259919B (en) 2002-12-17 2003-07-11 Bi-directional driving circuit for liquid crystal display device
CNB031499198A CN1317690C (en) 2002-12-17 2003-07-30 Bidirectional drive circuit of liquid crystal displaying apparatus
DE2003137530 DE10337530B4 (en) 2002-12-17 2003-08-14 Bidirectional driver circuit for a liquid crystal display

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KR (1) KR100493385B1 (en)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8063860B2 (en) 2006-08-01 2011-11-22 Samsung Electronics Co., Ltd. Display device
KR101155895B1 (en) 2006-02-20 2012-06-21 삼성모바일디스플레이주식회사 Light emitting display and driving method thereof
CN104766576A (en) * 2015-04-07 2015-07-08 深圳市华星光电技术有限公司 GOA circuit based on P type thin film transistors

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012972B1 (en) * 2003-12-30 2011-02-10 엘지디스플레이 주식회사 Active matrix display device
KR101110133B1 (en) * 2004-12-28 2012-02-20 엘지디스플레이 주식회사 Shift register for LCD
KR101127813B1 (en) * 2004-12-29 2012-03-26 엘지디스플레이 주식회사 Shift register and liquid crystal display using the same
KR100714003B1 (en) * 2005-08-22 2007-05-04 삼성에스디아이 주식회사 shift resister circuit
JP4846348B2 (en) * 2005-11-18 2011-12-28 パナソニック液晶ディスプレイ株式会社 Display device
KR101197058B1 (en) * 2006-02-20 2012-11-06 삼성디스플레이 주식회사 Driving apparatus of display device
US8164562B2 (en) 2006-10-24 2012-04-24 Samsung Electronics Co., Ltd. Display device and driving method thereof
CN101783124B (en) * 2010-02-08 2013-05-08 北京大学深圳研究生院 Grid electrode driving circuit unit, a grid electrode driving circuit and a display device
CN101789213A (en) * 2010-03-30 2010-07-28 友达光电股份有限公司 Shift register circuit and grid electrode driving circuit
JP6009153B2 (en) * 2011-10-06 2016-10-19 株式会社ジャパンディスプレイ Display device
CN103928002B (en) 2013-12-31 2016-06-15 厦门天马微电子有限公司 A kind of gate driver circuit and indicating meter

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0581913B2 (en) * 1984-07-23 1993-11-16 Sharp Kk
DE4307177C2 (en) 1993-03-08 1996-02-08 Lueder Ernst Circuit arrangement as part of a shift register for controlling chain or matrix-shaped switching elements
JP3329008B2 (en) * 1993-06-25 2002-09-30 ソニー株式会社 Bidirectional signal transmission network and bidirectional signal transfer shift register
JP3272209B2 (en) * 1995-09-07 2002-04-08 アルプス電気株式会社 LCD Drive circuit
JPH09311667A (en) * 1996-05-23 1997-12-02 Matsushita Electron Corp Liquid crystal display device
US5859630A (en) * 1996-12-09 1999-01-12 Thomson Multimedia S.A. Bi-directional shift register
KR100242244B1 (en) * 1997-08-09 2000-02-01 구본준 Scanning circuit
JP3077650B2 (en) * 1997-10-27 2000-08-14 日本ビクター株式会社 Active matrix liquid crystal panel drive
JP3488085B2 (en) * 1998-05-25 2004-01-19 シャープ株式会社 Liquid crystal display device and driving method thereof
JP4043112B2 (en) * 1998-09-21 2008-02-06 東芝松下ディスプレイテクノロジー株式会社 Liquid crystal display device and driving method thereof
DE19950860B4 (en) * 1998-10-21 2009-08-27 Lg Display Co., Ltd. Shift register
JP3659103B2 (en) * 1999-12-28 2005-06-15 セイコーエプソン株式会社 Electro-optical device, driving circuit and driving method of electro-optical device, and electronic apparatus
JP2002140028A (en) * 2000-10-31 2002-05-17 Sony Corp Display device, its driving method, and image pickup device
TW525139B (en) * 2001-02-13 2003-03-21 Samsung Electronics Co Ltd Shift register, liquid crystal display using the same and method for driving gate line and data line blocks thereof
KR100788391B1 (en) 2001-02-27 2007-12-31 엘지.필립스 엘시디 주식회사 Circuit for bi-directional driving liquid crystal display panel

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101155895B1 (en) 2006-02-20 2012-06-21 삼성모바일디스플레이주식회사 Light emitting display and driving method thereof
US8063860B2 (en) 2006-08-01 2011-11-22 Samsung Electronics Co., Ltd. Display device
CN104766576A (en) * 2015-04-07 2015-07-08 深圳市华星光电技术有限公司 GOA circuit based on P type thin film transistors
CN104766576B (en) * 2015-04-07 2017-06-27 深圳市华星光电技术有限公司 GOA circuits based on P-type TFT

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CN1508770A (en) 2004-06-30
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TWI259919B (en) 2006-08-11
US20040113878A1 (en) 2004-06-17
TW200411258A (en) 2004-07-01
US7038643B2 (en) 2006-05-02
CN1317690C (en) 2007-05-23
JP2004199025A (en) 2004-07-15
DE10337530A8 (en) 2005-04-07
DE10337530B4 (en) 2009-01-29
DE10337530A1 (en) 2004-07-15

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