KR20100048445A - Gate driving unit for liquid crystal display device - Google Patents

Abstract

PURPOSE: A gate driving unit for a liquid crystal display device is provided to secure a rapid response while reducing power consumption in generating a gate driving signal. CONSTITUTION: A gate driving unit outputs a plurality of gate drive signals successively. A source driver is synchronized with the gate drive signal and outputs image data to the liquid crystal panel. A timing control part supplies a plurality of control signals. A plurality of stages outputs the gate drive signal. A level shifter outputs a gate high voltage or a gate low voltage. Charge share circuit parts(210,220) shares charge of a pair of stage outputs according to a common control signal.

Description

Gate driving unit for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver of a liquid crystal display and a driving method thereof, and more particularly to a gate driver capable of reducing the amount of current consumed when generating a gate drive signal through charge sharing in a gate driver of a liquid crystal display. will be.

Among the display devices, in particular, liquid crystal displays have advantages of small size, thinness, and low power consumption, and are used as notebook computers, office automation devices, and audio / video devices.

FIG. 1 is a block diagram illustrating a general liquid crystal display device 100. For the convenience of description, only the liquid crystal display panel 110, the plurality of source drivers SD1 to SD4, and the plurality of gate drivers GD1 to GD4. Shown.

In the liquid crystal display panel 110, a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn are formed to cross each other on a substrate using glass or the like, and are switched to the crossing regions. A thin film transistor TFT, a liquid crystal Clc, and a storage capacitor Cst are provided to define a pixel.

The pixels are formed in a matrix form in each region where the plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn cross each other, and are arranged in a matrix form, and image data is written to the plurality of pixels to display an image. This area is called an active area (A / A).

Each of the plurality of source drivers SD1 to SD4 outputs the image data D to the plurality of data lines DL1 to Dlm and provides the image data D to the liquid crystal display panel 110, thereby providing the plurality of gate drivers GD1. Each of the ~ GD4 outputs the gate driving signal Vg sequentially to the respective gate lines GL1 to GLn to control the switching of the thin film transistor TFT configured in each pixel to write the image data D to the pixel. To display an image.

In this case, each of the plurality of gate drivers GD1 to GD4 may be manufactured as a separate integrated circuit IC or may be formed at the periphery of the active area A / A of the substrate when the thin film transistor TFT is formed. It is also manufactured by a gate-in-panel (GIP) method.

Of course, the general liquid crystal display device provides image data and a plurality of control signals to the plurality of source driving units SD1 to SD4 in addition to the above-described configuration, and also provides the gate driving signals to the plurality of gate driving units GD1 to GD4. A timing controller for providing a plurality of control signals including a gate output enable (GOE) signal indicating the output of Vg), and a gamma reference voltage generator for providing gamma reference voltages to the plurality of source drivers SD1 to SD4. The apparatus may further include a backlight unit unit for supplying light to the liquid crystal display panel 110 and a power supply unit for providing an operating voltage of each component unit.

The gate driving units GD1 to GD4 of the liquid crystal display having such a configuration require high power consumption in outputting the gate driving signal Vg having a voltage variation range of about 20 to 30V. It demonstrates in detail.

In the above configuration, each of the gate drivers GD1 to GD4 includes a plurality of stages that serve as shift registers so that the gate driving signals {Vg (1), Vg (2), .., Vg (n)} is sequentially output, and FIG. 2 is a diagram illustrating a configuration of such a gate driver.

According to the configuration, a plurality of stages {stg (1) to stg (n)} outputting a plurality of gate driving signals {Vg (1), Vg (2), ..., Vg (n)} are cascaded, A plurality of clock signals CLK1 to CLK4 are provided to sequentially generate the gate driving signals Vg (1), Vg (2), ..., Vg (n).

At this time, each of the {stg (1) to stg (n)} is sequentially applied with one clock signal selected from the plurality of clock signals CLK1 to CLK4, and although not shown, the respective stages {stg (1) to stg). (n)}, the driving voltage VDD and the ground voltage VSS are supplied separately.

The operation principle of the gate driver of FIG. 2 will be briefly described with reference to the signal timing diagram of FIG. 3. The initial stage {stg (1)} is generated by the start signal Vst input to the initial stage {stg (1)}. The driving is started from each stage, and each stage outputs one gate driving signal Vg during one frame display period of the liquid crystal panel according to the clock signal selected among the four clock signals CLK1 to CLK4 that are cyclically input. .

These outputs are generated in sequence according to the order of the stage connection, and the output of any S-th stage is input as a start signal for driving the S + 1st stage (or S + 2th stage, where S is a natural number), and any S The second (S is a natural number) stage performs reset driving to prepare for display of the next frame by receiving the output of the S + 2th stage.

At this time, there is a reset time Trst for resetting a stage operation between the first clock signal CLK1 and the third clock signal CLK3, and of course, the second clock signal CLK2 and the fourth clock signal CLK4. In addition, it drives with this reset time (Trst).

Each stage of the gate driver performing such a configuration and operation, referring to FIG. 4, a level shifter for generating a gate high voltage Vgh and a gate low voltage Vgl constituting the gate driving signal Vg. shifter) 10.

The level shifter 10 receives a voltage source (Vgh-source) for generating the gate high voltage (Vgh) and a voltage source (Vgl-source) for generating the gate low voltage (Vgl), respectively. Pull-up or pull-down outputs, wherein the level shifter 10 illustrated in FIG. 4 is just one example of a PMOS switch SW1 and an NMOS switch SW2. Configuration is possible.

However, the gate driving signal Vg output through the level shifter 10 circuit as described above typically has the gate high voltage Vgh of about 25V and the gate low voltage Vgl of about -5V. In this case, there is a disadvantage in that a high power consumption is required because the variation range between the voltages is about 30V.

The present invention has been made to solve the above problems, an object of the present invention is to reduce the power consumed when generating the gate drive signal (Vg) in the gate driver.

In order to achieve the above object, the present invention provides a gate driver for sequentially outputting a plurality of gate driver signals, a source driver for outputting image data to the liquid crystal panel in synchronization with the gate driver signal, the gate driver and the source driver. A gate driver of a liquid crystal display device having a timing controller for providing a plurality of control signals for controlling a signal, wherein the gate driver includes one of a plurality of clock signals and outputs the gate driving signal including a gate high voltage and a gate low voltage. A stage of; A level shifter configured in each stage to amplify an input clock signal to output the gate high voltage or the gate low voltage; A charge sharing circuit unit configured between a pair of stages each receiving the clock signal at a time that does not overlap each other among the plurality of stages, and performing charge sharing on the output of the pair of stages according to a sharing control signal; A gate driver of a liquid crystal display device is proposed.

In the gate driver, the plurality of clock signals may include first clock signals and fourth clock signals applied at different timings.

In the gate driver, the first clock signal and the third clock signal are applied at a time that does not overlap each other, and the second clock signal and the fourth clock signal are applied at a time that does not overlap each other. do.

In the gate driver, the charge sharing circuit unit is configured between output stages of the level shifters respectively configured in the pair of stages.

In the gate driver, the charge sharing circuit unit may be configured between odd-numbered stages and even-numbered stages of the plurality of stages, respectively.

In the gate driver, the charge sharing circuit unit includes a first switch and a second switch that are switched and controlled by the sharing control signal, wherein the first switch and the second switch are each a level shifter configured in the pair of stages. Characterized in that the output of the input.

In the gate driver, the first switch and the second switch may be configured of a PMOS transistor and an NMOS transistor, respectively.

In the gate driver, the shared control signal may use one of the plurality of control signals.

According to the present invention having the above characteristics, it is possible to reduce the power consumed when generating the gate drive signal and to ensure a fast response time, thereby providing a higher quality liquid crystal display device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a diagram illustrating a configuration of a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention, wherein the gate driver signals Vg (1), Vg (2), .., Vg (n are provided through a shift register. }) Is composed of a plurality of stages (stg (1) ~ stg (n)), the first charge sharing circuit unit 210 and the second charge sharing circuit unit 220 is sequentially output.

According to the configuration, a plurality of stages {stg (1) to stg (n)} outputting a plurality of gate driving signals {Vg (1), Vg (2), ..., Vg (n)} are cascaded, A plurality of clock signals CLK1 to CLK4 are provided to sequentially generate the gate driving signals Vg (1), Vg (2), ..., Vg (n).

At this time, each of the {stg (1) to stg (n)} is sequentially applied with one clock signal selected from the plurality of clock signals CLK1 to CLK4, and although not shown, the respective stages {stg (1) to stg). (n)}, the driving voltage VDD and the ground voltage VSS are supplied separately.

In addition, the present invention further comprises the first charge sharing circuit 210 and the second charge sharing circuit 220, wherein the first charge sharing circuit 210 and the second charge sharing circuit 220 is the same circuit And a pair of stages receiving the same clock signal among the plurality of stages {stg (1) to stg (n)} having a level shifter, and configured according to a charge sharing control signal (CSS). Charge sharing is performed on the pair of stage outputs.

In more detail, the first charge sharing circuit 210 and the second charge sharing circuit 220 generate the gate driving signal Vg at each stage {stg (1) to stg (n)}. A circuit unit configured for charge sharing for reducing power consumption, and a circuit configured between output stages of a level shifter configured in a pair of stages.

Accordingly, referring to the exemplary circuit diagram of the first charge sharing circuit unit 210 of FIG. 6, the level shifter L / S-1 of the first stage {stg (1)} and the third stage {stg (3)} may be used. In the configuration showing only the level shifters L / S-3, the first charge sharing circuit 210 is configured between the output terminals of the two level shifters L / S-1 and L / S-3. do.

Although not shown, of course, the second shifter is formed between the level shifter L / S-2 of the second stage {stg (2)} and the level shifter L / S-4 of the fourth stage {stg (4)}. Naturally, the charge sharing circuit unit 220 performs the same configuration and operation as the first charge sharing circuit unit 210.

In this regard, the first charge sharing circuit unit 210 includes a first switch CS-SW1 and a second switch CS-SW2 that are switched and controlled by a shared control signal CSS. The CS-SW1 and the second switch CS-SW2 are respectively output from the level shifter L / S-1 of the first stage {stg (1)} and the third stage {stg (3)}. The output of the level shifter (L / S-3) is input.

That is, the first switch CS-SW1 and the second switch CS-SW2 configured in the first charge sharing circuit unit 210 have the first stage {stg (1)} and the third stage {stg (3). A switching element for controlling the charge sharing for the output between the outputs. Preferably, the switching device is configured of an NMOS transistor and a PMOS transistor to perform another charge sharing at different timings.

FIG. 7 is an equivalent circuit diagram briefly explaining the function of the first charge sharing circuit unit 210 or the second charge sharing circuit unit 220. The first switch CS-SW1 is connected to the shared control signal CSS. Next, the level shifter output stages of the two stages are formed like diode current paths by the second switch CS-SW2 to perform charge sharing.

As described above, the charge sharing circuits 210 and 220 constituting charge sharing between stages are configured between two stages operating by receiving a clock signal with a time difference as described above, and referring to the signal timing diagram of FIG. 8. Describe the operation.

Referring to the operation of the gate driver according to the present invention illustrated in FIG. 5 according to the signal timing diagram of FIG. 8, the initial stage {stg () is generated by the start signal Vst input to the initial stage {stg (1)}. 1)}, the drive starts, and the stage is selected from four clock signals CLK1 to CLK4 that are cyclically input. Each stage has one gate driving signal Vg during one frame display period of the liquid crystal panel. )

These outputs are generated in sequence according to the order of the stage connection, and the output of any S-th stage is input as a start signal for driving the S + 1st stage (or S + 2th stage, where S is a natural number). The S-th stage performs reset driving to prepare for display of the next frame by receiving the output of the S + 2th stage.

At this time, the interval between the first clock signal CLK1 and the third clock signal CLK3 is the interval reset time Trst, which is a time interval configured for driving a normal stage, etc., and of course, the second clock signal CLK2. And the fourth clock signal CLK4 are driven with the reset time Trst.

In addition, the present invention uses the reset time (Trst) at the application timing between the plurality of clock signals (CLK1 ~ CLK4) by using the first charge sharing circuit 210 and the second charge sharing circuit 220 Perform

That is, the first charge sharing circuit unit 210 and the second charge sharing circuit unit 220 are connected to each other during the first sharing time Tcss by using a delay time between the two clock signals (that is, the reset time Trst). Charge sharing is performed for the level shifters of the two stages. In this case, the first sharing time Tcss is less than or equal to the reset time Trst.

Thus, the first charge sharing circuit unit 210 of the first stage {stg (1)} and the third stage {stg (3)} will be described as an example. In the first stage {stg (1)}, The first clock signal CLK1 is amplified to output the gate high voltage Vgh of the first gate driving signal Vg (1), and then the illustrated second shared control signal CSS2 is applied. At this time, only the first switch CS-SW1 of the first charge sharing circuit unit 210 is turned on.

Accordingly, the gate high voltage Vgh, which is the high level voltage of the gate driving signal output from the level shift L / S-1 of the first stage {stg (1)}, is determined by the third stage {stg (3)}. Is shared with the output terminal voltage of the level shift L / S-3. At this time, the output terminal of the level shift L / S-3 of the third stage {stg (3)} will be the voltage level of the gate low voltage Vgl after driving in the previous frame.

Accordingly, the output stage of the level shift L / S-3 of the third stage {stg (3)} has already received a voltage of a predetermined level, i.e., ideally, before the third gate driving signal Vg (3) is charged. The gate high voltage Vgh is charged to a voltage level close to the average of the gate low voltage Vgl.

Accordingly, the third stage {stg (3)} is operated at the pre-charged voltage level while driving the output of the third gate driving signal {Vg (3)}, that is, while the third clock signal CLK3 is applied and operated. Since the voltage level needs to be boosted only by the difference with respect to the gate high voltage Vgh, power consumption is reduced, and the transition to the gate high voltage Vgh state can be performed in a short time.

This driving is similarly performed in the second charge sharing circuit unit 220 in the second stage {stg (2)} and the fourth stage {stg (4)}.

In addition, the first charge sharing circuit unit 210 of the first stage {stg (1)} and the third stage {stg (3)} is applied to the case where the first shared control signal CSS2 of FIG. 7 is applied. For example, the first shared control signal CSS1 may be applied after the gate high voltage Vgh is output from the third stage stg (3). At this time, only the second switch CS-SW2 of the first charge sharing circuit unit 210 is turned on.

Accordingly, the gate high voltage Vgh, which is the high level voltage of the gate driving signal output from the level shift L / S-3 of the third stage {stg (3)}, is determined by the first stage {stg (1)}. Is shared with the output terminal voltage of the level shift L / S-1. At this time, the output terminal of the level shift L / S-1 of the first stage {stg (1)} may be the voltage level of the gate low voltage Vgl after the gate driving signal output.

As a result, the output stage of the level shift L / S-3 of the third stage {stg (3) may quickly become a voltage having a predetermined level, i.e., ideally, the gate high voltage Vgh and the gate low voltage Vgl. It has a state in which the voltage level is lowered to an average.

After the output of the third gate driving signal Vg (3), the voltage level needs to be boosted by only the difference with respect to the gate low voltage Vgl at the previously lowered voltage level, thereby reducing power consumption. It becomes possible to switch to the gate low voltage (Vgl) state in time. Of course, this operation is similarly performed in the second charge sharing circuit unit 220 in the second stage {stg (2)} and the fourth stage {stg (4)}.

In addition, in the signal timing diagram of FIG. 7, the first and second switches CS-SW1 and CS-SW2 configured as PMOS-type and NMOS-types are distinguished from each other to show operations. Although the shared control signal CSS1 and the second shared control signal CSS2 are illustrated as examples, this is only an example and a signal capable of distinguishing switching operations of the first switch CS-SW1 and the second switch CS-SW2 is possible. It may be applied in any way. In addition, for example, one of the plurality of control signals output from a timing controller for generating and providing a plurality of control signals for controlling the gate driver and the source driver (for example, source output enable ( SOE, Dual SOE, etc.) may be used.

FIG. 9 is a view for explaining an application of the gate driver of the liquid crystal display according to the present invention. In addition, the first charge sharing circuit unit 210 and the second charge sharing circuit unit 220 are further supplied with a separate voltage. It adds a pre-charging function.

That is, during the charge sharing operation of the first charge sharing circuit 210 and the second charge sharing circuit 220, each stage is applied by applying a precharging voltage Vpre set to an arbitrary voltage level as a level shift of each stage. It will be appreciated that the reduction in power consumed to generate faster voltage levels and gate drive signals can be seen.

1 is a block diagram illustrating a general liquid crystal display device 100.

FIG. 2 is a diagram illustrating a configuration of a gate driver of FIG. 1.

3 is a signal timing diagram for describing an operation principle of the gate driver of FIG. 2.

4 is a circuit diagram illustrating a level shifter configured in each gate driver of FIG. 2.

5 is a diagram illustrating a configuration of a gate driver of a liquid crystal display according to the present invention.

FIG. 6 is an exemplary circuit diagram of the first charge sharing circuit unit 210 of FIG. 5.

7 is an equivalent circuit diagram briefly explaining a function of the first charge sharing circuit unit 210 or the second charge sharing circuit unit 220.

8 is a signal timing diagram for describing an operation of the gate driver of the liquid crystal display according to the present invention.

9 is a view for explaining the application of the gate driver of the liquid crystal display according to the present invention;

<Brief description of the main parts of the drawing>

210, 220: first charge sharing circuit part, second charge sharing circuit part

CLK1 to CLK4: first to fourth clock signals

stg (1) to stg (n): first stage to nth stage

CSS1, CSS2: first shared control signal, second shared control signal

Claims (8)

A gate driver for sequentially outputting a plurality of gate driver signals, a source driver for outputting image data to the liquid crystal panel in synchronization with the gate driver signal, and timing for providing a plurality of control signals for controlling the gate driver and the source driver A gate driver of a liquid crystal display device having a control unit, A plurality of stages configured to receive one of a plurality of clock signals and output the gate driving signal including a gate high voltage and a gate low voltage; A level shifter configured in each stage to amplify an input clock signal to output the gate high voltage or the gate low voltage; A charge sharing circuit unit configured between a pair of stages each receiving the clock signal at a time that does not overlap each other among the plurality of stages, and performing charge sharing for the output of the pair of stages according to a sharing control signal; Gate driver of the liquid crystal display device including a The method according to claim 1, The plurality of clock signals may include first clock signals and fourth clock signals applied at different timings, respectively. The method according to claim 2, The first clock signal and the third clock signal are applied at a time not overlapping each other, and the second clock signal and the fourth clock signal are applied at a non-overlapping time not overlapping each other. Gate driver The method according to claim 3, And the charge sharing circuit unit is configured between the output terminals of the level shifters respectively configured in the pair of stages. The method according to claim 4, And the charge sharing circuit unit is configured between odd-numbered stages and even-numbered stages of the plurality of stages, respectively. The method according to claim 5, The charge sharing circuit unit, And a first switch and a second switch controlled by the sharing control signal, wherein the first switch and the second switch each receive an output of a level shifter configured in the pair of stages. Gate driver of the device The method of claim 6, The first switch and the second switch of the gate driver of the liquid crystal display device, characterized in that each consisting of a PMOS transistor and an NMOS transistor The method of claim 7, wherein The shared control signal includes a gate driver of one of the plurality of control signals.

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