JP5525685B2 - Semiconductor device and electronic equipment - Google Patents

Description

  The present invention relates to a pulse output circuit, a shift register, a display device having the shift register, a semiconductor device, and an electronic device, and more particularly to a pulse output circuit, a shift register, a display device, and a semiconductor constituted by a single-conductivity thin film transistor (TFT). The present invention relates to an apparatus and an electronic device.

  In recent years, there has been a development of a display device, particularly an active matrix display device, in which a circuit is formed using a thin film transistor (hereinafter also referred to as “TFT”) using a semiconductor thin film on an insulator, particularly a glass or plastic substrate. Progressing. An active matrix display device formed using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and the electric charges of each pixel are controlled by the TFTs arranged in each pixel. The video is displayed.

  Furthermore, as a recent technology, in addition to the pixel TFT that constitutes the pixel, a method of simultaneously forming a drive circuit using a TFT in the peripheral region of the pixel portion has been developed. Accordingly, it has become an indispensable device for a display unit of a portable information terminal whose application field has been remarkably expanded in recent years.

  In general, a CMOS circuit in which an N-type TFT and a P-type TFT are combined is used as a circuit constituting a driving circuit of a display device. A characteristic of a CMOS circuit is that current flows only at the moment when the logic changes (from H (High) level to L (Low) level, or from L level to H level). Ideally, no current flows (actually, there is a small leakage current), so that the power consumption of the entire circuit can be kept very low, and the TFTs of the opposite polarities are complementary Therefore, it is possible to operate at high speed.

  However, considering the manufacturing process, the CMOS circuit has a complicated ion doping process and the like, and the large number of processes directly affects the manufacturing cost. In view of this, there has been proposed a circuit in which a conventional CMOS circuit is configured using either N-type or P-type unipolar TFTs and realizes high-speed operation similar to that of a CMOS circuit ( For example, see Patent Document 1).

  As shown in FIGS. 7A to 7C, the circuit described in Patent Document 1 is configured so that the gate electrode of the TFT 2050 electrically connected to the output terminal is temporarily floated, whereby the TFT 2050. Using the capacitive coupling between the gate and the source, the potential of the gate electrode can be made higher than the power supply potential. As a result, an output without amplitude attenuation can be obtained without causing a voltage drop due to the threshold value of the TFT 2050. Reference numerals 2010, 2020, 2030, 2040, and 2060 denote TFTs, 2070 denotes a capacitive element, 2100 denotes a first amplitude compensation circuit, and 2200 denotes a second amplitude compensation circuit.

  Such an operation in the TFT 2050 is called a bootstrap operation. By this operation, an output pulse can be obtained without causing a voltage drop due to the threshold value of the TFT.

7A to 7C has a potential such as noise at the node α because the gate electrodes of the TFTs 2050 and 2060 are in a floating state in a period in which no pulse is input and output. In order to solve this variation, a circuit that reduces noise generated at the node α by setting the TFTs 1020 and 1060 to the floating state in a period in which there is no input / output of a pulse (see FIGS. 8A to 8C). C)) has been proposed (see, for example, Patent Document 2). Reference numerals 1010, 1030, 1040, and 1050 denote TFTs, 1070 denotes a capacitive element, 1100 denotes a first amplitude compensation circuit, and 1200 denotes a second amplitude compensation circuit.
JP 2002-335153 A JP 2004-226429 A

  In FIG. 8, paying attention to SROut1, CK1 changes from H level to L level after the pulse is output. Along with this, the potential of SROut1 also starts decreasing. On the other hand, at the timing when CK2 becomes H level, the same operation as described above is performed in the second stage, and a pulse is output to SROut2. This pulse is input to the input terminal 3 in the first stage, and the TFT 1030 is turned on. As a result, the potentials of the gate electrodes of the TFTs 1020 and 1060 rise and turn on. Along with this, the potential of the gate electrode of the TFT 1050 and the potential of SROut1 are lowered. Thereafter, when the output of SROut2 changes from the H level to the L level, the TFT 1030 is turned off. Therefore, the gate electrodes of the TFTs 1020 and 1060 are in a floating state at this moment. Thereafter, this state continues until the next SP is input in the first stage.

  Thus, in the circuits of FIGS. 8A and 8B, the node β is in a floating state during a period in which no pulse is input / output. For example, when the circuits of FIGS. 8A and 8B are used as scan drivers, it is necessary to hold the potential of the node β for about one frame. Since the channel width of the TFT 1040 and the TFT 1060 is relatively large, the off-current is also increased. At this time, the potential of the node β may be lowered by the off-state current of the TFT 1040 and the TFT 1060, and the TFT 1060 may be turned off. As a result, a malfunction may occur due to capacitive coupling with the clock signal.

  Further, when a pulse is output from the TFT 1050, the node β is in a floating state. Therefore, when the potential of the node γ rises from the L level to the H level, the potential of the node β may increase due to capacitive coupling. As a result, the TFT 1020 may turn on and malfunction. Since this potential fluctuation is much smaller than the amplitude of a normal pulse, there is no problem if the potential fluctuation is smaller than the threshold value of the TFT 1020. However, when the potential fluctuation becomes larger than the threshold value of the TFT 1020, the potential of the node α is lowered, which may cause malfunction. In particular, when amorphous silicon is used as the TFT, a nitride film is often used for the gate insulating film, and the threshold value may vary. As a result, there is a high possibility that the pulse output circuit malfunctions.

  In addition, when amorphous silicon is used as the TFT, the electrical characteristics are inferior to those of a TFT using polysilicon, so that it is difficult to obtain a sufficient driving capability, and the threshold value shifts depending on voltage conditions. Therefore, there is a problem in circuit technology for forming a drive circuit for driving a pixel by using a TFT using amorphous silicon.

  The invention disclosed in this specification provides a pulse output circuit, a shift register, and a display device that reduce malfunctions in a circuit and guarantee more reliable operation by solving one or more of these problems. Objective.

  The pulse output circuit of the present invention is characterized in that a potential is periodically supplied to the gate electrode of a transistor in a floating state so that the gate electrode is turned on in a non-selection period in which no pulse is output. In addition, the potential is supplied to the gate electrode of the transistor by periodically turning on or off another transistor.

The shift register of the present invention is driven so that the pulse output from the m-th pulse output circuit and the pulse output from the (m + 1) -th pulse output circuit overlap by a half ( 1/4 period). Features. Hereinafter, specific configurations of the shift register and the pulse output circuit of the present invention will be described.

  The shift register of the present invention includes an (m-2) th pulse output circuit, an (m-1) th pulse output circuit, an mth pulse output circuit, an (m + 1) th pulse output circuit, and an (m + 2) th pulse output circuit. A plurality of pulse output circuits including at least a pulse output circuit (m ≧ 3) and first to fourth signal lines for outputting a clock signal; In the m-th pulse output circuit, the first to third input terminals are different from three of the first signal line to the fourth signal line. Electrically connected to the signal line, the fourth input terminal is electrically connected to the output terminal of the (m−2) th pulse output circuit, and the fifth input terminal is connected to the (m−1) th output terminal. The sixth input terminal is electrically connected to the output terminal of the pulse output circuit, and the sixth input terminal is (m + 2) The output terminal is electrically connected to the output terminal of the pulse output circuit. The output terminal includes a sixth input terminal of the (m−2) th pulse output circuit, a fifth input terminal of the (m + 1) th pulse output circuit, and a fifth input terminal. It is characterized in that it is electrically connected to the fourth input terminal of the (m + 2) pulse output circuit.

  The pulse output circuit of the present invention includes first to ninth transistors. The first transistor has a first electrode electrically connected to the first power supply line and a second electrode connected to the first power supply line. 3 is electrically connected to the gate electrode of the third transistor, the gate electrode is electrically connected to the fourth input terminal, and the second transistor has the first electrode electrically connected to the second power supply line. , The second electrode is electrically connected to the gate electrode of the third transistor, the gate electrode is electrically connected to the gate electrode of the fourth transistor, and the third transistor has the first electrode as the first electrode. The second electrode is electrically connected to the output terminal, the fourth transistor has the first electrode electrically connected to the third power supply line, the second electrode The electrode is electrically connected to the output terminal and the fifth transistor The first electrode is electrically connected to the fourth power supply line, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode The sixth transistor is electrically connected to the fourth input terminal, and the sixth transistor has a first electrode electrically connected to the fourth power supply line, a second electrode connected to the gate electrode of the second transistor, and a fourth transistor The gate electrode of the transistor is electrically connected, the gate electrode is electrically connected to the fifth input terminal, the seventh transistor has the first electrode electrically connected to the fifth power supply line, The second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, the gate electrode is electrically connected to the sixth input terminal, and the eighth transistor includes the first transistor The electrode is in electrical contact with the fifth power line The second electrode is electrically connected to the second electrode of the ninth transistor, the gate electrode is electrically connected to the second input terminal, and the ninth transistor has the first electrode connected to the second electrode. The gate electrode of the second transistor and the gate electrode of the fourth transistor are electrically connected, and the gate electrode is electrically connected to the third input terminal.

  The display device of the present invention includes a pixel and a shift register that drives the pixel, and the shift register includes the (m−2) th pulse output circuit, the (m−1) th pulse output circuit, and the mth A plurality of pulse output circuits including at least a pulse output circuit, an (m + 1) th pulse output circuit, and an (m + 2) th pulse output circuit (m ≧ 3); a first signal line to a fourth signal line for outputting a clock signal; The pulse output circuit includes a first input terminal to a sixth input terminal and an output terminal; in the m-th pulse output circuit, the first input terminal to the third input terminal are: The fourth signal line is electrically connected to any one of the first signal line to the fourth signal line, the fourth input terminal is electrically connected to the output terminal of the (m−2) th pulse output circuit, and the fifth The input terminal is electrically connected to the output terminal of the (m−1) th pulse output circuit. The sixth input terminal is electrically connected to the output terminal of the (m + 2) th pulse output circuit, the output terminal is the sixth input terminal of the (m−2) th pulse output circuit, and the The fifth input terminal of the (m + 1) pulse output circuit and the fourth input terminal of the (m + 2) th pulse output circuit are electrically connected.

  The present invention can suppress malfunction of a pulse output circuit by periodically supplying a potential to a gate electrode of a transistor that is in a floating state in a non-selection period in which no pulse is input and output.

Further, by using the m-th of the pulse output from the pulse output circuit (m + 1) -th pulse half outputted from the pulse output circuit (1/4 cycles) overlapping driving method, applying a large load And a pulse output circuit operating at a high frequency can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings.

(Embodiment 1)
In this embodiment, an example of a pulse output circuit of the present invention and a shift register including the pulse output circuit will be described with reference to drawings.

The shift register described in this embodiment includes a first pulse output circuit _{10_1} to an nth pulse output circuit _{10_n} (n ≧ 3), and first signal lines 11 to 4 for outputting clock signals. It has a line 14 (see FIG. 1A). The first signal line 11 outputs a first clock signal (CK1), the second signal line 12 outputs a second clock signal (CK2), and the third signal line 13 outputs a third clock signal. (CK3) is output, and the fourth signal line 14 outputs a fourth clock signal (CK4).

The clock signal (CK) is a signal that repeats an H (High) signal and an L (Low) signal at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are In order, it is delayed by 1/4 period. In this embodiment, driving of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4).

Each of the first pulse output circuit _{10_1} to the nth pulse output circuit _{10_n} includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a 5 input terminals 25, sixth input terminals 26, and output terminals 27 (see FIG. 1B).

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first signal line 11 to the fourth signal line 14. For example, in FIG. 1, in the first pulse output circuit 10 _{_ 1} , the first input terminal 21 is electrically connected to the first signal line 11, and the second input terminal 22 is connected to the second signal line 12. The third input terminal 23 is electrically connected to the third signal line 13. In the second pulse output circuit _{10_2} , the first input terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is electrically connected to the third signal line 13. The third input terminal 23 is electrically connected to the fourth signal line 14.

  In the m-th pulse output circuit (m ≧ 3) of the shift register described in this embodiment, the fourth input terminal 24 includes the output terminal 27 of the (m−2) th pulse output circuit and the (m− The first input terminal 25 is electrically connected to the fifth input terminal 25 of the pulse output circuit 1), and the fifth input terminal 25 is the output terminal 27 of the (m−1) th pulse output circuit and the (m + 1) th pulse output circuit. The fourth input terminal 24 is electrically connected, the sixth input terminal 26 is electrically connected to the output terminal 27 of the (m + 2) th pulse output circuit, and the output terminal 27 is the (m−2) th. The sixth input terminal 26 of the first pulse output circuit, the fifth input terminal 25 of the (m + 1) th pulse output circuit, and the fourth input terminal 24 of the (m + 2) th pulse output circuit; A signal is output to OUT (m).

For example, in the third pulse output circuit 10 _{_3,} the fourth input terminal 24 to the fifth input terminal electrically connected to the first output terminal and a second pulse output circuit 10 _{_1} pulse output circuit 10 _{_2} is, the fifth input terminal 25 is a fourth input terminal electrically connected to the output terminal and the fourth pulse output circuit 10 _{_4} of the second pulse output circuit 10 _{_2,} input terminal 26 of the sixth first 5 is a pulse connected output circuit 10 _{_5} output terminal and electrically, the output terminal the input terminal of the sixth of the first pulse output circuit 10 _{_1,} fifth input terminal of the fourth pulse output circuit 10 _{_4} and The fifth pulse output circuit _{10_5} is electrically connected to the fourth input terminal. In the third pulse output circuit _{10_3} , the fourth input terminal 24 receives a signal output from the output terminal of the first pulse output circuit _{10_1} , and the fifth input terminal 25 receives the second pulse. The signal output from the output terminal of the output circuit _{10_2} is input, the signal output from the output terminal of the fifth pulse output circuit _{10_5} is input to the sixth input terminal 26, and the signal is output from the output terminal 27. signal is input input terminal of the sixth of the first pulse output circuit 10 _{- 1,} the input terminal of the fifth fourth pulse output circuit 10 _{- 4} and the fourth input terminal of the fifth pulse output circuit 10 _{_5} .

  In the first pulse output circuit, the first start pulse (SP1) is input to the fourth input terminal 24, and the second start pulse (SP2) is input to the fifth input terminal 25.

Next, specific structures of the first pulse output circuit _{10_1} to the n-th pulse output circuit _{10_n} are described.

Each of the first pulse output circuit _{10_1} to the n-th pulse output circuit _{10_n} includes a first transistor 101 to a ninth transistor 109, a first capacitor element 111, and a second capacitor element 112. (See FIG. 1C). In addition to the first input terminal 21 to the sixth input terminal 26 and the output terminal 27 described above, the first transistor 101 to the ninth transistor 109 are connected from the first power supply line 31 to the sixth power supply line 36. A signal is supplied.

  In the first transistor 101, the first electrode (one of the source electrode and the drain electrode) is electrically connected to the first power supply line 31, and the second electrode (the other of the source electrode and the drain electrode) is the third. The gate electrode of the transistor 103 and the second electrode of the second capacitor 112 are electrically connected, and the gate electrode is electrically connected to the fourth input terminal 24. In the second transistor 102, the first electrode is electrically connected to the second power supply line 32, the second electrode is electrically connected to the gate electrode of the third transistor 103, and the gate electrode is fourth. The transistor 104 is electrically connected to the gate electrode. In the third transistor 103, the first electrode is electrically connected to the first input terminal 21, and the second electrode is electrically connected to the output terminal 27. The fourth transistor 104 has a first electrode electrically connected to the third power supply line 33 and a second electrode electrically connected to the output terminal 27. In the fifth transistor 105, the first electrode is electrically connected to the fourth power supply line 34, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. The gate electrode is electrically connected to the fourth input terminal 24. The sixth transistor 106 has a first electrode electrically connected to the fourth power supply line 34, and a second electrode electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. And the gate electrode is electrically connected to the fifth input terminal 25. In the seventh transistor 107, the first electrode is electrically connected to the fifth power supply line 35, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. The gate electrode is electrically connected to the sixth input terminal 26. The eighth transistor 108 has a first electrode electrically connected to the fifth power supply line 35, a second electrode electrically connected to the second electrode of the ninth transistor 109, and a gate electrode The second input terminal 22 is electrically connected. In the ninth transistor 109, the first electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104, and the gate electrode is electrically connected to the third input terminal 23. Has been. In the first capacitor 111, the first electrode is electrically connected to the sixth power supply line 36, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. Connected. In the second capacitor 112, the first electrode is electrically connected to the output terminal 27, and the second electrode is electrically connected to the second electrode of the first transistor 101 and the gate electrode of the third transistor 103. It is connected to the.

  In FIG. 1C, the second electrode of the first transistor 101, the second electrode of the second transistor 102, the gate electrode of the third transistor 103, and the second electrode of the second capacitor 112 Let the connection location be node A. The gate electrode of the second transistor 102, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the second electrode of the seventh transistor 107 The connection point of the first electrode of the ninth transistor 109 and the second electrode of the first capacitor 111 is a node B. Further, a connection position of the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, the first electrode of the second capacitor 112, and the output terminal 27 is a node C.

  Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. Specifically, in the timing chart of FIG. 2, description is divided into a first period 51, a second period 52, a third period 53, a fourth period 54, and a fifth period 55. Note that in the following description, the first transistor 101 to the ninth transistor 109 are N-channel thin film transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). Shall be.

Here, the output of the second pulse output circuit _{10_2} will be described. In the second pulse output circuit _{10_2} , the first input terminal 21 is electrically connected to the second signal line 12 that supplies the second clock signal (CK2), and the second input terminal 22 is the third. Is electrically connected to the third signal line 13 that supplies the second clock signal (CK3), and the third input terminal 23 is electrically connected to the fourth signal line 14 that supplies the fourth clock signal (CK4). It is connected.

  Note that the potential (VDD) of V1 is supplied to the first power supply line 31 and the fifth power supply line 35, and the second power supply line 32 to the fourth power supply line 34 and the sixth power supply line 36 have V2 potential. It is assumed that a potential (VSS) is supplied. Here, V1> V2. The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and are VDD when the level is H and VSS when the level is the L level. And In addition, here, VSS is set to 0 for simplification of description, but the present invention is not limited to this.

In the first period 51, the second start pulse (SP2) is at the H level, and the first transistor 101 and the fifth transistor which are electrically connected to the fourth input terminal 24 of the second pulse output circuit _{10_2} . The transistor 105 is turned on. Since the third clock signal (CK3) and the fourth clock signal (CK4) are also at the H level, the eighth transistor 108 and the ninth transistor 109 are also turned on (see FIG. 3A).

  At this time, since the first transistor 101 is on, the potential of the node A is increased. A through current flows between the fifth power supply line 35 and the fourth power supply line 34. By adjusting the size of the transistor, the potential of the node B is set so that the second transistor 102 is turned off. To control. For example, by increasing the channel width of the fifth transistor 105 (the channel width in the direction perpendicular to the direction in which carriers flow in the source region and the drain region) as compared with the eighth transistor 108 and the ninth transistor 109. Realized.

In the second period 52, H-level signal from the output terminal 27 of the first pulse output circuit _{10 _1} (OUT (1)) is output to the fifth input terminal 25 of the second pulse output circuit _{10 _2} The sixth transistor 106 that is electrically connected is turned on. In addition, since the third clock signal (CK3) becomes L level and the eighth transistor 108 is turned off, the through current observed in the first period 51 disappears (see FIG. 3B).

  At this time, the potential of the node A is obtained by subtracting the threshold voltage of the first transistor 101 from the potential of the first power supply line 31 with the second electrode of the first transistor 101 serving as the source electrode. Therefore, V1−Vth101 (Vth101 is the threshold voltage of the first transistor 101). Then, the first transistor 101 is turned off, and the node A is in a floating state while maintaining V1-Vth101.

  Here, in the third transistor 103, the potential of the gate electrode is V1-Vth101. If the voltage between the gate and the source of the third transistor 103 exceeds the threshold value, that is, if V1−Vth101−V2> Vth103 (Vth103 is the threshold voltage of the third transistor 103), The third transistor 103 is turned on.

  In the third period 53, the second start pulse (SP2) becomes L level, and the first transistor 101 and the fifth transistor 105 are turned off. Further, the second clock signal (CK2) becomes H level, and an H level signal is supplied to the first electrode of the third transistor 103 electrically connected to the first input terminal 21 (FIG. 3 ( C)).

  Here, since the third transistor 103 is on, a current is generated between the source and the drain, and the node C (the output terminal 27 (OUT (2))), that is, the second electrode of the third transistor 103 is generated. In this case, the potential of the source electrode starts to rise. A capacitive coupling due to the second capacitor 112 exists between the gate and the source of the third transistor 103, and the potential of the gate electrode of the third transistor 103 which is in a floating state is increased as the potential of the node C is increased. Ascend (bootstrap operation). Eventually, the potential of the gate electrode of the third transistor 103 becomes higher than V1 + Vth103, and the potential of the node C becomes equal to V1.

  Note that this bootstrap operation is performed by providing the second capacitor element 112 between the gate electrode and the second electrode of the third transistor 103, but without providing the second capacitor element 112. Alternatively, this may be performed by capacitive coupling of the channel capacitance of the third transistor 103 and the parasitic capacitance between the gate electrode and the second electrode of the third transistor 103.

At this time, since the output terminal 27 (OUT (1)) of the first pulse output circuit _{10_1} is at the H level, the sixth transistor 106 is turned on and the node B is maintained at the L level. Therefore, when the potential of the node C rises from the L level to the H level, it is possible to suppress problems due to capacitive coupling between the node B and the node C.

After that, in the second half of the third period 53, the output terminal 27 (OUT (1)) of the first pulse output circuit _{10_1} becomes L level, the sixth transistor 106 is turned off, and the node B is in a floating state. Become. Further, the third clock signal (CK3) is at an H level, and the eighth transistor 108 is turned on (see FIG. 3D).

In the fourth period 54, an output terminal 27 of the fourth pulse output circuit _{10 _4} (OUT (4)) becomes the H level, which is electrically connected to an output terminal 27 of the fourth pulse output circuit _{10 _4} The input terminal 26 of the second pulse output circuit _{10_2} is at the H level, the seventh transistor 107 is turned on, and the node B is also at the H level. Accordingly, the second transistor 102 and the fourth transistor 104 are turned on, the third transistor 103 is turned off, and the output terminal 27 (OUT (2)) becomes L level. Further, the fourth clock signal (CK4) is at an H level, and the ninth transistor 109 is turned on (see FIG. 4A).

  After that, in the second half of the fourth period 54, the third clock signal (CK3) becomes L level, and the eighth transistor 108 is turned off (see FIG. 4B).

In the fifth period 55, the output terminal 27 (OUT (4)) of the fourth pulse output circuit _{10_4} becomes the L level, the seventh transistor 107 is turned off, and the node B is kept floating at the H level. It becomes a state. Accordingly, the second transistor 102 and the fourth transistor 104 are kept on (see FIG. 4C).

  After that, in a certain period of the fifth period 55 (when the third clock signal (CK3) and the fourth clock signal (CK4) are both at the H level), the eighth transistor 108 and the ninth transistor 109 are The signal is turned on, and an H level signal is periodically supplied to the node B (see FIG. 4D).

  In this manner, by adopting a configuration in which an H level signal is periodically supplied to the node B during a period in which the potential of the output terminal 27 is held at an L level, malfunction of the pulse output circuit can be suppressed. Further, by periodically turning on or off the eighth transistor 108 and the ninth transistor 109, the shift of the threshold value of the transistor can be reduced.

Further, in the fifth period 55, while the H-level signal is not supplied to the node B from the fifth power supply line 35, the off-state current of the fifth transistor 105 and the sixth transistor 106 causes the node B to Potential may drop. However, since the first capacitor 111 is electrically connected to the node B, a decrease in the potential of the node B can be reduced.

  Note that although the case where the fifth power supply line 35 is set to the same potential (VDD) of V1 as that of the first power supply line 31 is described in this embodiment mode, the fifth power supply line 35 is set to the first power supply line. It may be set lower than 31 (V1> V35> V2, V35 being the potential of the fifth power supply line 35). As a result, the potentials of the gate electrodes of the second transistor 102 and the fourth transistor 104 can be kept low, the shift of the threshold values of the second transistor 102 and the fourth transistor 104 is reduced, and deterioration is reduced. Can be suppressed.

In the shift register described in this embodiment, as illustrated in FIG. 5A, the pulse output from the mth pulse output circuit and the pulse output from the (m + 1) th pulse output circuit are half. The overlapping driving method is used (for 1/4 period). This is compared with the driving method (see FIG. 5B) in which the pulse output from the mth pulse output circuit and the pulse output from the (m + 1) th pulse output circuit in the conventional shift register do not overlap. The time for charging the wiring can be approximately doubled. Thus, by using a first m of the pulse output from the pulse output circuit (m + 1) -th pulse half outputted from the pulse output circuit (1/4 cycles) overlapping driving method, a large load A pulse output circuit that can be applied and operates at a high frequency can be provided. In addition, the operating conditions of the pulse output circuit can be increased. In particular, it is very effective to use the driving method shown in FIG. 5A for a thin film transistor using amorphous silicon having poor electrical characteristics.

  Note that the shift register and the pulse output circuit described in this embodiment can be combined with any structure of the shift register and the pulse output circuit described in other embodiments in this specification. The invention of this embodiment can also be applied to a semiconductor device. In this specification, a semiconductor device means a device that can function by utilizing semiconductor characteristics.

(Embodiment 2)
In this embodiment, different structures from the shift register and the pulse output circuit described in the above embodiments are described with reference to drawings.

The shift register described in this embodiment includes a first pulse output circuit _{10_1} to an nth pulse output circuit _{10_n} (n ≧ 3), and first signal lines 11 to 4 for outputting clock signals. It has a line 14 (see FIG. 6A). In addition, each of the first pulse output circuit _{10_1} to the nth pulse output circuit _{10_n} includes a first input terminal 21, a second input terminal 22, a third input terminal 23, and a fourth input terminal 24. , A fifth input terminal 25, a sixth input terminal 26, a first output terminal 27, and a second output terminal 28 (see FIG. 6B). In the pulse output circuit shown in the first embodiment, the second output terminal 28 is newly added.

  The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first signal line 11 to the fourth signal line 14. In the m-th pulse output circuit (m ≧ 3) of the shift register described in this embodiment, the fourth input terminal 24 includes the first output terminal 27 of the (m−2) th pulse output circuit and the The fifth input terminal 25 is electrically connected to the fifth input terminal 25 of the (m−1) pulse output circuit, and the fifth input terminal 25 is connected to the first output terminal 27 and the (( The m + 1) pulse output circuit is electrically connected to the fourth input terminal 24, and the sixth input terminal 26 is electrically connected to the first output terminal 27 of the (m + 2) th pulse output circuit. The first output terminal 27 is the sixth input terminal 26 of the (m−2) th pulse output circuit, the fifth input terminal 25 of the (m + 1) th pulse output circuit, and the fifth input terminal 25 of the (m + 2) th pulse output circuit. 4 input terminal 24 and second output terminal 28 is connected to OUT ( ) To output the signal.

  In other words, the shift register described in this embodiment includes the first output terminal 27 and the second output terminal 28, and is used to output a signal to the other pulse output circuit and to the outside. The output terminal is provided separately.

Next, specific structures of the first pulse output circuit _{10_1} to the n-th pulse output circuit _{10_n} described in this embodiment will be described.

Each of the pulse output circuit _{10 _n} of the first pulse output circuit _{10 - 1} to the n, the first transistor 101 to the ninth transistor 109, the transistor 204 of the tenth transistor 201 to 13, a first capacitive element 111, a second capacitor 112, and a third capacitor 211 (see FIG. 6C). The pulse output circuit described in this embodiment has a structure in which a tenth transistor 201 to a thirteenth transistor 204 and a third capacitor 211 are added to the pulse output circuit described in Embodiment 1. In addition to the first input terminal 21 to the sixth input terminal 26, the first output terminal 27, the first power supply line 31 to the sixth power supply line 36 described in the first embodiment, a second Signals are supplied to the transistors from the output terminal 28 and the seventh power supply line 37 to the ninth power supply line 39.

  In the tenth transistor 201, the first electrode is electrically connected to the first input terminal 21, the second electrode is electrically connected to the second output terminal 28, and the gate electrode is the first transistor. 101 is electrically connected to the second electrode. In the eleventh transistor 202, the first electrode is electrically connected to the eighth power supply line 38, the second electrode is electrically connected to the second output terminal 28, and the gate electrode is the second transistor. The gate electrode of 102 and the gate electrode of the fourth transistor 104 are electrically connected. In the twelfth transistor 203, the first electrode is electrically connected to the ninth power supply line 39, the second electrode is electrically connected to the second output terminal 28, and the gate electrode is the ninth transistor. It is electrically connected to 109 gate electrodes. In the thirteenth transistor 204, the first electrode is electrically connected to the seventh power supply line 37, the second electrode is electrically connected to the first output terminal 27, and the gate electrode is the ninth transistor. It is electrically connected to 109 gate electrodes. In the third capacitor 211, the first electrode is electrically connected to the second output terminal 28, and the second electrode is the second electrode of the first transistor 101 and the gate electrode of the tenth transistor 201. Is electrically connected.

  Similarly to the second power line 32 to the fourth power line 34 and the sixth power line 36, the potential V2 (VSS) is supplied to the seventh power line 37 to the ninth power line 39. It can be set as a structure.

  The first output terminal 27 and the second output terminal 28 are provided so that the same signal is output. The tenth transistor 201 corresponds to the third transistor 103, and the fourth transistor 104 corresponds to the fourth transistor 104. The eleventh transistor 202 has a corresponding configuration. That is, the tenth transistor 201 performs a bootstrap operation similarly to the third transistor 103. Note that the bootstrap operation of the tenth transistor 201 is performed by providing the third capacitor element 211 between the gate electrode and the second electrode of the tenth transistor 201. Without providing 211, the capacitance may be obtained by capacitive coupling of the channel capacitance of the tenth transistor 201 and the parasitic capacitance between the gate electrode and the second electrode of the tenth transistor 201.

  The twelfth transistor 203 and the thirteenth transistor 204 are used to shorten the falling time of the potential of the scanning line. If the fall time of the scan line potential can be sufficiently shortened by the twelfth transistor 203 and the thirteenth transistor 204, the fall time of the scan line potential must be shortened by the fourth transistor 104 and the eleventh transistor 202. Therefore, the potential of the fifth power supply line 35 can be set lower than the power supply of the first power supply line 31. This makes it possible to reduce threshold shifts of the fourth transistor 104, the eleventh transistor 202, and the second transistor 102.

  Note that the shift register and the pulse output circuit described in this embodiment can be combined with any structure of the shift register and the pulse output circuit described in other embodiments in this specification. The invention of this embodiment can also be applied to a semiconductor device.

(Embodiment 3)
In this embodiment, structures that are different from those of the shift register and the pulse output circuit described in the above embodiments are described.

  In the structures described in Embodiments 1 and 2 above, an example in which all circuits are formed using N-channel thin film transistors has been described. However, only P-channel thin film transistors are used in that unipolar thin film transistors are used. A similar configuration may be used. Although not particularly illustrated, in the diagram illustrated in FIG. 1C or FIG. 6C, the connection of the transistors is the same, and the potential of the power supply line is described in Embodiment Mode 1 and Embodiment Mode 2. And reverse. Further, a configuration may be adopted in which the H level and the L level of the input signal are all reversed. Note that the invention of this embodiment can also be applied to a semiconductor device.

(Embodiment 4)
A structure in which the shift register described in any of the above embodiments is provided in a display device is described with reference to drawings.

  In FIG. 9A, a pixel portion 1102 in which a plurality of pixels 1101 are arranged in a matrix is provided over a substrate 1107. A signal line driver circuit 1103 and a first scan line driver are provided around the pixel portion 1102. A circuit 1104 and a second scan line driver circuit 1105 are included. These drive circuits are supplied with signals from the outside via the FPC 1106.

  FIG. 9B illustrates the structure of the first scan line driver circuit 1104 and the second scan line driver circuit 1105. The scan line driver circuits 1104 and 1105 each include a shift register 1114 and a buffer 1115. FIG. 9C illustrates the structure of the signal line driver circuit 1103. The signal line driver circuit 1103 includes a shift register 1111, a first latch circuit 1112, a second latch circuit 1113, and a buffer 1117.

  The circuit operating as a shift register in this embodiment can be applied to the circuits of the shift register 1111 and the shift register 1114. By applying the circuit that operates as the shift register described in the above embodiment mode, even when a circuit that operates as the shift register is provided using a thin film transistor using amorphous silicon, the circuit can be operated at a high frequency.

  Note that the configurations of the scan line driver circuit and the signal line driver circuit are not limited to those shown in FIG. 9, and may include, for example, a sampling circuit or a level shifter. In addition to the driving circuit, a circuit such as a CPU or a controller may be integrally formed on the substrate 1107. Then, the number of external circuits (IC) to be connected is reduced, and the weight and thickness can be further increased.

  Note that the display device described in this embodiment can be implemented in combination with the structure of the shift register, the pulse output circuit, or the display device described in other embodiments in this specification.

(Embodiment 5)
In this embodiment, a structure of a display panel used for the display device described in Embodiment 4 is described with reference to drawings.

  First, a display panel applicable to a display device will be described with reference to FIG. 10A is a top view illustrating the display panel, and FIG. 10B is a cross-sectional view taken along line A-A ′ in FIG. 10A. A signal line driver circuit 3601, a pixel portion 3602, a second scan line driver circuit 3603, and a first scan line driver circuit 3606 indicated by dotted lines are included. Further, a sealing substrate 3604 and a sealing material 3605 are provided, and an inner side surrounded by the sealing material 3605 is a space 3607.

  Note that the wiring 3608 is a wiring for transmitting a signal input to the second scan line driver circuit 3603, the first scan line driver circuit 3606, and the signal line driver circuit 3601, and is an FPC (flexible flexible cable) serving as an external input terminal. Print circuit) 3609 receives a video signal, a clock signal, a start signal, and the like. An IC chip (a semiconductor chip in which a memory circuit, a buffer circuit, or the like is formed) 3618 and an IC chip 3619 are mounted on a joint portion between the FPC 3609 and the display panel by a COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The display device in this specification includes not only a display panel body but also a state in which an FPC or a PWB is attached thereto. In addition, it is assumed that an IC chip or the like is mounted.

  Next, a cross-sectional structure is described with reference to FIG. A pixel portion 3602 and its peripheral driver circuits (a second scan line driver circuit 3603, a first scan line driver circuit 3606, and a signal line driver circuit 3601) are formed over the substrate 3610. Here, a signal line A driver circuit 3601 and a pixel portion 3602 are shown.

  Note that the signal line driver circuit 3601 forms a CMOS circuit using an N-channel TFT 3620 and a P-channel TFT 3621. In this embodiment mode, a display panel in which a peripheral drive circuit is integrally formed on a substrate is shown; however, it is not always necessary, and all or a part of the peripheral drive circuit is formed on an IC chip or the like and mounted by COG or the like. You may do it.

  The pixel portion 3602 includes a plurality of circuits that form a pixel including a switching TFT 3611 and a driving TFT 3612. Note that the source electrode of the driving TFT 3612 is electrically connected to the first electrode 3613. An insulator 3614 is formed so as to cover an end portion of the first electrode 3613. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 3614. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 3614, it is preferable that only the upper end portion of the insulator 3614 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 3614, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  Over the first electrode 3613, a layer 3616 containing an organic compound and a second electrode 3617 are formed. Here, as a material used for the first electrode 3613 which functions as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

  The layer 3616 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 3616 containing an organic compound, a Group 4 metal complex of the periodic table of elements is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer. However, in this embodiment, an inorganic compound is used for part of a film made of an organic compound. Will also be included. Further, a known triplet material can be used.

Further, as a material used for the second electrode (cathode) 3617 formed over the layer 3616 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof MgAg, MgIn, AlLi, or the like) , CaF ₂ , or calcium nitride) may be used. Note that in the case where light generated in the layer 3616 containing an organic compound transmits the second electrode 3617, the second electrode (cathode) 3617 includes a thin metal film and a transparent conductive film (ITO ( A stack of indium tin oxide), an indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, the sealing substrate 3604 is bonded to the substrate 3610 with the sealant 3605, whereby the display element 3622 is provided in the space 3607 surrounded by the substrate 3610, the seal substrate 3604, and the sealant 3605. Note that the space 3607 includes a structure filled with a sealant 3605 in addition to a case where the space 3607 is filled with an inert gas (such as nitrogen or argon).

  Note that an epoxy-based resin is preferably used for the sealant 3605. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), polyester, acrylic, or the like can be used as a material used for the sealing substrate 3604.

  A display panel can be obtained as described above.

  As shown in FIG. 10, the signal line driver circuit 3601, the pixel portion 3602, the second scan line driver circuit 3603, and the first scan line driver circuit 3606 are integrally formed, whereby the cost of the display device can be reduced.

  Note that as a structure of the display panel, a signal line driver circuit 3601, a pixel portion 3602, a second scan line driver circuit 3603, and a first scan line driver circuit 3606 are integrally formed as shown in FIG. The structure is not limited, and the signal line driver circuit 4201 shown in FIG. 11A corresponding to the signal line driver circuit 3601 may be formed over the IC chip and mounted on the display panel with COG or the like. Note that the substrate 4200, the pixel portion 4202, the second scan line driver circuit 4203, the first scan line driver circuit 4204, the FPC 4205, the IC chip 4206, the IC chip 4207, the sealing substrate 4208, and the sealing material in FIG. Reference numeral 4209 denotes a substrate 3610, a pixel portion 3602, a second scan line driver circuit 3603, a first scan line driver circuit 3606, an FPC 3609, an IC chip 3618, an IC chip 3619, a sealing substrate 3604, and a sealing material in FIG. It corresponds to 3605.

  That is, only the signal line driver circuit that requires high-speed operation among the driver circuits is formed on the IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

  The first scan line driver circuit 4203 and the second scan line driver circuit 4204 provided with the shift register described in the above embodiment mode are formed integrally with the pixel portion 4202, so that cost can be reduced.

  Thus, the cost of a high-definition display device can be reduced. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 4205 and the substrate 4200, the substrate area can be effectively used.

  In addition, the signal line driver circuit 4211 in FIG. 11B corresponding to the signal line driver circuit 3601, the second scan line driver circuit 3603, and the first scan line driver circuit 3606 in FIG. The line driver circuit 4214 and the first scan line driver circuit 4213 may be formed over an IC chip and mounted on the display panel with COG or the like. In this case, a high-definition display device can have lower power consumption. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use polysilicon for a semiconductor layer of a transistor used in the pixel portion. Note that the substrate 4210, the pixel portion 4212, the FPC 4215, the IC chip 4216, the IC chip 4217, the sealing substrate 4218, and the sealant 4219 in FIG. 11B are the substrate 3610, the pixel portion 3602, the FPC 3609, and the IC in FIG. It corresponds to a chip 3618, an IC chip 3619, a sealing substrate 3604, and a sealing material 3605.

  In addition, cost can be reduced by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 4212. Further, a large display panel can be manufactured.

  Further, examples of display elements applicable to the display element 3622 are shown in FIGS. That is, a structure of a display element that can be applied to the pixel described in the above embodiment mode will be described with reference to FIGS.

  15A, an anode 4402 over a substrate 4401, a hole injection layer 4403 made of a hole injection material, a hole transport layer 4404 made of a hole transport material thereon, a light-emitting layer 4405, an electron In this element structure, an electron transport layer 4406 made of a transport material, an electron injection layer 4407 made of an electron injection material, and a cathode 4408 are stacked. Here, the light emitting layer 4405 may be formed of only one kind of light emitting material, but may be formed of two or more kinds of materials. Further, the structure of the element of the present invention is not limited to this structure.

  In addition to the stacked structure in which the functional layers shown in FIGS. 15A and 15B are stacked, an element using a polymer compound and a triplet light emitting material that emits light from a triplet excited state are used in the light emitting layer. There are many variations, such as high-efficiency elements. The present invention can also be applied to a white display element obtained by controlling the carrier recombination region by the hole blocking layer and dividing the light emitting region into two regions.

  In the element manufacturing method of the present invention illustrated in FIG. 15A, first, a hole injection material, a hole transport material, and a light-emitting material are sequentially deposited on a substrate 4401 having an anode 4402 (ITO). Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 4408 is formed by vapor deposition.

  Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as long as they are organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

  The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as —N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As an electron transport material, a metal complex is often used, and Alq, BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”), bis (10-hydroxybenzo [h] -quinolinato) There are metal complexes having a quinoline skeleton or a benzoquinoline skeleton such as beryllium (hereinafter referred to as “BeBq”). Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like Oxadiazole derivatives of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (hereinafter “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

  The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the light emitting material, various fluorescent dyes are effective in addition to metal complexes such as Alq, Almq, BeBq, BAlq, Zn (BOX) ₂ and Zn (BTZ) ₂ . As fluorescent dyes, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

  A highly reliable display element can be manufactured by combining the materials having the functions described above.

  In addition, if the polarity of the driving transistor having the pixel structure described in the above embodiment is changed to be an N-channel transistor, the potential of the counter electrode of the display element and the potential set to the power supply line are reversed. A display element in which layers are formed in the reverse order of FIG. 15A can be used. That is, as shown in FIG. 15B, a cathode 4408 over an substrate 4401, an electron injection layer 4407 made of an electron injection material, and an electron transport layer 4406 made of an electron transport material, a light emitting layer 4405, and a hole transport. In this element structure, a hole transport layer 4404 made of a material, a hole injection layer 4403 made of a hole injection material, and an anode 4402 are laminated.

  Further, in order to extract light emission from the display element, at least one of the anode and the cathode only needs to be transparent. Then, a TFT and a display element are formed on the substrate, and a top emission that extracts light emission from a surface opposite to the substrate, a bottom emission that extracts light emission from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. There is a display element having a dual emission structure in which light emission is extracted from the pixel, and the pixel structure described in the above embodiment can be applied to a display element having any emission structure.

  A display element having a top emission structure will be described with reference to FIG.

  A driving TFT 4501 is formed over a substrate 4500 with a base film 4505 interposed therebetween, a first electrode 4502 is formed in contact with a source electrode of the driving TFT 4501, and a layer 4503 containing an organic compound and a second electrode 4504 are formed thereover. Is formed.

  The first electrode 4502 is an anode of the display element. The second electrode 4504 is a cathode of the display element. That is, a display element is a portion where the layer 4503 containing an organic compound is sandwiched between the first electrode 4502 and the second electrode 4504.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the display element can be extracted from the top surface as indicated by an arrow in FIG. That is, when applied to the display panel in FIG. 10, light is emitted to the sealing substrate 3604 side. Therefore, when a display element having a top emission structure is used for a display device, the sealing substrate 3604 is a light-transmitting substrate.

  In the case where an optical film is provided, an optical film may be provided over the sealing substrate 3604.

  Next, a display element having a bottom emission structure will be described with reference to FIG. Except for the emission structure, the display element has the same structure as that in FIG.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A metal film can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

  In this manner, light from the display element can be extracted to the lower surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 10, light is emitted to the substrate 3610 side. Therefore, when a display element having a bottom emission structure is used for a display device, the substrate 3610 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 3610 may be provided with an optical film.

  Next, a display element having a dual emission structure will be described with reference to FIG. Except for the emission structure, the display element has the same structure as that in FIG.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the display element can be extracted on both sides as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 10, light is emitted to the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element having a dual emission structure is used for a display device, both the substrate 3610 and the sealing substrate 3604 are light-transmitting substrates.

  In the case where an optical film is provided, the optical film may be provided on both the substrate 3610 and the sealing substrate 3604.

  Further, the present invention can be applied to a display device that realizes full color display using a white display element and a color filter.

  For example, as shown in FIG. 13, a base film 4602 is formed on a substrate 4600, a driving TFT 4601 is formed thereon, a first electrode 4603 is formed in contact with the source electrode of the driving TFT 4601, A layer 4604 containing an organic compound and a second electrode 4605 may be formed.

  The first electrode 4603 is an anode of the display element. The second electrode 4605 is a cathode of the display element. That is, a display element is a portion where the layer 4604 containing an organic compound is sandwiched between the first electrode 4603 and the second electrode 4605. In the configuration of FIG. 13, white light is emitted. A red color filter 4606R, a green color filter 4606G, and a blue color filter 4606B are provided above the display element, so that full color display can be performed. Further, a black matrix (also referred to as BM) 4607 for separating these color filters is provided.

  The above-described structure of the display element can be used in combination, and can be appropriately used for a display device driven by the pulse output circuit and the shift register of the present invention. In addition, the configuration of the display panel and the display element described above are examples, and other configurations can be applied as a matter of course.

(Embodiment 6)
The present invention can be applied to various electronic devices. Specifically, it can be applied to driving of a display portion of an electronic device. Such electronic devices include cameras such as video cameras and digital cameras, goggle-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, personal digital assistants (mobile computers, mobile phones, Portable game machine or electronic book), image reproducing apparatus provided with a recording medium (specifically, an apparatus equipped with a light emitting device capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image) Etc.

  FIG. 14A illustrates a light-emitting device, which includes a housing 6001, a support base 6002, a display portion 6003, a speaker portion 6004, a video input terminal 6005, and the like. The display device of the present invention can be used for the display portion 6003. The light emitting devices include all information display light emitting devices such as for personal computers, for receiving television broadcasts, and for displaying advertisements. By driving the display portion 6003 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14B shows a camera, which includes a main body 6101, a display portion 6102, an image receiving portion 6103, operation keys 6104, an external connection port 6105, a shutter button 6106, and the like. By driving the display portion 6102 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14C illustrates a computer, which includes a main body 6201, a housing 6202, a display portion 6203, a keyboard 6204, an external connection port 6205, a pointing device 6206, and the like. By driving the display portion 6203 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14D illustrates a mobile computer, which includes a main body 6301, a display portion 6302, a switch 6303, operation keys 6304, an infrared port 6305, and the like. By driving the display portion 6302 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A 6403, a display portion B 6404, and a recording medium (such as a DVD). A reading unit 6405, an operation key 6406, a speaker unit 6407, and the like are included. The display portion A 6403 can mainly display image information, and the display portion B 6404 can mainly display character information. Power consumption can be reduced by driving the display portion A 6403 or the display portion B 6404 with the use of the shift register of the present invention.

  FIG. 14F illustrates a goggle type display including a main body 6501, a display portion 6502, and an arm portion 6503. By driving the display portion 6502 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14G illustrates a video camera, which includes a main body 6601, a display portion 6602, a housing 6603, an external connection port 6604, a remote control reception portion 6605, an image receiving portion 6606, a battery 6607, an audio input portion 6608, operation keys 6609, and an eyepiece. Part 6610 and the like. By driving the display portion 6602 using the shift register of the present invention, power consumption can be reduced.

  FIG. 14H illustrates a mobile phone, which includes a main body 6701, a housing 6702, a display portion 6703, an audio input portion 6704, an audio output portion 6705, operation keys 6706, an external connection port 6707, an antenna 6708, and the like. By driving the display portion 6703 using the shift register of the present invention, power consumption can be reduced.

  Thus, the present invention can be applied to all electronic devices.

FIG. 6 illustrates an example of a shift register and a pulse output circuit of the present invention. The figure which shows an example of operation | movement of the pulse output circuit of this invention. The figure which shows an example of operation | movement of the pulse output circuit of this invention. The figure which shows an example of operation | movement of the pulse output circuit of this invention. The figure which compared and showed operation | movement of this invention and the conventional pulse output circuit. FIG. 6 illustrates an example of a shift register and a pulse output circuit of the present invention. The figure which shows an example of the conventional shift register and pulse output circuit, and its operation | movement. The figure which shows an example of the conventional shift register and pulse output circuit, and its operation | movement. FIG. 6 illustrates an example of a display device provided with a shift register of the present invention. FIG. 6 illustrates an example of a display device provided with a shift register of the present invention. FIG. 6 illustrates an example of a display device provided with a shift register of the present invention. FIG. 6 illustrates an example of a display device provided with a shift register of the present invention. FIG. 6 illustrates an example of a display device provided with a shift register of the present invention. FIG. 13 illustrates an example of an electronic device in which a shift register of the present invention is provided. FIG. 13 illustrates an example of a display element of a display device provided with the shift register of the present invention.

Explanation of symbols

10 pulse output circuit 11 signal line 12 signal line 13 signal line 14 signal line 21 input terminal 22 input terminal 23 input terminal 24 input terminal 25 input terminal 26 input terminal 27 output terminal 31 power supply line 32 power supply line 33 power supply line 34 power supply line 35 Power supply line 36 Power supply line 51 Period 52 Period 53 Period 54 Period 55 Period 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 111 Capacitor element 112 Capacitor element

Claims (5)

A first transistor to a ninth transistor; a capacitor; a first input terminal to a sixth input terminal; and an output terminal.
The first transistor has a first electrode electrically connected to a first power supply line, a second electrode electrically connected to a gate electrode of the third transistor, and a gate electrode connected to the fourth transistor. Is electrically connected to the input terminal of
The second transistor has a first electrode electrically connected to a second power supply line, a second electrode electrically connected to a gate electrode of the third transistor, and a gate electrode connected to the fourth transistor. Electrically connected to the gate electrode of the transistor of
The third transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the output terminal,
The fourth transistor has a first electrode electrically connected to a third power supply line, a second electrode electrically connected to the output terminal,
The fifth transistor has a first electrode electrically connected to a fourth power supply line, a second electrode electrically connected to a gate electrode of the fourth transistor, and a gate electrode connected to the fourth power line. Is electrically connected to the input terminal of
The sixth transistor has a first electrode electrically connected to the fourth power supply line, a second electrode electrically connected to a gate electrode of the fourth transistor, and a gate electrode connected to the fourth power line. 5 is electrically connected to the input terminal,
The seventh transistor has a first electrode electrically connected to a fifth power supply line, a second electrode electrically connected to a gate electrode of the fourth transistor, and a gate electrode connected to the sixth transistor. Is electrically connected to the input terminal of
The eighth transistor has a first electrode electrically connected to the fifth power supply line, a second electrode electrically connected to the second electrode of the ninth transistor, and a gate electrode Electrically connected to the second input terminal;
The ninth transistor has a first electrode electrically connected to a gate electrode of the fourth transistor, a gate electrode electrically connected to the third input terminal,
The capacitor element has a first electrode electrically connected to a sixth power supply line, a second electrode electrically connected to a gate electrode of the fourth transistor ,
A first clock signal is input to the second input terminal,
A second clock signal is input to the third input terminal,
The period in which the first clock signal is one of high level or low level overlaps the period in which the second clock signal is one of high level or low level,
The eighth transistor is on when the first clock signal is one of high level or low level, and is off when the first clock signal is the other of high level or low level,
The ninth transistor is on when the second clock signal is one of high level or low level, and is off when the second clock signal is the other of high level or low level. A semiconductor device characterized by the above. A first transistor to a ninth transistor; a capacitor; a first input terminal to a sixth input terminal; and an output terminal.
In the first transistor, a first potential is supplied to a first electrode, a second electrode is electrically connected to a gate electrode of the third transistor, and a gate electrode is connected to the fourth input terminal. Electrically connected,
In the second transistor, a second potential is supplied to the first electrode, the second electrode is electrically connected to the gate electrode of the third transistor, and the gate electrode is the gate of the fourth transistor. Electrically connected to the electrodes,
The third transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the output terminal,
In the fourth transistor, the second potential is supplied to a first electrode, the second electrode is electrically connected to the output terminal,
In the fifth transistor, the second potential is supplied to the first electrode, the second electrode is electrically connected to the gate electrode of the fourth transistor, and the gate electrode is the fourth input terminal. Electrically connected to the
In the sixth transistor, the second potential is supplied to the first electrode, the second electrode is electrically connected to the gate electrode of the fourth transistor, and the gate electrode is the fifth input terminal. Electrically connected to the
In the seventh transistor, the first potential is supplied to the first electrode, the second electrode is electrically connected to the gate electrode of the fourth transistor, and the gate electrode is the sixth input terminal. Electrically connected to the
In the eighth transistor, the first potential is supplied to a first electrode, a second electrode is electrically connected to a second electrode of the ninth transistor, and a gate electrode is connected to the second electrode. Electrically connected to the input terminal,
The ninth transistor has a first electrode electrically connected to a gate electrode of the fourth transistor, a gate electrode electrically connected to the third input terminal,
In the capacitor, the second potential is supplied to a first electrode, the second electrode is electrically connected to a gate electrode of the fourth transistor ,
A first clock signal is input to the second input terminal,
A second clock signal is input to the third input terminal,
The period in which the first clock signal is one of high level or low level overlaps the period in which the second clock signal is one of high level or low level,
The eighth transistor is on when the first clock signal is one of high level or low level, and is off when the first clock signal is the other of high level or low level,
The ninth transistor is on when the second clock signal is one of high level or low level, and is off when the second clock signal is the other of high level or low level. A semiconductor device characterized by the above. In claim 1 or claim 2 ,
The semiconductor device, wherein the first to ninth transistors are formed using amorphous silicon. In any one of Claims 1 thru | or 3 ,
The semiconductor device, wherein the first to ninth transistors are N-channel thin film transistors. An electronic device including the semiconductor device according to any one of claims 1 to 4.

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