JP5478165B2 - Semiconductor device - Google Patents

Description

The present invention relates to a driver circuit (also referred to as a pulse output circuit or a shift register). Alternatively, the present invention relates to a display device including a driver circuit formed over the same substrate as the pixel portion. Alternatively, the present invention relates to an electronic device including the display device.

With the spread of large display devices such as liquid crystal televisions, higher value-added products are required for display devices, and development is ongoing. In particular, a technique in which a driving circuit such as a scanning line driving circuit is formed on the same substrate as the pixel portion using a thin film transistor (TFT) whose channel region is formed of an amorphous semiconductor can reduce cost and improve reliability. In order to make a significant contribution, development is actively underway.

A thin film transistor in which a channel region is formed using an amorphous semiconductor causes deterioration such as an increase in threshold voltage or a decrease in field-effect mobility. As the deterioration of the thin film transistor progresses, there is a problem that the drive circuit becomes difficult to operate and an image cannot be displayed. Therefore, Patent Document 1 discloses a shift register that can suppress deterioration of a thin film transistor. In Patent Document 1, two thin film transistors are provided to suppress deterioration of characteristics of the thin film transistors, and the thin film transistors are connected between an output terminal of a flip-flop and a wiring to which VSS (hereinafter, negative power supply) is supplied. Then, one thin film transistor and the other thin film transistor are alternately turned on. By doing so, the time for which the thin film transistor is turned on can be shortened to about a half of one frame period, so that the deterioration of characteristics of the thin film transistor can be suppressed to some extent.

JP-A-2005-050502

An object of one embodiment of the present invention is to provide a driver circuit that reduces the degree of deterioration of characteristics of a thin film transistor, reduces malfunction in the circuit, and guarantees more accurate operation.

  One embodiment of the present invention includes first to ninth transistors, first to fifth input terminals, and output terminals, and is electrically connected to the first to sixth power lines. The first transistor has a first electrode electrically connected to the first power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode. Is electrically connected to the fourth input terminal, and the second transistor has the first electrode electrically connected to the second power supply line, and the second electrode is the first electrode of the ninth transistor. And the gate electrode is electrically connected to the gate electrode of the fourth transistor. The third transistor has the first electrode electrically connected to the first input terminal and the second transistor. The electrode is electrically connected to the output terminal, and the fourth transistor includes the first electrode The fifth transistor is electrically connected to the third power supply line, the second electrode is electrically connected to the output terminal, the fifth transistor has the first electrode electrically connected to the fourth power supply line, The second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, the gate electrode is electrically connected to the fourth input terminal, and the sixth transistor includes the first transistor The electrode is electrically connected to the fifth power supply line, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is connected to the fifth input terminal. Electrically connected, the seventh transistor has a first electrode electrically connected to the fifth power supply line, a second electrode electrically connected to the first electrode of the eighth transistor, A gate electrode electrically connected to the third input terminal; In the transistor, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, the gate electrode is electrically connected to the second input terminal, and the ninth transistor Is a pulse output circuit in which the gate electrode is electrically connected to the sixth input terminal.

  In one embodiment of the present invention, the potential of the first power supply line is higher than the potentials of the second power supply line, the third power supply line, the fourth power supply line, the fifth power supply line, and the sixth power supply line. A pulse output circuit may be used.

  In one embodiment of the present invention, a pulse output circuit in which the potential of the fifth power supply line and the potential of the sixth power supply line are lower than the potential of the first power supply line may be used.

  In one embodiment of the present invention, the first to ninth transistors may be pulse output circuits formed using an oxide semiconductor.

  In one embodiment of the present invention, the first to ninth transistors may be pulse output circuits that are N-channel thin film transistors.

  One embodiment of the present invention includes first to thirteenth transistors, first to fifth input terminals, and first to second output terminals. The first power supply line To the ninth power supply line, the first transistor has the first electrode electrically connected to the first power supply line, and the second electrode has the first electrode of the ninth transistor. And the gate electrode is electrically connected to the fourth input terminal. The second transistor has the first electrode electrically connected to the second power supply line and the second electrode The ninth transistor is electrically connected to the first electrode, the gate electrode is electrically connected to the gate electrode of the fourth transistor, and the third transistor has the first electrode connected to the first input terminal. Electrically connected, the second electrode is electrically connected to the first output terminal, In the transistor No. 4, the first electrode is electrically connected to the third power supply line, the second electrode is electrically connected to the first output terminal, and the fifth transistor has the first electrode Electrically connected to the fourth power supply line, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the fourth input terminal; The sixth transistor has a first electrode electrically connected to the fifth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. The gate electrode is electrically connected to the fifth input terminal, the seventh transistor is electrically connected to the fifth power supply line, and the second electrode is electrically connected to the eighth input terminal. A gate electrode electrically connected to the first electrode of the transistor; The eighth transistor is electrically connected to the third input terminal, and the eighth transistor has the second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. The ninth transistor has a gate electrode electrically connected to the sixth power supply line, and the tenth transistor has the first electrode electrically connected to the first input terminal. , The second electrode is electrically connected to the second output terminal, the gate electrode is electrically connected to the gate electrode of the third transistor, and the eleventh transistor has the first electrode connected to the first electrode. 8 is electrically connected to the power supply line, the second electrode is electrically connected to the second output terminal, and the gate electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. Connected to the 12th In the register, the first electrode is electrically connected to the ninth power supply line, the second electrode is electrically connected to the second output terminal, and the gate electrode is electrically connected to the gate electrode of the seventh transistor. The thirteenth transistor has a first electrode electrically connected to the seventh power supply line, a second electrode electrically connected to the first output terminal, and a gate electrode connected to the seventh power supply line. It is a pulse output circuit electrically connected to a gate electrode of a transistor.

  In one embodiment of the present invention, the pulse output circuit includes an (m−1) th pulse output circuit, an mth pulse output circuit, an (m + 1) th pulse output circuit, and an (m + 2) th pulse output circuit (m + 2). ≧ 2) and includes first to fourth signal lines for outputting a clock signal. In the m-th pulse output circuit, the first to third input terminals are the first input terminal to the first input line. Are electrically connected to three different signal lines among the first to fourth signal lines, and the fourth input terminal is electrically connected to the output terminal of the (m−1) th pulse output circuit. The fifth input terminal is electrically connected to the output terminal of the (m + 2) th pulse output circuit, and the output terminal is electrically connected to the fourth input terminal of the (m + 1) th pulse output circuit. Shift register.

  In one embodiment of the present invention, each of the first signal line to the fourth signal line may be a shift register that sequentially outputs a clock signal delayed by ¼ cycle.

  According to one embodiment of the present invention, a driver circuit that reduces the degree of deterioration of characteristics of a thin film transistor, reduces malfunctions in the circuit, and ensures more accurate operation can be provided.

FIG. 6 is a diagram illustrating an example of a shift register and a pulse output circuit. The figure which shows an example of operation | movement of a pulse output circuit. The figure which shows an example of operation | movement of a pulse output circuit. The figure which shows an example of operation | movement of a pulse output circuit. The figure which compared and showed operation | movement of the pulse output circuit. FIG. 6 is a diagram illustrating an example of a shift register and a pulse output circuit. FIG. 10 illustrates an example of a display device provided with a shift register. FIG. 10 illustrates an example of a display device provided with a shift register. FIG. 10 illustrates an example of a display device provided with a shift register. FIG. 10 illustrates an example of a display device provided with a shift register. FIG. 10 illustrates an example of a display device provided with a shift register. FIG. 6 illustrates an example of an electronic device provided with a shift register. FIG. 14 illustrates an example of a display element of a display device provided with a shift register. FIG. 13 shows a display on a display panel provided with a shift register. The timing chart of a shift register, and the figure which shows the signal waveform observed.

  Hereinafter, embodiments and examples of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings.

(Embodiment 1)
In this embodiment, an example of a pulse output circuit which is a driver circuit and a shift register including the pulse output circuit will be described with reference to drawings.

The shift register described in this embodiment includes a first pulse output circuit _{10_1} to an nth pulse output circuit _{10_n} (n ≧ 2), and first signal lines 11 to 4 for outputting clock signals. It has a line 14 (see FIG. 1A). The first signal line 11 outputs a first clock signal (CK1), the second signal line 12 outputs a second clock signal (CK2), and the third signal line 13 outputs a third clock signal. (CK3) is output, and the fourth signal line 14 outputs a fourth clock signal (CK4).

  The clock signal (CK) is a signal that repeats an H (High) signal and an L (Low) signal at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are In order, it is delayed by 1/4 period. In this embodiment, driving of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4).

Each of the first pulse output circuit _{10_1} to the nth pulse output circuit _{10_n} includes a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a 5 input terminals 25 and output terminals 26 (see FIG. 1B).

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first signal line 11 to the fourth signal line 14. For example, in FIG. 1, in the first pulse output circuit 10 _{_ 1} , the first input terminal 21 is electrically connected to the first signal line 11, and the second input terminal 22 is connected to the second signal line 12. The third input terminal 23 is electrically connected to the third signal line 13. In the second pulse output circuit _{10_2} , the first input terminal 21 is electrically connected to the second signal line 12, and the second input terminal 22 is electrically connected to the third signal line 13. The third input terminal 23 is electrically connected to the fourth signal line 14.

  In the m-th pulse output circuit (m ≧ 2) of the shift register described in this embodiment, the fourth input terminal 24 is electrically connected to the output terminal 26 of the (m−1) th pulse output circuit. The fifth input terminal 25 is electrically connected to the output terminal 26 of the (m + 2) th pulse output circuit, and the output terminal 26 is electrically connected to the fourth input terminal 24 of the (m + 1) th pulse output circuit. And outputs a signal to OUT (m).

For example, in the third pulse output circuit _{10_3} , the fourth input terminal 24 is electrically connected to the output terminal 26 of the second pulse output circuit _{10_2} , and the fifth input terminal 25 is the fifth pulse output. connected output terminals 26 electrically in circuit _{10 _5,} the output terminal 26 and the fourth pulse output circuit ₁₀ the fourth input terminal 24 and the first fifth input terminal 25 of the pulse output circuit _{10 _1 _4} Electrically connected.

In the first pulse output circuit _{10_1} , the first start pulse (SP1) is input to the fourth input terminal 24. In the (n−1) th pulse output circuit 10 _(n−1) , the second start pulse (SP 2) is input to the fifth input terminal 25. In the n-th pulse output circuit 10 — _n) , the third start pulse (SP3) is input to the fifth input terminal 25. Note that the second start pulse (SP2) and the third start pulse (SP3) may be signals input from the outside, or may be signals generated separately inside the drive circuit. For example, the (n + 1) th pulse output circuit 10 _{(n + 1)} and the (n + 2) th pulse output circuit 10 _{(n + 2)} that do not contribute to the pulse output to the display unit are provided (also referred to as a dummy stage). It is also possible to generate signals corresponding to the second start pulse (SP2) and the third start pulse (SP3).

Next, specific structures of the first pulse output circuit _{10_1} to the n-th pulse output circuit _{10_n} are described.

Each of the first pulse output circuit _{10_1} to the nth pulse output circuit _{10_n} includes a first transistor 101 to a ninth transistor 109 (see FIG. 1C). In addition to the first input terminal 21 to the fifth input terminal 25 and the output terminal 26 described above, the first transistor 101 to the ninth transistor 109 are connected from the first power supply line 31 to the sixth power supply line 36. A signal is supplied.

  In the first transistor 101, the first electrode (one of the source electrode and the drain electrode) is electrically connected to the first power supply line 31, and the second electrode (the other of the source electrode and the drain electrode) is the ninth. The transistor 109 is electrically connected to the first electrode, and the gate electrode is electrically connected to the fourth input terminal 24. In the second transistor 102, the first electrode is electrically connected to the second power supply line 32, the second electrode is electrically connected to the first electrode of the ninth transistor 109, and the gate electrode is The fourth transistor 104 is electrically connected to the gate electrode. The third transistor 103 has a first electrode electrically connected to the first input terminal 21 and a second electrode electrically connected to the output terminal 26. The fourth transistor 104 has a first electrode electrically connected to the third power supply line 33 and a second electrode electrically connected to the output terminal 26. In the fifth transistor 105, the first electrode is electrically connected to the fourth power supply line 34, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. The gate electrode is electrically connected to the fourth input terminal 24. In the sixth transistor 106, the first electrode is electrically connected to the fifth power supply line 35, and the second electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104. And the gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 107 has a first electrode electrically connected to the fifth power supply line 35, a second electrode electrically connected to the second electrode of the eighth transistor 108, and a gate electrode The third input terminal 23 is electrically connected. In the eighth transistor 108, the first electrode is electrically connected to the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104, and the gate electrode is electrically connected to the second input terminal 22. Has been. In the ninth transistor 109, the first electrode is electrically connected to the second electrode of the first transistor 101 and the second electrode of the second transistor 102, and the second electrode is connected to the third transistor 103. The gate electrode is electrically connected to the sixth power supply line 36.

  In FIG. 1C, a connection point between the gate electrode of the third transistor 103 and the second electrode of the ninth transistor 109 is a node A. The gate electrode of the second transistor 102, the gate electrode of the fourth transistor 104, the second electrode of the fifth transistor 105, the second electrode of the sixth transistor 106, and the first electrode of the eighth transistor 108 A connection point of the electrodes is referred to as node B. A connection point of the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the output terminal 26 is a node C.

Note that a capacitor for performing a bootstrap operation by bringing the node A into a floating state may be additionally provided between the node A and the node C. Further, in order to hold the potential of the node B, a capacitor in which one electrode is electrically connected to the node B may be separately provided.

Note that the clock signal supplied to the gate electrode of the seventh transistor 107 by the third input terminal and the clock signal supplied to the gate electrode of the eighth transistor 108 by the second input terminal are The same effect can be obtained even if the wiring relationship is changed so that the clock signal supplied to the gate electrode by the second input terminal and the clock signal supplied to the eighth gate electrode by the third input terminal are obtained. Note that as in the period of FIG. 3D, the seventh transistor 107 and the eighth transistor 108 are turned off, the seventh transistor 107 is turned off, the eighth transistor 108 is turned on, When the seventh transistor 107 is turned off and the eighth transistor 108 is turned off, the potential of the node B is lowered by the potential of the second input terminal 22 and the third input terminal 23 being lowered. Occurs twice due to a decrease in the potential of the gate electrode of the seventh transistor 107 and a decrease in the potential of the gate electrode of the eighth transistor 108. On the other hand, both the seventh transistor 107 and the eighth transistor 108 are turned on as in the period of FIG. 3D, and the seventh transistor 107 is turned on as in the period of FIG. When the eighth transistor 108 is turned off and then the seventh transistor 107 is turned off and the eighth transistor 108 is turned off as in the period of FIG. 4B, the second input terminal 22 is turned off. Further, the decrease in the potential of the node B caused by the decrease in the potential of the third input terminal 23 can be reduced at a time due to the decrease in the potential of the gate electrode of the eighth transistor 108. Therefore, by setting the clock signal supplied to the gate electrode of the seventh transistor 107 by the third input terminal and the clock signal supplied to the eighth gate electrode by the second input terminal, the potential of the node B can be reduced. It is preferable to reduce the fluctuation because noise can be reduced.

  Next, the operation of the shift register shown in FIG. 1 will be described with reference to FIGS. Specifically, in the timing chart of FIG. 2, description is divided into a first period 51, a second period 52, a third period 53, a fourth period 54, and a fifth period 55. Note that in the following description, the first transistor 101 to the ninth transistor 109 are N-channel thin film transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). Shall be.

Here, the output of the first pulse output circuit _{10_1} will be described. In the second pulse output circuit _{10_1} , the first input terminal 21 is electrically connected to the first signal line 11 that supplies the first clock signal (CK1), and the second input terminal 22 is the second input terminal 22. Is electrically connected to the second signal line 12 that supplies the second clock signal (CK2), and the third input terminal 23 is electrically connected to the third signal line 13 that supplies the third clock signal (CK3). It is connected.

  Note that the first potential (VDD) is supplied to the first power supply line 31, the second potential (VCC) is supplied to the fifth power supply line 35 and the sixth power supply line 36, and the second potential (VCC) is supplied. A third potential (VSS) is supplied to the power supply line 32 to the fourth power supply line 34. Here, VDD> VCC> VSS. The first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and are VDD when the level is H and VSS when the level is the L level. And In addition, here, VSS is set to 0 for simplification of description, but the present invention is not limited to this. Note that the difference between VSS and VDD and the difference between VCC and VSS are larger than the threshold voltage of the transistor, that is, the transistor is turned on (conductive state). Note that the potential applied to the gate electrodes of the second transistor 102 and the fourth transistor 104 can be kept low by making the potential of the fifth power supply line 35 lower than the potential of the first power supply line 31. The shift of the threshold voltage of the second transistor 102 and the fourth transistor 104 can be reduced and deterioration can be suppressed.

In the first period 51, the first start pulse (SP1) is at an H level and the first transistor 101 and the fifth transistor electrically connected to the fourth input terminal 24 of the second pulse output circuit _{10_1} The transistor 105 is turned on. Since the third clock signal (CK3) is also at the H level, the seventh transistor 107 is also turned on. Further, the second potential VCC is applied to the gate of the ninth transistor 109, and the ninth transistor is also turned on (see FIG. 3A).

  At this time, since the first transistor 101 and the ninth transistor are on, the potential of the node A is increased. Further, since the fifth transistor 105 is on, the potential of the node B drops. Note that the first transistor is off and the potential of the node C is at an L level.

  At this time, the potential of the second transistor of the first transistor 101 is set to the threshold of the first transistor 101 from the potential of the first power supply line 31 with the second electrode of the first transistor 101 as a source. Since the value voltage is subtracted, it becomes VDD-Vth101 (Vth101 is the threshold voltage of the first transistor 101). The potential of the node A is a value obtained by subtracting the threshold voltage of the ninth transistor 109 from (VDD−Vth101) with the second electrode of the ninth transistor 109 serving as a source. Vth109 (Vth109 is the threshold voltage of the ninth transistor 109). Then, the first transistor 101 and the ninth transistor 109 are turned off, and the node A is in a floating state while maintaining (VDD−Vth101−Vth109).

  Here, in the third transistor 103, the potential of the gate electrode is (VDD−Vth101−Vth109). When the voltage between the gate and the source of the third transistor 103 exceeds the threshold voltage, that is, when VDD−Vth101−Vth109VSS> Vth103 (Vth103 is the threshold voltage of the third transistor 103). The third transistor 103 is turned on.

In the second period 52, the first input terminal 21 of the first pulse output circuit _{10_1} is switched from the L level to the H level. Here, since the third transistor 103 is on, a current is generated between the source and the drain, and the node C (the output terminal 26 (OUT (1))), that is, the second electrode of the third transistor 103 is generated. In this case, the potential of the source electrode starts to rise. There is a capacitive coupling due to parasitic capacitance between the gate and the source of the third transistor 103, and the potential of the gate electrode of the third transistor 103 which is in a floating state increases as the potential of the node C increases (boot) Strap action). Eventually, the potential of the gate electrode of the third transistor 103 becomes higher than VDD + Vth103, and the potential of the node C becomes equal to VDD (see FIGS. 2 and 3B).

At this time, since the fourth input terminal 24 of the first pulse output circuit _{10_1} is at the H level by the first start pulse (SP1), the fifth transistor 105 is turned on and the node B is at the L level. Is maintained. Therefore, when the potential of the node C rises from the L level to the H level, it is possible to suppress problems due to capacitive coupling between the node B and the node C.

  Next, in the third period 53, the first start pulse (SP1) becomes L level, and the first transistor 101 and the fifth transistor 105 are turned off. In addition, since the first clock signal (CK1) is kept at the H level following the second period 52 and the potential of the node A does not change following the second period 52, the first electrode of the transistor 103 Is supplied with an H level signal (see FIG. 3C). Note that in the third period 53, each transistor is turned off, so that the node B is in a floating state. However, since the potential of the node C does not change, the influence of the failure due to the capacitive coupling between the node B and the node C is hardly affected. It can be ignored.

Note that as shown in FIG. 1C, by providing the ninth transistor 109 to which the first potential VDD is applied to the gate, the following advantages are obtained before and after the bootstrap operation.

When there is no ninth transistor 109 to which the second potential VCC is applied to the gate, when the potential of the node A is increased by the bootstrap operation, the potential of the source that is the second electrode of the first transistor 101 is increased. As a result, the potential becomes higher than the first potential VDD. Then, the source of the first transistor 101 is switched to the first electrode side, that is, the first power supply line 31 side. Therefore, in the first transistor 101, a large bias voltage is applied between the gate and the source and between the gate and the drain during the period of FIG. It can be.

By providing the ninth transistor 109 to which the high power supply potential VDD is applied to the gate, the potential of the node A is increased by the bootstrap operation, but the potential of the second electrode of the first transistor 101 is increased. It can be prevented from occurring. That is, by providing the ninth transistor 109, the value of the negative bias voltage applied between the gate and the source of the first transistor 101 can be reduced. Therefore, with the circuit configuration in this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 101 can be reduced, so that deterioration of the first transistor 101 due to stress is suppressed. be able to.

Note that the place where the ninth transistor 109 is provided is connected between the second electrode of the first transistor 101 and the gate of the third transistor 103 through the first electrode and the second electrode. Any configuration may be used. Note that in the case of forming a shift register including a plurality of pulse output circuits in this embodiment, the ninth transistor 109 may be omitted in a signal line driver circuit having more stages than a scan line driver circuit.

Note that an oxide semiconductor may be used for the semiconductor layers of the first transistor 101 to the ninth transistor. By using an oxide semiconductor as a semiconductor layer of a transistor, an off current of a thin film transistor can be reduced, an on current and a field effect mobility can be increased, and a degree of deterioration can be reduced. A drive circuit that reduces malfunctions and guarantees a more accurate operation can be obtained. In addition, compared with a transistor using an oxide semiconductor and a transistor using amorphous silicon, the degree of deterioration of the transistor due to application of a high potential to the gate electrode is small. Therefore, even when the second potential VCC is the first potential VDD, a similar operation can be obtained and the number of wirings routed between the circuits can be reduced, so that the circuit can be reduced in size. Note that as the oxide semiconductor, for example, zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like can also be used. In the case where ZnO is used for the semiconductor layer, the gate insulating layer uses Y ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , or a laminate thereof, and the gate electrode layer, the source electrode layer, and the drain electrode layer include ITO, Au, Ti or the like can be used. In addition, In, Ga, or the like can be added to ZnO.

As the oxide semiconductor, a thin film represented by InMO ₃ (ZnO) _x (x> 0) can be used. Note that M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, M may be Ga, and may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements. For example, an In—Ga—Zn—O-based non-single-crystal film can be used as the oxide semiconductor layer.

Instead of an In—Ga—Zn—O-based non-single-crystal film as an oxide semiconductor (InMO ₃ (ZnO) _x (x> 0) film), InMO ₃ (ZnO) _x (x > 0) A film may be used. In addition to the above oxide semiconductors, In—Sn—Zn—O-based, In—Al—Zn—O-based, Sn—Ga—Zn—O-based, Al—Ga—Zn—O-based, Sn— Applying an Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor is used. Can do.

After that, in the second half of the third period 53, the first input terminal 21 of the first pulse output circuit _{10_1} becomes L level, and the potential of the node C decreases. In addition, when the second input terminal 22, the third input terminal 23, and the fifth input terminal 25 become H level in the second half of the third period 53, the potential of the node B is rapidly increased to VCC. Become. As a result, the second transistor 102 and the fourth transistor 104 are turned on, so that the potential of the node C can be sharply lowered.

Note that the timing at which the second start pulse (SP2) and the third start pulse (SP3) output the H (High) signal, that is, the timing at which the fifth input terminal 25 becomes H level is the second input. This overlaps with the timing at which the terminal 22 and the third input terminal 23 become H level. Therefore, the wiring for inputting the second start pulse (SP2) and the third start pulse (SP3) can be omitted.

In the first half of the fourth period 54, the fifth input terminal 25 of the first pulse output circuit _{10_1} holds the H level, so that the node B holds VCC. Accordingly, the second transistor 102 and the fourth transistor 104 are turned on, the third transistor 103 is turned off, and the potential of the node C, that is, the potential of the output terminal 26 becomes L level. (See FIG. 4A).

After that, in the second half of the fourth period 54, the fifth input terminal 25 of the first pulse output circuit _{10_1} is at an L level, and the sixth transistor 106 is turned off (see FIG. 4B). At this time, the node B changes from a state where the VCC level is maintained to a floating state. Accordingly, the second transistor 102 and the fourth transistor 104 are kept on (see FIG. 4C). However, as shown in FIG. 2, the potential of the node B drops from the VCC level due to the off-state current of the transistor and the like.

  After that, in a certain period of the fifth period 55 (when the second clock signal (CK2) and the third clock signal (CK3) are both at the H level), the seventh transistor 107 and the eighth transistor 108 are The node is turned on, and a VCC level signal is periodically supplied to the node B (see FIG. 4D).

  In this manner, by adopting a configuration in which an H level signal is periodically supplied to the node B during a period in which the potential of the output terminal 26 is held at an L level, malfunction of the pulse output circuit can be suppressed. Further, by periodically turning on or off the seventh transistor 108 and the eighth transistor 109, a shift in threshold voltage of the transistors can be reduced.

Further, in the fifth period 55, while the H-level signal is not supplied to the node B from the fifth power supply line 35, the off-state current of the fifth transistor 105 and the sixth transistor 106 causes the node B to Potential may drop. For this reason, a capacitor may be provided in advance in the node B so that the decrease in the potential of the node B is alleviated.

  In the shift register described in this embodiment, as illustrated in FIG. 5A, the pulse output from the mth pulse output circuit and the pulse output from the (m + 1) th pulse output circuit are half. The overlapping driving method (for 1/4 period) is used. This is compared with the driving method (see FIG. 5B) in which the pulse output from the mth pulse output circuit and the pulse output from the (m + 1) th pulse output circuit in the conventional shift register do not overlap. The time for charging the wiring can be approximately doubled. In this way, by using a driving method in which the pulse output from the mth pulse output circuit and the pulse output from the (m + 1) th pulse output circuit overlap by half (for ¼ period), a large load is applied. A pulse output circuit that can be applied and operates at a high frequency can be provided. In addition, the operating conditions of the pulse output circuit can be increased. Therefore, it is very effective to use the driving method shown in FIG. 5A for a thin film transistor using amorphous silicon having poor electrical characteristics.

  Note that the shift register and the pulse output circuit described in this embodiment can be combined with any structure of the shift register and the pulse output circuit described in other embodiments in this specification. The structure of this embodiment can also be applied to a semiconductor device. In this specification, a semiconductor device means a device that can function by utilizing semiconductor characteristics.

(Embodiment 2)
In this embodiment, different structures from the shift register and the pulse output circuit described in the above embodiments are described with reference to drawings.

The shift register described in this embodiment includes a first pulse output circuit _{10_1} to an nth pulse output circuit _{10_n} (n ≧ 2), and first signal lines 11 to 4 for outputting clock signals. It has a line 14 (see FIG. 6A). In addition, each of the first pulse output circuit _{10_1} to the nth pulse output circuit _{10_n} includes a first input terminal 21, a second input terminal 22, a third input terminal 23, and a fourth input terminal 24. , A fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 6B). Note that the second output terminal 27 is newly added to the pulse output circuit shown in the first embodiment.

  The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first signal line 11 to the fourth signal line 14. In the m-th pulse output circuit (m ≧ 2) of the shift register described in this embodiment, the fourth input terminal 24 is electrically connected to the first output terminal 26 of the (m−1) th pulse output circuit. The fifth input terminal 25 is electrically connected to the first output terminal 26 of the (m + 2) th pulse output circuit, and the first output terminal 26 is connected to the (m + 1) th pulse output circuit. The fourth input terminal 24 and the second output terminal 27 output a signal to OUT (m).

  In other words, the shift register described in this embodiment includes the first output terminal 26 and the second output terminal 27, and outputs an output terminal for outputting a signal to another pulse output circuit and a signal to the outside. The output terminal is provided separately.

Next, specific structures of the first pulse output circuit _{10_1} to the n-th pulse output circuit _{10_n} described in this embodiment will be described.

Each of the pulse output circuit _{10 _n} of the first pulse output circuit _{10 - 1} to the n-th has a first transistor 101 to the ninth transistor 109, the transistor 204 of the tenth transistor 201 to 13, the (See FIG. 6C). The pulse output circuit described in this embodiment has a structure in which a tenth transistor 201 to a thirteenth transistor 204 are added to the pulse output circuit described in Embodiment 1. In addition to the first input terminal 21 to the fifth input terminal 25, the first output terminal 26, the first power supply line 31 to the sixth power supply line 36 described in the first embodiment, Signals are supplied to the transistors from the output terminal 27 and the seventh power supply line 37 to the ninth power supply line 39.

  In the tenth transistor 201, the first electrode is electrically connected to the first input terminal 21, the second electrode is electrically connected to the second output terminal 27, and the gate electrode is the ninth transistor. 109 is electrically connected to the second electrode. In the eleventh transistor 202, the first electrode is electrically connected to the eighth power supply line 38, the second electrode is electrically connected to the second output terminal 27, and the gate electrode is the second transistor. The gate electrode of 102 and the gate electrode of the fourth transistor 104 are electrically connected. In the twelfth transistor 203, the first electrode is electrically connected to the ninth power supply line 39, the second electrode is electrically connected to the second output terminal 27, and the gate electrode is the seventh transistor. The gate electrode 107 is electrically connected. In the thirteenth transistor 204, the first electrode is electrically connected to the seventh power supply line 37, the second electrode is electrically connected to the first output terminal 26, and the gate electrode is the seventh transistor. The gate electrode 107 is electrically connected.

The seventh power supply line 37 to the ninth power supply line 39 can be configured to be supplied with the potential V2 (VSS) similarly to the second power supply line 32 to the fourth power supply line 34. .

The first output terminal 26 and the second output terminal 27 are provided so that the same signal is output, the tenth transistor 201 corresponds to the third transistor 103, and the fourth transistor 104 The eleventh transistor 202 has a corresponding configuration. That is, the tenth transistor 201 performs a bootstrap operation similarly to the third transistor 103. Note that the bootstrap operation of the tenth transistor 201 may be performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the tenth transistor 201. Note that a structure in which a capacitor is additionally provided may be employed.

The twelfth transistor 203 and the thirteenth transistor 204 are used to shorten the falling time of the potential of the scanning line. If the fall time of the scan line potential can be sufficiently shortened by the twelfth transistor 203 and the thirteenth transistor 204, the fall time of the scan line potential must be shortened by the fourth transistor 104 and the eleventh transistor 202. Therefore, the potential of the fifth power supply line 35 can be set lower than the power supply of the first power supply line 31. This makes it possible to reduce a shift in threshold voltage of the fourth transistor 104, the eleventh transistor 202, and the second transistor 102.

  Note that the shift register and the pulse output circuit described in this embodiment can be combined with any structure of the shift register and the pulse output circuit described in other embodiments in this specification. The structure of this embodiment can also be applied to a semiconductor device.

(Embodiment 3)
In this embodiment, structures that are different from those of the shift register and the pulse output circuit described in the above embodiments are described.

  In the structures described in Embodiments 1 and 2 above, an example in which all circuits are formed using N-channel thin film transistors has been described. However, only P-channel thin film transistors are used in that unipolar thin film transistors are used. A similar configuration may be used. Although not particularly illustrated, in the diagram illustrated in FIG. 1C or FIG. 6C, the connection of the transistors is the same, and the potential of the power supply line is described in Embodiment Mode 1 and Embodiment Mode 2. And reverse. Further, a configuration may be adopted in which the H level and the L level of the input signal are all reversed. Note that the structure of this embodiment can also be applied to a semiconductor device.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 4)
A structure in which the shift register described in any of the above embodiments is provided in a display device is described with reference to drawings.

  In FIG. 7A, a pixel portion 1102 in which a plurality of pixels 1101 are arranged in a matrix is provided over a substrate 1107, and a signal line driver circuit 1103 and a first scan line driver are provided around the pixel portion 1102. A circuit 1104 and a second scan line driver circuit 1105 are included. These drive circuits are supplied with signals from the outside via the FPC 1106.

  FIG. 7B illustrates a structure of the first scan line driver circuit 1104 and the second scan line driver circuit 1105. The scan line driver circuits 1104 and 1105 each include a shift register 1114 and a buffer 1115. FIG. 7C illustrates the structure of the signal line driver circuit 1103. The signal line driver circuit 1103 includes a shift register 1111, a first latch circuit 1112, a second latch circuit 1113, and a buffer 1117.

  The circuit operating as a shift register in this embodiment can be applied to the circuits of the shift register 1111 and the shift register 1114. By applying the circuit that operates as the shift register described in the above embodiment mode, even when a circuit that operates as the shift register is provided using a thin film transistor using amorphous silicon, the circuit can be operated at a high frequency. A circuit that operates as the shift register can be provided using a thin film transistor including an oxide semiconductor. A thin film transistor using an oxide semiconductor can reduce off-state current, increase on-state current and field-effect mobility, and reduce the degree of deterioration compared to amorphous silicon. Thus, a driving circuit that guarantees a more accurate operation can be obtained.

  Note that the configurations of the scan line driver circuit and the signal line driver circuit are not limited to those shown in FIG. 7, and may include, for example, a sampling circuit or a level shifter. In addition to the driving circuit, a circuit such as a CPU or a controller may be integrally formed on the substrate 1107. Then, the number of external circuits (IC) to be connected is reduced, and the weight and thickness can be further increased.

  Note that the display device described in this embodiment can be implemented in combination with the structure of the shift register, the pulse output circuit, or the display device described in other embodiments in this specification.

(Embodiment 5)
In this embodiment, a structure of a display panel used for the display device described in Embodiment 4 is described with reference to drawings.

  First, a display panel applicable to the display device will be described with reference to FIG. 8A is a top view illustrating the display panel, and FIG. 8B is a cross-sectional view taken along line A-A ′ in FIG. 8A. A signal line driver circuit 3601, a pixel portion 3602, a second scan line driver circuit 3603, and a first scan line driver circuit 3606 indicated by dotted lines are included. Further, a sealing substrate 3604 and a sealing material 3605 are provided, and an inner side surrounded by the sealing material 3605 is a space 3607.

  Note that the wiring 3608 is a wiring for transmitting a signal input to the second scan line driver circuit 3603, the first scan line driver circuit 3606, and the signal line driver circuit 3601, and is an FPC (flexible flexible cable) serving as an external input terminal. Print circuit) 3609 receives a video signal, a clock signal, a start signal, and the like. An IC chip (a semiconductor chip in which a memory circuit, a buffer circuit, or the like is formed) 3618 and an IC chip 3619 are mounted on a joint portion between the FPC 3609 and the display panel by a COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The display device in this specification includes not only a display panel body but also a state in which an FPC or a PWB is attached thereto. In addition, it is assumed that an IC chip or the like is mounted.

  Next, a cross-sectional structure is described with reference to FIG. A pixel portion 3602 and its peripheral driver circuits (a second scan line driver circuit 3603, a first scan line driver circuit 3606, and a signal line driver circuit 3601) are formed over the substrate 3610. Here, a signal line A driver circuit 3601 and a pixel portion 3602 are shown.

  Note that the signal line driver circuit 3601 forms a CMOS circuit using an N-channel TFT 3620 and a P-channel TFT 3621. In this embodiment mode, a display panel in which a peripheral drive circuit is integrally formed on a substrate is shown; however, it is not always necessary, and all or a part of the peripheral drive circuit is formed on an IC chip or the like and mounted by COG or the like. You may do it.

  The pixel portion 3602 includes a plurality of circuits that form a pixel including a switching TFT 3611 and a driving TFT 3612. Note that the source electrode of the driving TFT 3612 is electrically connected to the first electrode 3613. An insulator 3614 is formed so as to cover an end portion of the first electrode 3613. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 3614. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 3614, it is preferable that only the upper end portion of the insulator 3614 has a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 3614, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  Over the first electrode 3613, a layer 3616 containing an organic compound and a second electrode 3617 are formed. Here, as a material used for the first electrode 3613 which functions as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

  The layer 3616 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 3616 containing an organic compound, a Group 4 metal complex of the periodic table of elements is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer. However, in this embodiment, an inorganic compound is used for part of a film made of an organic compound. Will also be included. Further, a known triplet material can be used.

Further, as a material used for the second electrode (cathode) 3617 formed over the layer 3616 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof MgAg, MgIn, AlLi, or the like) , CaF ₂ , or calcium nitride) may be used. Note that in the case where light generated in the layer 3616 containing an organic compound transmits the second electrode 3617, the second electrode (cathode) 3617 includes a thin metal film and a transparent conductive film (ITO ( A stack of indium tin oxide), an indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, the sealing substrate 3604 is bonded to the substrate 3610 with the sealant 3605, whereby the display element 3622 is provided in the space 3607 surrounded by the substrate 3610, the seal substrate 3604, and the sealant 3605. Note that the space 3607 includes a structure filled with a sealant 3605 in addition to a case where the space 3607 is filled with an inert gas (such as nitrogen or argon).

  Note that an epoxy-based resin is preferably used for the sealant 3605. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), polyester, acrylic, or the like can be used as a material used for the sealing substrate 3604.

  A display panel can be obtained as described above.

  As shown in FIG. 8, the signal line driver circuit 3601, the pixel portion 3602, the second scan line driver circuit 3603, and the first scan line driver circuit 3606 are integrally formed, whereby the cost of the display device can be reduced.

  Note that as a structure of the display panel, a signal line driver circuit 3601, a pixel portion 3602, a second scan line driver circuit 3603, and a first scan line driver circuit 3606 are integrally formed as shown in FIG. The configuration is not limited, and the signal line driver circuit 4201 shown in FIG. 9A corresponding to the signal line driver circuit 3601 may be formed over the IC chip and mounted on the display panel with COG or the like. Note that the substrate 4200, the pixel portion 4202, the second scan line driver circuit 4203, the first scan line driver circuit 4204, the FPC 4205, the IC chip 4206, the IC chip 4207, the sealing substrate 4208, and the sealing material in FIG. Reference numeral 4209 denotes a substrate 3610, a pixel portion 3602, a second scan line driver circuit 3603, a first scan line driver circuit 3606, an FPC 3609, an IC chip 3618, an IC chip 3619, a sealing substrate 3604, and a sealing material in FIG. It corresponds to 3605.

  That is, only the signal line driver circuit that requires high-speed operation among the driver circuits is formed on the IC chip using a CMOS or the like to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

  The first scan line driver circuit 4203 and the second scan line driver circuit 4204 provided with the shift register described in the above embodiment mode are formed integrally with the pixel portion 4202, so that cost can be reduced.

  Thus, the cost of a high-definition display device can be reduced. Further, by mounting an IC chip on which a functional circuit (memory or buffer) is formed at a connection portion between the FPC 4205 and the substrate 4200, the substrate area can be effectively used.

  Further, the signal line driver circuit 4211 in FIG. 9B corresponding to the signal line driver circuit 3601, the second scan line driver circuit 3603, and the first scan line driver circuit 3606 in FIG. The line driver circuit 4214 and the first scan line driver circuit 4213 may be formed over an IC chip and mounted on the display panel with COG or the like. In this case, a high-definition display device can have lower power consumption. Therefore, in order to obtain a display device with lower power consumption, it is preferable to use polysilicon for a semiconductor layer of a transistor used in the pixel portion. Note that the substrate 4210, the pixel portion 4212, the FPC 4215, the IC chip 4216, the IC chip 4217, the sealing substrate 4218, and the sealant 4219 in FIG. 9B are the substrate 3610, the pixel portion 3602, the FPC 3609, and the IC in FIG. It corresponds to a chip 3618, an IC chip 3619, a sealing substrate 3604, and a sealing material 3605.

  In addition, cost can be reduced by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 4212. Further, a large display panel can be manufactured. Alternatively, a transistor in a pixel portion and a transistor included in a shift register can be used as a thin film transistor including an oxide semiconductor. A thin film transistor using an oxide semiconductor can reduce off-state current, increase on-state current and field-effect mobility, and reduce the degree of deterioration compared to amorphous silicon. Thus, a driving circuit that guarantees a more accurate operation can be obtained.

  Further, examples of display elements applicable to the display element 3622 are shown in FIGS. That is, a structure of a display element that can be applied to the pixel described in the above embodiment mode will be described with reference to FIGS.

  In the display element in FIG. 13A, an anode 4402 over a substrate 4401, a hole injection layer 4403 made of a hole injection material, a hole transport layer 4404 made of a hole transport material thereon, a light emitting layer 4405, an electron In this element structure, an electron transport layer 4406 made of a transport material, an electron injection layer 4407 made of an electron injection material, and a cathode 4408 are stacked. Here, the light emitting layer 4405 may be formed of only one kind of light emitting material, but may be formed of two or more kinds of materials. Further, the structure of the element is not limited to this structure.

  In addition to the stacked structure in which the functional layers shown in FIGS. 13A and 13B are stacked, an element using a polymer compound and a triplet light emitting material that emits light from a triplet excited state are used in the light emitting layer. There are many variations, such as high-efficiency elements. The present invention can also be applied to a white display element obtained by controlling the carrier recombination region by the hole blocking layer and dividing the light emitting region into two regions.

  In the element manufacturing method illustrated in FIG. 13A, first, a hole injecting material, a hole transporting material, and a light emitting material are sequentially deposited on a substrate 4401 having an anode 4402 (ITO). Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 4408 is formed by vapor deposition.

  Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as long as they are organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

  The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as —N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As an electron transport material, a metal complex is often used, and Alq, BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”), bis (10-hydroxybenzo [h] -quinolinato) There are metal complexes having a quinoline skeleton or a benzoquinoline skeleton such as beryllium (hereinafter referred to as “BeBq”). Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like Oxadiazole derivatives of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (hereinafter “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

  The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the light emitting material, various fluorescent dyes are effective in addition to metal complexes such as Alq, Almq, BeBq, BAlq, Zn (BOX) ₂ and Zn (BTZ) ₂ . As fluorescent dyes, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

  A highly reliable display element can be manufactured by combining the materials having the functions described above.

  In addition, if the polarity of the driving transistor having the pixel structure described in the above embodiment is changed to be an N-channel transistor, the potential of the counter electrode of the display element and the potential set to the power supply line are reversed. A display element in which layers are formed in the reverse order of FIG. 13A can be used. That is, as shown in FIG. 13B, a cathode 4408 over an substrate 4401, an electron injection layer 4407 made of an electron injection material, an electron transport layer 4406 made of an electron transport material, a light emitting layer 4405, and a hole transport. In this element structure, a hole transport layer 4404 made of a material, a hole injection layer 4403 made of a hole injection material, and an anode 4402 are laminated.

  Further, in order to extract light emission from the display element, at least one of the anode and the cathode only needs to be transparent. Then, a TFT and a display element are formed on the substrate, and a top emission that extracts light emission from a surface opposite to the substrate, a bottom emission that extracts light emission from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. There is a display element having a dual emission structure in which light emission is extracted from the pixel, and the pixel structure described in the above embodiment can be applied to a display element having any emission structure.

  A display element having a top emission structure will be described with reference to FIG.

  A driving TFT 4501 is formed over a substrate 4500 with a base film 4505 interposed therebetween, a first electrode 4502 is formed in contact with a source electrode of the driving TFT 4501, and a layer 4503 containing an organic compound and a second electrode 4504 are formed thereover. Is formed.

  The first electrode 4502 is an anode of the display element. The second electrode 4504 is a cathode of the display element. That is, a display element is a portion where the layer 4503 containing an organic compound is sandwiched between the first electrode 4502 and the second electrode 4504.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the display element can be extracted from the top surface as indicated by an arrow in FIG. That is, when applied to the display panel in FIG. 8, light is emitted to the sealing substrate 3604 side. Therefore, when a display element having a top emission structure is used for a display device, the sealing substrate 3604 is a light-transmitting substrate.

  In the case where an optical film is provided, an optical film may be provided over the sealing substrate 3604.

  Next, a display element having a bottom emission structure will be described with reference to FIG. Except for the emission structure, the display element has the same structure as that in FIG.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A metal film can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

  In this manner, light from the display element can be extracted to the lower surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 8, light is emitted to the substrate 3610 side. Therefore, when a display element having a bottom emission structure is used for a display device, the substrate 3610 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 3610 may be provided with an optical film.

  Next, a display element having a dual emission structure will be described with reference to FIG. Except for the emission structure, the display element has the same structure as that in FIG.

  Here, as a material used for the first electrode 4502 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

A material used for the second electrode 4504 functioning as a cathode is a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride). A stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used. Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

  In this manner, light from the display element can be extracted on both sides as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 8, light is emitted to the substrate 3610 side and the sealing substrate 3604 side. Therefore, when a display element having a dual emission structure is used for a display device, both the substrate 3610 and the sealing substrate 3604 are light-transmitting substrates.

  In the case where an optical film is provided, the optical film may be provided on both the substrate 3610 and the sealing substrate 3604.

  In addition, the structure of the pulse output circuit described in the above embodiment can be applied to a display device that realizes full-color display using a white display element and a color filter.

  For example, as shown in FIG. 11, a base film 4602 is formed on a substrate 4600, a driving TFT 4601 is formed thereon, a first electrode 4603 is formed in contact with the source electrode of the driving TFT 4601, A layer 4604 containing an organic compound and a second electrode 4605 may be formed.

  The first electrode 4603 is an anode of the display element. The second electrode 4605 is a cathode of the display element. That is, a display element is a portion where the layer 4604 containing an organic compound is sandwiched between the first electrode 4603 and the second electrode 4605. In the configuration of FIG. 11, white light is emitted. A red color filter 4606R, a green color filter 4606G, and a blue color filter 4606B are provided above the display element, so that full color display can be performed. Further, a black matrix (also referred to as BM) 4607 for separating these color filters is provided.

  The structures of the display elements described above can be used in combination, and can be used as appropriate for the display device driven by the pulse output circuit and the shift register described in the above embodiments. In addition, the configuration of the display panel and the display element described above are examples, and other configurations can be applied as a matter of course.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 6)
In this embodiment, examples of electronic devices are described. Specifically, it can be applied to driving of a display portion of an electronic device. Such electronic devices include cameras such as video cameras and digital cameras, goggle-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, personal digital assistants (mobile computers, mobile phones, Portable game machine or electronic book), image reproducing apparatus provided with a recording medium (specifically, an apparatus equipped with a light emitting device capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image) Etc.

  FIG. 12A illustrates a light-emitting device, which includes a housing 6001, a support base 6002, a display portion 6003, a speaker portion 6004, a video input terminal 6005, and the like. A display device including the pulse output circuit described in the above embodiment can be used for the display portion 6003. The light emitting devices include all information display light emitting devices such as for personal computers, for receiving television broadcasts, and for displaying advertisements. An electronic device including a display device that operates with a driver circuit in which malfunctions are reduced by driving the display portion 6003 with the use of the shift register described in the above embodiment can be provided.

  FIG. 12B shows a camera, which includes a main body 6101, a display portion 6102, an image receiving portion 6103, operation keys 6104, an external connection port 6105, a shutter button 6106, and the like. By driving the display portion 6102 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit with reduced malfunctions can be provided.

  FIG. 12C illustrates a computer, which includes a main body 6201, a housing 6202, a display portion 6203, a keyboard 6204, an external connection port 6205, a pointing device 6206, and the like. By driving the display portion 6203 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit in which malfunctions are reduced can be provided.

  FIG. 12D illustrates a mobile computer, which includes a main body 6301, a display portion 6302, a switch 6303, operation keys 6304, an infrared port 6305, and the like. By driving the display portion 6302 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit in which malfunctions are reduced can be provided.

  FIG. 12E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A6403, a display portion B6404, and a recording medium (DVD or the like). A reading unit 6405, an operation key 6406, a speaker unit 6407, and the like are included. The display portion A 6403 can mainly display image information, and the display portion B 6404 can mainly display character information. By driving the display portion A 6403 and the display portion B 6404 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit with reduced malfunction can be provided.

  FIG. 12F illustrates a goggle type display, which includes a main body 6501, a display portion 6502, and an arm portion 6503. By driving the display portion 6502 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit in which malfunctions are reduced can be provided.

  FIG. 12G illustrates a video camera, which includes a main body 6601, a display portion 6602, a housing 6603, an external connection port 6604, a remote control receiving portion 6605, an image receiving portion 6606, a battery 6607, an audio input portion 6608, operation keys 6609, and an eyepiece. Part 6610 and the like. By driving the display portion 6602 using the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit with reduced malfunctions can be provided.

  FIG. 12H illustrates a mobile phone, which includes a main body 6701, a housing 6702, a display portion 6703, an audio input portion 6704, an audio output portion 6705, operation keys 6706, an external connection port 6707, an antenna 6708, and the like. By driving the display portion 6703 with the use of the shift register described in the above embodiment, an electronic device including a display device that operates with a driver circuit with reduced malfunctions can be provided.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

A scan line driver circuit (hereinafter referred to as a gate driver) including the shift register in FIG. 1A described in the above embodiment mode and a signal line driver circuit (referred to as a source driver) are formed over a substrate provided with a display portion. FIG. 14 shows a photograph of a display panel employing an organic EL element as a display element. In the display panel shown in FIG. 14, a source driver is arranged in the short side direction, a gate driver is arranged in the long side direction, and an FPC terminal portion is provided in the short side direction in which the source driver is arranged on a rectangular substrate. It is configured. In addition, an In—Ga—Zn—O-based non-single-crystal film that is an oxide semiconductor is used as a semiconductor layer of a thin film transistor disposed in each pixel, the gate driver, and the source driver. Note that the color display method of the display panel shown in FIG. 14 is configured such that a color filter is provided on a thin film transistor and white light is emitted from an organic EL element on the color filter, thereby realizing color display.

Specific specifications of the display panel shown in FIG. 14 are shown in Table 1.

In Table 1, 2Tr1C is an abbreviation for a structure including two transistors and one capacitor in one pixel.

In addition, signal waveforms observed in a source driver including an actually manufactured shift register will be described with reference to FIGS. Note that FIG. 15A is a timing chart of the driver circuit described in the above embodiment, and FIG. 15B shows a signal waveform actually observed. 15A and 15B, SSP is the first start pulse (S-SP) of the source driver, SCK1 is the first clock signal of the source driver, and SOUT1 is the first-stage pulse output of the source driver. An output signal of the circuit, SOUT (dum), is an output signal of the final stage (dummy stage) of the pulse output circuit of the source driver.

It can be seen that the actually observed signal waveforms are obtained as shown in the timing charts of FIGS.

10 pulse output circuit 11 signal line 12 signal line 13 signal line 14 signal line 21 input terminal 22 input terminal 23 input terminal 24 input terminal 25 input terminal 26 output terminal 27 output terminal 31 power supply line 32 power supply line 33 power supply line 34 power supply line 35 Power supply line 36 Power supply line 37 Power supply line 38 Power supply line 39 Power supply line 51 Period 52 Period 53 Period 54 Period 55 Period 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 201 Transistor 202 Transistor 203 Transistor 204 Transistor 1101 Pixel 1102 Pixel portion 1103 Signal line driver circuit 1104 Scan line driver circuit 1105 Scan line driver circuit 1106 FPC
1107 substrate 1111 shift register 1112 latch circuit 1113 latch circuit 1114 shift register 1115 buffer 1117 buffer 3601 signal line driver circuit 3602 pixel portion 3603 scanning line driver circuit 3604 sealing substrate 3605 sealant 3606 scan line driver circuit 3607 space 3608 wiring 3609 FPC
3610 Substrate 3611 Switching TFT
3612 Driving TFT
3613 Electrode 3614 Insulator 3616 Layer 3617 Electrode 3618 IC chip 3619 IC chip 3620 N-channel TFT
3621 P-channel TFT
3622 Display element 4200 Substrate 4201 Signal line driver circuit 4202 Pixel portion 4203 Scan line driver circuit 4204 Scan line driver circuit 4205 FPC
4206 IC chip 4207 IC chip 4208 Sealing substrate 4209 Sealing material 4210 Substrate 4211 Signal line driver circuit 4212 Pixel portion 4213 Scan line driver circuit 4214 Scan line driver circuit 4215 FPC
4216 IC chip 4217 IC chip 4218 Sealing substrate 4219 Sealing material 4401 Substrate 4402 Anode 4403 Hole injection layer 4404 Hole transport layer 4405 Light emitting layer 4406 Electron transport layer 4407 Electron injection layer 4408 Cathode 4500 Substrate 4501 Driving TFT
4502 Electrode 4503 Layer 4504 Electrode 4505 Base film 4600 Substrate 4601 Driving TFT
4602 Base film 4603 Electrode 4604 Layer 4605 Electrode 6001 Case 6002 Support base 6003 Display unit 6004 Speaker unit 6005 Video input terminal 6101 Main unit 6102 Display unit 6103 Image receiving unit 6104 Operation key 6105 External connection port 6106 Shutter button 6201 Main unit 6202 Case 6203 Display Unit 6204 Keyboard 6205 External connection port 6206 Pointing device 6301 Main body 6302 Display unit 6303 Switch 6304 Operation key 6305 Infrared port 6401 Main unit 6402 Case 6403 Display unit A
6404 Display portion B
6405 section 6406 operation key 6407 speaker section 6501 main body 6502 display section 6503 arm section 6601 main body 6602 display section 6603 casing 6604 external connection port 6605 remote control receiving section 6606 image receiving section 6607 battery 6608 voice input section 6609 operation key 6610 eyepiece section 6701 main body 6702 Housing 6703 Display unit 6704 Audio input unit 6705 Audio output unit 6706 Operation key 6707 External connection port 6708 Antenna 4606B Color filter 4606G Color filter 4606R Color filter

Claims (2)

Having first to fifth transistors;
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor;
A gate of the fourth transistor is electrically connected to a gate of the second transistor;
One of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor;
The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
The first signal is input to the gate of the third transistor,
A semiconductor device, wherein a second signal is output from one of a source and a drain of the first transistor. Having first to seventh transistors;
One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor;
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
One of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the seventh transistor;
A gate of the fourth transistor is electrically connected to a gate of the second transistor;
A gate of the fourth transistor is electrically connected to a gate of the seventh transistor;
One of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor;
One of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor;
The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the third transistor;
The other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the fourth transistor;
The first signal is input to the gate of the third transistor,
A second signal is output from one of the source and the drain of the first transistor,
A semiconductor device, wherein a third signal is output from one of a source and a drain of the sixth transistor.