JP2011030171A5 - - Google Patents
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- JP2011030171A5 JP2011030171A5 JP2009206918A JP2009206918A JP2011030171A5 JP 2011030171 A5 JP2011030171 A5 JP 2011030171A5 JP 2009206918 A JP2009206918 A JP 2009206918A JP 2009206918 A JP2009206918 A JP 2009206918A JP 2011030171 A5 JP2011030171 A5 JP 2011030171A5
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Claims (7)
第１の電源線乃至第６の電源線と電気的に接続され、
前記第１のトランジスタは、第１の電極が前記第１の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第２のトランジスタは、第１の電極が前記第２の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４のトランジスタのゲート電極に電気的に接続され、
前記第３のトランジスタは、第１の電極が前記第１の入力端子に電気的に接続され、第２の電極が前記出力端子に電気的に接続され、
前記第４のトランジスタは、第１の電極が前記第３の電源線に電気的に接続され、第２の電極が前記出力端子に電気的に接続され、
前記第５のトランジスタは、第１の電極が前記第４の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第６のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第５の入力端子に電気的に接続され、
前記第７のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第８のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第３の入力端子に電気的に接続され、
前記第８のトランジスタは、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第２の入力端子に電気的に接続され、
前記第９のトランジスタは、ゲート電極が前記第６の入力端子に電気的に接続されていることを特徴とするパルス出力回路。 A first transistor to a ninth transistor; a first input terminal to a fifth input terminal; and an output terminal;
Electrically connected to the first power supply line to the sixth power supply line;
The first transistor has a first electrode electrically connected to the first power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the fourth input terminal;
The second transistor has a first electrode electrically connected to the second power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the gate electrode of the fourth transistor;
The third transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the output terminal,
The fourth transistor has a first electrode electrically connected to the third power supply line, a second electrode electrically connected to the output terminal,
The fifth transistor has a first electrode electrically connected to the fourth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fourth input terminal,
The sixth transistor has a first electrode electrically connected to the fifth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fifth input terminal,
The seventh transistor has a first electrode electrically connected to the fifth power supply line, a second electrode electrically connected to the first electrode of the eighth transistor, and a gate electrode Electrically connected to the third input terminal;
In the eighth transistor, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the second input terminal. And
The pulse output circuit according to claim 9, wherein the ninth transistor has a gate electrode electrically connected to the sixth input terminal.
第１の電源線乃至第６の電源線と電気的に接続され、
前記第１のトランジスタは、第１の電極が前記第１の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第２のトランジスタは、第１の電極が前記第２の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４のトランジスタのゲート電極に電気的に接続され、
前記第３のトランジスタは、第１の電極が前記第１の入力端子に電気的に接続され、第２の電極が前記出力端子に電気的に接続され、
前記第４のトランジスタは、第１の電極が前記第３の電源線に電気的に接続され、第２の電極が前記出力端子に電気的に接続され、
前記第５のトランジスタは、第１の電極が前記第４の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第６のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第５の入力端子に電気的に接続され、
前記第７のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第８のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第３の入力端子に電気的に接続され、
前記第８のトランジスタは、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第２の入力端子に電気的に接続され、
前記第９のトランジスタは、ゲート電極が前記第６の入力端子に電気的に接続されており、
前記第１のトランジスタ乃至前記第９のトランジスタは、酸化物半導体を用いて形成されていることを特徴とするパルス出力回路。 A first transistor to a ninth transistor; a first input terminal to a fifth input terminal; and an output terminal;
Electrically connected to the first power supply line to the sixth power supply line;
The first transistor has a first electrode electrically connected to the first power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the fourth input terminal;
The second transistor has a first electrode electrically connected to the second power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the gate electrode of the fourth transistor;
The third transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the output terminal,
The fourth transistor has a first electrode electrically connected to the third power supply line, a second electrode electrically connected to the output terminal,
The fifth transistor has a first electrode electrically connected to the fourth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fourth input terminal,
The sixth transistor has a first electrode electrically connected to the fifth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fifth input terminal,
The seventh transistor has a first electrode electrically connected to the fifth power supply line, a second electrode electrically connected to the first electrode of the eighth transistor, and a gate electrode Electrically connected to the third input terminal;
In the eighth transistor, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the second input terminal. And
A gate electrode of the ninth transistor is electrically connected to the sixth input terminal;
The pulse output circuit, wherein the first to ninth transistors are formed using an oxide semiconductor.
前記第１の電源線の電位は、前記第２の電源線、前記第３の電源線、前記第４の電源線、前記第５の電源線、及び前記第６の電源線の電位より高いことを特徴とするパルス出力回路。 In claim 1 or 2 ,
The potential of the first power line is higher than the potentials of the second power line, the third power line, the fourth power line, the fifth power line, and the sixth power line. A pulse output circuit characterized by.
前記第５の電源線の電位及び前記第６の電源線の電位は、前記第１の電源線の電位より低いことを特徴とするパルス出力回路。 In claim 3 ,
The pulse output circuit, wherein a potential of the fifth power supply line and a potential of the sixth power supply line are lower than a potential of the first power supply line.
第１の電源線乃至第９の電源線と電気的に接続され、
前記第１のトランジスタは、第１の電極が前記第１の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第２のトランジスタは、第１の電極が前記第２の電源線に電気的に接続され、第２の電極が前記第９のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第４のトランジスタのゲート電極に電気的に接続され、
前記第３のトランジスタは、第１の電極が前記第１の入力端子に電気的に接続され、第２の電極が前記第１の出力端子に電気的に接続され、
前記第４のトランジスタは、第１の電極が前記第３の電源線に電気的に接続され、第２の電極が前記第１の出力端子に電気的に接続され、
前記第５のトランジスタは、第１の電極が前記第４の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第４の入力端子に電気的に接続され、
前記第６のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第５の入力端子に電気的に接続され、
前記第７のトランジスタは、第１の電極が前記第５の電源線に電気的に接続され、第２の電極が前記第８のトランジスタの第１の電極に電気的に接続され、ゲート電極が前記第３の入力端子に電気的に接続され、
前記第８のトランジスタは、第２の電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、ゲート電極が前記第２の入力端子に電気的に接続され、
前記第９のトランジスタは、ゲート電極が前記第６の電源線に電気的に接続され、
前記第１０のトランジスタは、第１の電極が前記第１の入力端子に電気的に接続され、第２の電極が前記第２の出力端子に電気的に接続され、ゲート電極が前記第３のトランジスタのゲート電極に電気的に接続され、
前記第１１のトランジスタは、第１の電極が前記第８の電源線に電気的に接続され、第２の電極が前記第２の出力端子に電気的に接続され、ゲート電極が前記第２のトランジスタのゲート電極及び前記第４のトランジスタのゲート電極に電気的に接続され、
前記第１２のトランジスタは、第１の電極が前記第９の電源線に電気的に接続され、第２の電極が前記第２の出力端子に電気的に接続され、ゲート電極が前記第７のトランジスタのゲート電極に電気的に接続され、
前記第１３のトランジスタは、第１の電極が前記第７の電源線に電気的に接続され、第２の電極が前記第１の出力端子に電気的に接続され、ゲート電極が前記第７のトランジスタのゲート電極に電気的に接続されていることを特徴とするパルス出力回路。 A first transistor to a thirteenth transistor, a first input terminal to a fifth input terminal, and a first output terminal to a second output terminal;
Electrically connected to the first power supply line to the ninth power supply line;
The first transistor has a first electrode electrically connected to the first power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the fourth input terminal;
The second transistor has a first electrode electrically connected to the second power supply line, a second electrode electrically connected to the first electrode of the ninth transistor, and a gate electrode Electrically connected to the gate electrode of the fourth transistor;
The third transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the first output terminal,
The fourth transistor has a first electrode electrically connected to the third power supply line, a second electrode electrically connected to the first output terminal,
The fifth transistor has a first electrode electrically connected to the fourth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fourth input terminal,
The sixth transistor has a first electrode electrically connected to the fifth power supply line, and a second electrode electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor. And the gate electrode is electrically connected to the fifth input terminal,
The seventh transistor has a first electrode electrically connected to the fifth power supply line, a second electrode electrically connected to the first electrode of the eighth transistor, and a gate electrode Electrically connected to the third input terminal;
In the eighth transistor, the second electrode is electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor, and the gate electrode is electrically connected to the second input terminal. And
The ninth transistor has a gate electrode electrically connected to the sixth power supply line,
The tenth transistor has a first electrode electrically connected to the first input terminal, a second electrode electrically connected to the second output terminal, and a gate electrode connected to the third input terminal. Electrically connected to the gate electrode of the transistor,
The eleventh transistor has a first electrode electrically connected to the eighth power supply line, a second electrode electrically connected to the second output terminal, and a gate electrode connected to the second power terminal. Electrically connected to the gate electrode of the transistor and the gate electrode of the fourth transistor;
The twelfth transistor has a first electrode electrically connected to the ninth power supply line, a second electrode electrically connected to the second output terminal, and a gate electrode connected to the seventh power supply line. Electrically connected to the gate electrode of the transistor,
The thirteenth transistor has a first electrode electrically connected to the seventh power supply line, a second electrode electrically connected to the first output terminal, and a gate electrode connected to the seventh power supply line. A pulse output circuit which is electrically connected to a gate electrode of a transistor.
前記パルス出力回路は、第（ｍ−１）のパルス出力回路、第ｍのパルス出力回路、第（ｍ＋１）のパルス出力回路、及び第（ｍ＋２）のパルス出力回路（ｍ≧２）を少なくとも含み、
クロック信号を出力する第１の信号線乃至第４の信号線を有し、
前記第ｍのパルス出力回路において、
前記第１の入力端子乃至前記第３の入力端子は、前記第１の信号線乃至第４の信号線のうち３本の異なった信号線と電気的に接続され、
前記第４の入力端子は、前記第（ｍ−１）のパルス出力回路の出力端子と電気的に接続され、
前記第５の入力端子は、前記第（ｍ＋２）のパルス出力回路の出力端子と電気的に接続され、
前記出力端子は、前記第（ｍ＋１）のパルス出力回路の第４の入力端子と電気的に接続されていることを特徴とするシフトレジスタ。 The pulse output circuit according to any one of claims 1 to 5,
The pulse output circuit includes at least a (m−1) th pulse output circuit, an mth pulse output circuit, an (m + 1) th pulse output circuit, and an (m + 2) th pulse output circuit (m ≧ 2). ,
A first signal line to a fourth signal line for outputting a clock signal;
In the mth pulse output circuit,
The first input terminal to the third input terminal are electrically connected to three different signal lines among the first signal line to the fourth signal line,
The fourth input terminal is electrically connected to an output terminal of the (m−1) th pulse output circuit,
The fifth input terminal is electrically connected to an output terminal of the (m + 2) th pulse output circuit;
The shift register, wherein the output terminal is electrically connected to a fourth input terminal of the (m + 1) th pulse output circuit.
前記第１の信号線乃至第４の信号線の各々は、順に１／４周期遅延したクロック信号を出力することを特徴とするシフトレジスタ。
In claim 6,
Each of the first signal line to the fourth signal line sequentially outputs a clock signal delayed by a quarter cycle.
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| JP2011030171A5 true JP2011030171A5 (en) | 2012-10-18 |
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| JP2014224212A Active JP6028009B2 (en) | 2009-06-30 | 2014-11-04 | Semiconductor device and display device |
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| TWI511116B (en) | 2006-10-17 | 2015-12-01 | Semiconductor Energy Lab | Pulse output circuit, shift register, and display device |
| KR101828960B1 (en) | 2010-03-02 | 2018-02-13 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Pulse signal output circuit and shift register |
| US8854867B2 (en) * | 2011-04-13 | 2014-10-07 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and driving method of the memory device |
| KR101940570B1 (en) | 2011-05-13 | 2019-01-21 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | El display device and electronic device |
| US9171842B2 (en) | 2012-07-30 | 2015-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Sequential circuit and semiconductor device |
| US8952723B2 (en) * | 2013-02-13 | 2015-02-10 | Semiconductor Energy Laboratory Co., Ltd. | Programmable logic device and semiconductor device |
| JP6097653B2 (en) * | 2013-08-05 | 2017-03-15 | 株式会社ジャパンディスプレイ | Thin film transistor circuit and display device using the same |
| JP6618779B2 (en) * | 2014-11-28 | 2019-12-11 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US10330993B2 (en) * | 2016-12-23 | 2019-06-25 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| JPWO2022185143A1 (en) * | 2021-03-05 | 2022-09-09 | ||
| CN115715411A (en) * | 2021-05-31 | 2023-02-24 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
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| JP2001273785A (en) * | 2000-03-29 | 2001-10-05 | Casio Comput Co Ltd | Shift register and electronic device |
| JP4425547B2 (en) * | 2003-01-17 | 2010-03-03 | 株式会社半導体エネルギー研究所 | Pulse output circuit, shift register, and electronic device |
| JP4560502B2 (en) * | 2005-09-06 | 2010-10-13 | キヤノン株式会社 | Field effect transistor |
| JP5525685B2 (en) * | 2006-10-17 | 2014-06-18 | 株式会社半導体エネルギー研究所 | Semiconductor device and electronic equipment |
| TWI511116B (en) * | 2006-10-17 | 2015-12-01 | Semiconductor Energy Lab | Pulse output circuit, shift register, and display device |
| JP5197058B2 (en) * | 2007-04-09 | 2013-05-15 | キヤノン株式会社 | Light emitting device and manufacturing method thereof |
| JP5241724B2 (en) * | 2007-09-12 | 2013-07-17 | シャープ株式会社 | Shift register |
| EP2189988B1 (en) * | 2007-09-12 | 2012-12-12 | Sharp Kabushiki Kaisha | Shift register |
| JP2009181612A (en) * | 2008-01-29 | 2009-08-13 | Toshiba Mobile Display Co Ltd | Shift register circuit and liquid crystal display unit |
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