CN115715411A

CN115715411A - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN115715411A
Application number: CN202180001368.8A
Authority: CN
Inventors: 商广良; 刘利宾; 卢江楠; 冯宇; 殷新社; 史世明
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2023-02-24
Also published as: US20230282170A1; WO2022252710A1; CN115699155A; WO2022252092A1

Abstract

Disclosed are a shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit includes: an input circuit (110), a first control circuit (120), an output circuit (140), an output noise reduction circuit (130), and a reset circuit (150); the input circuit (110) is connected with the input end (IN) and is configured to control the level of the first node (P1) IN response to an input signal input by the input end (IN); the first control circuit (120) is connected with the first node (P1), the second node (P2) and the first clock signal terminal (CK), and is configured to control the level of the second node (P2) under the control of the level of the first node (P1) and the first clock signal provided by the first clock signal terminal (CK); an output circuit (140) is connected to the output terminal (OUT) and configured to output an output signal at the output terminal (OUT) under control of a level of the second node (P2); an output noise reduction circuit (130) is connected to the output terminal (OUT) and configured to reduce noise on the output terminal (OUT) under control of the level of the first node (P1); the reset circuit (150) is connected to the global reset terminal (RST) and the first voltage terminal (VGH) and is configured to turn off the output noise reduction circuit (130) in response to a global reset signal provided by the global reset terminal (RST), the global reset signal being at an inactive level during a first phase of operation and including at least one segment of an active level during a second phase of operation. The shift register unit can avoid the influence of the long-time continuous conduction of a transistor in the output noise reduction circuit (130) on the output reset and noise reduction capability of the output noise reduction circuit, thereby prolonging the service life of the shift register unit and improving the display quality of the display panel.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The embodiment of the disclosure relates to a shift register unit, a driving method thereof, a gate driving circuit and a display device.

Background

In the field of display technology, a pixel array, such as a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel, generally includes a plurality of rows of gate scan signal lines and a plurality of columns of data lines interleaved with the gate scan signal lines. The driving of the gate scan signal lines may be implemented by a bonded integrated driving circuit. In recent years, with the continuous improvement of the manufacturing process of the amorphous silicon thin film transistor or the oxide thin film transistor, a Gate scan signal line driving circuit may be directly integrated On the thin film transistor Array substrate to form a Gate driver On Array (GOA) to drive the Gate scan signal lines. For example, the GOA including a plurality of cascaded shift register units may be used to provide switching state voltage signals (scan signals) to a plurality of rows of gate scan signal lines of a pixel array, so as to control the plurality of rows of gate scan signal lines to be turned on sequentially, and simultaneously provide data signals to corresponding rows of pixel units in the pixel array from data lines, so as to form gray scale voltages required for displaying gray scales of an image in each pixel unit, thereby displaying an image of one frame.

Disclosure of Invention

At least one embodiment of the present disclosure provides a shift register unit, including: the device comprises an input circuit, a first control circuit, an output noise reduction circuit and a reset circuit; the input circuit is connected with the input end and is configured to respond to an input signal input by the input end to control the level of the first node; the first control circuit is connected with the first node, the second node and the first clock signal end and is configured to control the level of the second node under the control of the level of the first node and the first clock signal provided by the first clock signal end; the output circuit is connected with an output end and configured to output an output signal at the output end under the control of the level of the second node; the output noise reduction circuit is connected with the output end and is configured to reduce noise of the output end under the control of the level of the first node; the reset circuit is connected with a total reset terminal and a first voltage terminal and is configured to enable the output noise reduction circuit to be turned off in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is at an invalid level in a first operation stage and comprises at least one segment of valid level in a second operation stage.

For example, a shift register unit provided in at least one embodiment of the present disclosure further includes a second control circuit, where the second control circuit is connected to the first node, a third node, and a second clock signal terminal, and is configured to control a level of the third node under control of a level of the first node and a second clock signal provided by the second clock signal terminal; the output noise reduction circuit is further coupled to the third node and configured to output an inactive level of the output signal at the output terminal in response to a level of the third node.

For example, in the shift register unit provided in at least one embodiment of the present disclosure, the reset circuit is further connected to the third node, and is configured to reset the third node in response to a total reset signal provided by the total reset terminal, so that the output noise reduction circuit is turned off.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the second control circuit includes a first sub-circuit; the first sub-circuit is connected to the first node, the second clock signal terminal, and the third node, and configured to control a level of the third node under control of a level of the first node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the second control circuit further includes a second sub-circuit; the second sub-circuit is connected with a second voltage terminal, the first node and a first control node, and is configured to control the level of the first control node in response to a second voltage provided by the second voltage terminal; the first sub-circuit is further connected to the first control node and configured to control a level of the third node in response to a level of the first control node.

For example, the shift register unit provided in at least one embodiment of the present disclosure further includes a third control circuit, which is connected to the second node, a fourth node, and the second clock signal terminal, and configured to control a level of the fourth node under control of a level of the second node and a second clock signal provided by the second clock signal terminal.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the third control circuit includes a third sub-circuit and a fourth sub-circuit; the third sub-circuit is connected with the second clock signal end and a second control node and is configured to control the level of the second control node under the control of the level of the second node; the fourth sub-circuit is connected to the second clock signal terminal, the second control node, and the fourth node, and configured to control a level of the fourth node in response to a second clock signal provided from the second clock signal terminal.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the third control circuit further includes a fifth sub-circuit, which is connected to a second voltage terminal, the second node, and a third control node, and configured to control a level of the third control node in response to a second voltage provided by the second voltage terminal; the third sub-circuit is also connected to the third control node and configured to control a level of the second control node in response to a level of the third control node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the second control circuit further includes a sixth sub-circuit, which is connected to the second control node, the first voltage terminal, and the first sub-circuit, and configured to control a level of the first control node to be kept stable in response to a level of the second control node.

For example, the shift register unit provided in at least one embodiment of the present disclosure further includes a fourth control circuit connected to the first node, the first voltage terminal, and the fourth node, and configured to control a level of the fourth node in response to the level of the first node.

For example, at least one embodiment of the present disclosure provides a shift register unit further including a fifth control circuit, which is connected to the second control node, the third node, and the first voltage terminal, and configured to control a level of the third node in response to a level of the second control node.

For example, the shift register unit provided in at least one embodiment of the present disclosure further includes a sixth control circuit, where the sixth control circuit is connected to the total reset terminal, the first voltage terminal, and the first node, and is configured to reset the first node under the control of a reset signal provided by the total reset terminal.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the input circuit includes an input transistor, a gate of the input transistor and the first clock signal terminal are connected to receive the first clock signal, a first pole of the input transistor and the input terminal are connected to receive the input signal, and a second pole of the input transistor and the first node are connected.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the reset circuit includes a reset transistor, a gate of the reset transistor is connected to the overall reset terminal to receive the overall reset signal, a first pole of the reset transistor is connected to the first voltage terminal to receive a first voltage, and a second pole of the reset transistor is connected to the third node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the output noise reduction circuit includes an output noise reduction transistor, a gate of the output noise reduction transistor is connected to the third node, a first pole of the output noise reduction transistor is connected to the second voltage terminal to receive the second voltage, and a second pole of the output noise reduction transistor is connected to the output terminal.

For example, in the shift register unit provided in at least one embodiment of the present disclosure, the output noise reduction circuit further includes an output noise reduction capacitor, a first pole of the output noise reduction capacitor is connected to the second voltage terminal to receive the second voltage, and a second pole of the output noise reduction capacitor is connected to the third node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the output circuit includes an output transistor and an output capacitor; a gate of the output transistor is connected to the fourth node, a first pole of the output transistor is connected to the output terminal, and a second pole of the output transistor is connected to the first voltage terminal to receive a first voltage; a first pole of the output capacitor is coupled to the fourth node, and a second pole of the output capacitor is coupled to the first voltage terminal to receive the first voltage.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the first sub-circuit includes a first control transistor, a second control transistor, and a first control capacitor; a gate of the first control transistor is connected to the first control node, a first pole of the first control transistor is connected to the second clock signal terminal to receive the second clock signal, and a second pole of the first control transistor is connected to the first pole of the first control capacitor; a second pole of the first control capacitor is connected to the first control node; the gate and the first pole of the second control transistor are connected to each other and both connected to the first control node, and the second pole of the second control transistor is connected to the third node.

For example, in the shift register unit provided in at least one embodiment of the present disclosure, the second sub-circuit includes a third control transistor, a gate of the third control transistor is connected to the second voltage terminal, a first pole of the third control transistor is connected to the first node, and a second pole of the third control transistor is connected to the first control node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the sixth sub-circuit includes a fourth control transistor; a gate of the fourth control transistor is connected to the second control node, a first pole of the fourth control transistor is connected to the first voltage terminal to receive a first voltage, and a second pole of the fourth control transistor is connected to the first pole of the first control capacitor.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the sixth control circuit includes a fifth control transistor; a gate of the fifth control transistor is coupled to the global reset terminal to receive the global reset signal, a first pole of the fifth control transistor is coupled to the first voltage terminal to receive a first voltage, and a second pole of the fifth control transistor is coupled to the first node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the first control circuit includes a sixth control transistor and a seventh control transistor; a gate of the sixth control transistor is connected to the first node, a first pole of the sixth control transistor is connected to the first clock signal terminal to receive the first clock signal, and a second pole of the sixth control transistor is connected to the second node; a gate of the seventh control transistor is coupled to the first clock signal terminal to receive the first clock signal, a first pole of the seventh control transistor is coupled to the second voltage terminal to receive a second voltage, and a second pole of the seventh control transistor is coupled to the second node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the third sub-circuit includes an eighth control transistor and a third control capacitor, the fourth sub-circuit includes a ninth control transistor, and the fifth sub-circuit includes a tenth control transistor; a gate of the tenth control transistor and the second voltage terminal are connected to receive the second voltage, a first pole of the tenth control transistor and the second node are connected, and a second pole of the tenth control transistor and the third control node are connected; a first pole of the third control capacitor is connected to the third control node, and a second pole of the third control capacitor is connected to the second control node; a gate of the eighth control transistor is connected to the third control node, a first pole of the eighth control transistor is connected to the second clock signal terminal to receive the second clock signal, and a second pole of the eighth control transistor is connected to the second control node; the gate of the ninth control transistor is connected to the second clock signal terminal to receive the second clock signal, the first pole of the ninth control transistor is connected to the second control node, and the second pole of the ninth control transistor is connected to the fourth node.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the fourth control circuit includes an eleventh control transistor, a gate of the eleventh control transistor is connected to the first node, a first pole of the eleventh control transistor is connected to the fourth node, and a second pole of the eleventh control transistor is connected to the first voltage terminal to receive a first voltage.

For example, in a shift register unit provided in at least one embodiment of the present disclosure, the fifth control circuit includes a twelfth control transistor, a gate of the twelfth control transistor is connected to the second control node, a first pole of the twelfth control transistor is connected to the third node, and a second pole of the twelfth control transistor is connected to the first voltage terminal to receive the first voltage.

At least one embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units provided in any one embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a driving method of a shift register unit, including a first operation phase and a second operation phase; in the first operation phase, the driving method comprises a first sub-phase, a second sub-phase and a third sub-phase: in the first sub-phase, the input circuit controls the level of a first node in response to the effective level of the input signal input by the input end; the first control circuit controls the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal end; in the second sub-phase, the output circuit outputs an output signal at the output terminal under the control of the level of the second node; in the third sub-stage, the output noise reduction circuit reduces noise of the output end under the control of the level of the first node; in the second operation phase, the driving method includes at least one reset phase in which an active level of a total reset signal is applied to the total reset terminal, an inactive level of the first clock signal is applied to the first clock signal terminal, and the reset circuit turns off the output noise reduction circuit in response to the active level of the total reset signal.

For example, in a driving method provided by at least one embodiment of the present disclosure, in a case where the shift register unit further includes a second control circuit, wherein the second control circuit is connected to the first node, a third node, and a second clock signal terminal, and is configured to control a level of the third node under control of a level of the first node and a second clock signal provided by the second clock signal terminal; the output noise reduction circuit is further coupled to the third node and configured to output an inactive level of the output signal at the output terminal in response to a level of the third node; the reset phase further comprises: the reset circuit resets the third node in response to an active level of the total reset signal, so that the output noise reduction circuit is turned off in response to a level of the third node.

At least one embodiment of the present disclosure further provides a display device including the gate driving circuit provided in any one embodiment of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 is a schematic block diagram of a shift register unit according to at least one embodiment of the present disclosure;

fig. 2 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 3 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 4 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 5 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 6 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 7 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

fig. 8 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure;

FIG. 9 is a circuit diagram of a specific implementation of the shift register cell shown in FIG. 7 in some examples;

FIG. 10 is a circuit diagram of a specific implementation of the shift register cell shown in FIG. 7 in further examples;

FIG. 11 is a circuit diagram of a specific implementation of the shift register cell shown in FIG. 8 in some examples;

FIG. 12 is a circuit diagram of a specific implementation of the shift register cell shown in FIG. 2 in some examples;

FIG. 13 is a circuit diagram of a specific implementation of the shift register cell shown in FIG. 5 without the second sub-circuit and the sixth sub-circuit;

FIG. 14 is a circuit diagram of a particular implementation of the shift register cell of FIG. 7 in further examples;

fig. 15A shows a signal timing chart when the shift register unit 10 shown in fig. 14 operates;

fig. 15B shows a signal timing chart when the shift register unit 10 shown in fig. 11 operates;

fig. 16 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

fig. 17 is a schematic view of a display device according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components have been omitted from the present disclosure.

In order to keep the pixel brightness fluctuations within a reasonable range, the data still needs to be refreshed during static pictures, because the voltage controlling the pixel brightness will change over time due to leakage of the transistor. In order to reduce the power consumption of the display panel, the refresh frequency thereof can be reduced, and meanwhile, in order to ensure that the display quality of the display panel is not affected, the leakage speed of the transistor needs to be reduced, and the oxide semiconductor has the characteristic of ultra-low leakage, so as to meet the requirement.

When the gate driving circuit drives a plurality of rows of sub-pixel units in a display panel, the effective level of a gate scanning driving signal needs to be output line by line in a display stage to drive the plurality of rows of sub-pixel units to emit light line by line, and meanwhile, in order to ensure normal display of the display panel, in a blanking stage, the reset transistors of all shift register units in the gate driving circuit need to be started to reset and reduce noise of an output end, so that the ineffective level of the gate scanning signal is output in the blanking stage. However, in the blanking period, especially when the display panel is driven at a low frequency, the continuous turning on of the reset transistor for a long time may affect the ability of resetting the output and reducing the noise, thereby affecting the service life of the gate driving circuit.

At least one embodiment of the present disclosure provides a shift register unit, including: the device comprises an input circuit, a first control circuit, an output noise reduction circuit and a reset circuit; the input circuit is connected with the input end and is configured to respond to an input signal input by the input end to control the level of the first node; the first control circuit is connected with the first node, the second node and the first clock signal end and is configured to control the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal end; the output circuit is connected with the output end and is configured to output an output signal at the output end under the control of the level of the second node; the output noise reduction circuit is connected with the output end and is configured to reduce noise of the output end under the control of the level of the first node; the reset circuit is connected with the total reset terminal and the first voltage terminal and is configured to enable the output noise reduction circuit to be switched off in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is at an invalid level in a first operation stage, and at least one section of valid level is included in a second operation stage.

Some embodiments of the disclosure also provide a gate driving circuit, a display device and a driving method corresponding to the shift register unit.

The shift register unit provided by the embodiment of the disclosure resets the output noise reduction circuit through the reset circuit at the second operation stage, so that the influence of the long-time continuous conduction of the transistor in the output noise reduction circuit on the output reset and noise reduction capability of the output noise reduction circuit is avoided, the service life of the shift register unit can be prolonged, and the display quality of the display panel is improved.

In addition, in the embodiments of the present disclosure, for clarity and conciseness of representation, the definition of "one frame", "each frame", or "a certain frame" includes a first operation phase and a second operation phase that are sequentially performed, for example, the first operation phase is a display period, and the second operation phase is a blanking period, which is not limited in this regard. The following description takes the first operation phase as a display period and the second operation phase as a blanking period as an example, which is not limited by the embodiments of the disclosure. For example, in the display period, the gate driving circuit outputs the active level of the gate driving signal, the active level of the gate driving signal can drive a plurality of rows of sub-pixel units in the display panel to complete the scanning display of a complete image from the first row to the last row, and in the blanking period, the gate driving circuit outputs the inactive level of the gate driving signal, thereby avoiding the display abnormity of the panel.

Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a shift register unit according to at least one embodiment of the present disclosure. As shown in fig. 1, in some examples, the shift register cell 10 may include an input circuit 110, a first control circuit 120, an output noise reduction circuit 130, an output circuit 140, and a reset circuit 150. By cascading a plurality of shift register units 10, a gate driving circuit can be obtained, where the gate driving circuit is used to drive a display panel and sequentially provides scanning signals for a plurality of gate lines of the display panel, so as to perform progressive or interlaced scanning and the like during a period when the display panel displays a frame of picture.

For example, as shown IN fig. 1, the input circuit 110 is connected to the input terminal IN and configured to control a level of the first node P1 IN response to an input signal input to the input terminal IN. For example, IN some examples, the input circuit 110 is connected to the input terminal IN, the first clock signal terminal CK, and the first node P1, and is configured to be turned on under control of the first clock signal supplied from the first clock signal terminal CK, so that the input terminal IN and the first node P1 are connected, thereby causing the input signal supplied from the input terminal IN to be input to the first node P1, and charging the potential of the first node P1 to an operating potential (e.g., a potential at which a transistor connected to the first node P1 can be turned on). For example, IN other examples, the input circuit 110 may be connected to the input terminal IN and the first node P1, and configured to be turned on under the control of the input signal provided by the input terminal IN to connect the input terminal IN and the first node P1, so that the input signal provided by the input terminal IN is input to the first node P1, and the potential of the first node P1 is pulled up to the operating potential. It should be noted that the embodiment of the present disclosure is not limited thereto as long as it is satisfied that the first node P1 can be charged at a corresponding stage.

For example, the first control circuit 120 is connected to the first node P1, the second node P2 and the first clock signal terminal CK, and is configured to control the level of the second node P2 under the control of the level of the first node P1 and the first clock signal provided by the first clock signal terminal CK. For example, in some examples, the first control circuit 120 is connected to the first node P1, the second node P2, the second voltage terminal VGL, and the first clock signal terminal CK, and is configured to be turned on under the control of the level of the first node P1 and the first clock signal provided by the first clock signal terminal CK, such that the second node P2 is connected to the second voltage terminal VGL to receive the second voltage or to the first clock signal terminal CK to receive the first clock signal, thereby achieving the control of the level of the second node P2.

For example, the output circuit 140 is connected to the output terminal OUT, and configured to output an output signal at the output terminal OUT under the control of the level of the second node P2. For example, in some examples, the output circuit 140 is connected to the output terminal OUT, the fourth node P4, and the first voltage terminal VGH, and is configured to be turned on under the control of the level of the fourth node P4, so that the first voltage provided by the first voltage terminal VGH is output to the output terminal OUT as an output signal. The fourth node P4 is connected to the second node P2, for example, through the third control circuit 170, that is, the output circuit 140 is indirectly connected to the second node P2, that is, controlled by the second node P2, and thus may be configured to be turned on under the control of the level of the second node P2, so that the first voltage provided by the first voltage terminal VGH is output to the output terminal OUT as the output signal.

It should be noted that in the embodiment of the present disclosure, "under the control of the level of the second node" may indicate that the second node indirectly controls the output circuit, that is, whether the output circuit is turned on or not may be controlled by the level (i.e., the level of the fourth node P4) output by another circuit (e.g., the third control circuit) related to the level of the second node, and of course, the level control of the second node P2 may also be directly received, which is not limited in this embodiment of the present disclosure. The following examples are similar and will not be described in detail.

For example, the output noise reduction circuit 130 is connected to the output terminal OUT and configured to reduce noise of the output terminal OUT under the control of the level of the first node P1. For example, in some examples, the output noise reduction circuit 130 is connected to the second voltage terminal VGL third node P3 and the output terminal OUT, and is configured to connect the output terminal OUT and the second voltage terminal VGL when turned on under the control of the level of the third node P3, so that the output terminal OUT can be pulled down (e.g., discharged) by the second voltage VGL to achieve noise reduction. The third node P3 is connected to the first node P1 through the second control circuit 160, that is, the output noise reduction circuit 130 is indirectly connected to the first node P1, that is, indirectly controlled by the first node P1, and thus may also be configured to be turned on under the control of the level of the first node P1, so that the second voltage provided by the second voltage terminal VGL is output to the output terminal OUT, so as to implement noise reduction.

The reset circuit 150 is connected to the overall reset terminal RST and the first voltage terminal VGH, and is configured to turn off the output noise reduction circuit 130 in response to an overall reset signal provided from the overall reset terminal RST. For example, the total reset signal is at an inactive level during the first phase of operation and includes at least one active level (e.g., a level that turns on a transistor) during the second phase of operation. For example, the reset circuit 150 is connected to the third node P3, the total reset terminal RST and the first voltage terminal VGH, and is configured to cause the first voltage terminal VGH to be connected to the third node P3 in response to a total reset signal provided by the total reset terminal RST to reset the third node P3, thereby causing the output noise reduction circuit 130 to be turned off in response to a level of the third node P3.

For example, in the second operation phase, i.e. the blanking phase, the total reset signal includes at least one segment of active level, so that the reset circuit 150 can be made to be turned on in response to the at least one segment of active level of the total reset signal in the blanking phase, and the third node P3 is reset to the first voltage at least once, so that the output noise reduction circuit 130 is turned off at least once in response to the level of the third node P3, thereby preventing the transistor included in the output noise reduction circuit 130 from being continuously turned on for a long time in the blanking phase to affect the performance of the transistor to affect the output reset and noise reduction capability of the output noise reduction circuit 130, so that the service life of the circuit can be prolonged, and the display quality of the display panel can be ensured.

It should be noted that in the first operation phase, i.e. the display phase, the transistors in the output noise reduction circuit are not always turned on, for example, in the phase of the display phase in which the output circuit outputs the output signal, the output noise reduction circuit is turned off, and therefore, in the display phase, the reset signal is at an inactive level, so that the normal operation of the shift register unit can be ensured.

For example, as shown in fig. 1, the shift register unit 10 further includes a second control circuit 160, for example, the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB. For example, in some examples, the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and is configured to connect the third node P3 and the second clock signal terminal CB under the level control of the first node P1 to provide the second clock signal provided by the second clock signal terminal CB to the third node P3, so as to control the level of the third node P3.

For example, in this example, the output noise reduction circuit 130 is also connected to the third node P3, and is configured to output an inactive level of the output signal (e.g., a level that turns off the transistor) at the output terminal OUT in response to the level of the third node P3. For example, the reset circuit is further connected to the third node P3, and is configured to reset the third node P3 in response to a total reset signal provided by the total reset terminal RST, so that the output noise reduction circuit 130 is turned off. For a detailed description, reference may be made to the above description of the output noise reduction circuit 130 and the reset circuit 150, which are not described herein again.

For example, as shown in fig. 1, in other examples, the shift register unit 10 further includes a third control circuit 170, and the third control circuit 170 is connected to the second node P2, the fourth node P4 and the second clock signal terminal CB, and configured to control the level of the fourth node P4 under the control of the level of the second node P2 and the second clock signal provided by the second clock signal terminal CB. For example, in some examples, the third control circuit 170 is connected to the second node P2, the fourth node P4 and the second clock signal terminal CB, and is configured to connect the fourth node P4 and the second node P2 under the control of the level of the second node P2 and the second clock signal provided by the second clock signal terminal CB, so as to provide the level of the second node P2 to the fourth node P4, thereby controlling the level of the fourth node P4.

Fig. 2 is a schematic block diagram of another shift register unit according to at least one embodiment of the present disclosure. For example, as shown in fig. 2, the second control circuit 160 includes a first sub-circuit 161; for example, the first sub-circuit 161 is connected to the first node P1, the second clock signal terminal CB, and the third node P3, and configured to control the level of the third node P3 under the control of the level of the first node P1. For example, in some examples, the first sub-circuit 161 is connected to the first node P1, the second clock signal terminal CB, and the third node P3, and configured to connect the second clock signal terminal CB to the third node P3 under the control of the level of the first node P1, thereby controlling the level of the third node P3.

Fig. 3 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure. For example, as shown in fig. 3, the second control circuit 160 further includes a second sub-circuit 162; the second sub-circuit 162 is connected to the second voltage terminal VGL, the first node P1, and the first control node P11, and configured to control a level of the first control node P11 in response to a second voltage provided from the second voltage terminal VGL; the first sub-circuit 161 is also connected to the first control node P11 and configured to control the level of the third node P3 in response to the level of the first control node P11. For example, in some examples, the second sub circuit 162 is turned on in response to the second voltage provided by the second voltage terminal VGL, such that the first node P1 and the first control node P11 are connected, such that the level of the first control node P11 is the same as the level of the first node P1; in this example, the first sub-circuit 161 is turned on in response to the level of the first control node P11, so that the second clock signal terminal CB is connected to the third node P3, thereby controlling the level of the third node P3.

Fig. 4 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure. For example, as shown in fig. 4, the second control circuit 160 further includes a sixth sub-circuit 163. For example, the sixth sub-circuit 163 is connected with the second control node P21, the first voltage terminal VGH, and the first sub-circuit 161, and is configured to control the level of the first control node P11 to be kept stable in response to the level of the second control node P21. For example, in some examples, the sixth sub-circuit 163 is turned on in response to the level of the second control node P21, so that the first voltage terminal VGH is connected to the first sub-circuit 161, thereby preventing the second clock signal terminal CB connected to the first sub-circuit 161 from affecting the level of the first control node P11 when the second clock signal is changed, and thus affecting the normal operation of the shift register unit.

Fig. 5 is a schematic block diagram of another shift register unit according to at least one embodiment of the present disclosure. For example, as shown in fig. 5, the third control circuit includes a third sub-circuit 171 and a fourth sub-circuit 172; the third sub-circuit 171 is connected to the second clock signal terminal CB and the second control node P21, and configured to control the level of the second control node P21 under the control of the level of the second node P2; the fourth sub-circuit 172 is connected to the second clock signal terminal CB, the second control node P21, and the fourth node P4, and is configured to control a level of the fourth node P4 in response to the second clock signal provided from the second clock signal terminal CB. For example, in some examples, the third sub-circuit 171 is turned on under the control of the level of the second node P2, so that the second clock signal terminal CB is connected to the second control node P21, thereby supplying the second clock signal provided by the second clock signal terminal CB to the second control node P21 to control the level of the second control node P21; the fourth sub-circuit 172 is turned on in response to the second clock signal provided from the second clock signal terminal CB so that the second control node P21 is connected to the fourth node P4, thereby inputting the level of the second control node P21 to the fourth node P4 to control the level of the fourth node P4.

Fig. 6 is a schematic block diagram of another shift register unit provided in at least one embodiment of the present disclosure. For example, as shown in fig. 6, the third control circuit 170 further includes a fifth sub-circuit 173, e.g., the third sub-circuit 173 is connected to the second voltage terminal VGL, the second node P2, and the third control node P31, and configured to control a level of the third control node P31 in response to a second voltage provided from the second voltage terminal VGL; the third sub-circuit 173 is also connected to the third control node P31, and is configured to control the level of the second control node P21 in response to the level of the third control node P31. For example, in some examples, the fifth sub-circuit 173 is turned on in response to the second voltage provided from the second voltage terminal VGL, and inputs the level of the second node P2 to the third control node P31 to control the level of the third control node P31; in this example, the third sub-circuit 173 is configured to be turned on in response to the level of the third control node P31 such that the second clock signal terminal CB is connected to the second control node P21, thereby supplying the second clock signal provided from the second clock signal terminal CB to the second control node P21 to control the level of the second control node P21.

Fig. 7 is a schematic block diagram of another shift register unit according to at least one embodiment of the present disclosure. For example, as shown in fig. 7, the shift register unit 10 further includes a fourth control circuit 180 on the basis of the example shown in fig. 6. For example, the fourth control circuit 180 is connected with the first node P1, the first voltage terminal VGH, and the fourth node P4, and is configured to control the level of the fourth node P4 in response to the level of the first node P1. For example, in some examples, the fourth control circuit 180 is turned on in response to the level of the first node P1, such that the first voltage terminal VGH is connected to the fourth node P4, and thus the first voltage provided by the first voltage terminal VGH is input to the fourth node P4 to control the level of the fourth node P4.

For example, as shown in fig. 7, the shift register unit 10 further includes a fifth control circuit 190. For example, the fifth control circuit 190 is connected with the second control node P21, the third node P3, and the first voltage terminal VGH, and is configured to control the level of the third node P3 in response to the level of the second control node P21. For example, in some examples, the fifth control circuit 190 is configured to turn on in response to the level of the second control node P21 such that the third node P3 is connected with the first voltage terminal VGH to receive the first voltage, thereby enabling control of the level of the third node P3.

Fig. 8 is a schematic block diagram of another shift register unit according to at least one embodiment of the present disclosure. For example, as shown in fig. 8, on the basis of the example shown in fig. 7, the shift register unit further includes a sixth control circuit 200, for example, the sixth control circuit 200 is connected with the total reset terminal RST, the first voltage terminal VGH and the first node P1, and is configured to reset the first node P1 under the control of a reset signal provided by the total reset terminal RST. For example, in some examples, the sixth control circuit 200 is configured to turn on in response to a reset signal provided by the overall reset terminal RST, so that the first node P1 is connected with the first voltage terminal VGH to receive the first voltage, thereby enabling resetting of the first node P1.

For example, in this example, in the blanking phase, when the reset signal is at the active level, the first node P1 is reset, so that the first control circuit 120, the second control circuit 160, and the fourth control circuit 180 are turned off, so that the transistors T2, T4, T5, and T8 (shown in fig. 9) included therein are restored in a short time, and thus the state of the shift register unit can be further stabilized, and the service life of the circuit can be extended.

It will be appreciated by those skilled in the art that although a plurality of control circuits and a plurality of reset circuits are shown in fig. 1-8, the above examples are not intended to limit the scope of the present disclosure. In practical applications, a skilled person may choose to use or not use one or more of the above circuits according to circumstances, and various combination modifications based on the above circuits do not depart from the principle of the present disclosure, and are not described in detail here.

When the shift register unit shown in fig. 7 does not include the sixth sub-circuit 163, fig. 9 is a circuit diagram of a specific implementation manner of the shift register unit shown in fig. 7 in some examples, and in some embodiments of the present disclosure, the shift register unit 10 shown in fig. 7 may be implemented as the circuit structure shown in fig. 9. As shown in fig. 9, the shift register unit 10 includes: the input transistors M1 to tenth control transistors M14, the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4. Note that, the transistors shown in fig. 9 are all illustrated by taking P-type transistors as examples, which is not limited in this embodiment of the present disclosure, and for example, at least some of the transistors in the shift register unit 10 may also be N-type transistors.

When the shift register unit shown in fig. 7 includes the sixth sub-circuit 163, fig. 10 is a circuit diagram of a specific implementation manner of the shift register unit shown in fig. 7 in some examples, that is, on the basis of the example shown in fig. 9, the shift register unit further includes a fourth control transistor T16. A detailed implementation of the shift register cell shown in fig. 7 is described below in conjunction with fig. 9 and 10.

For example, as shown IN fig. 9, the input circuit 110 includes an input transistor T1, a gate of the input transistor T1 is connected to the first clock signal terminal CK to receive the first clock signal, a first pole of the input transistor T1 is connected to the input terminal IN to receive the input signal, and a second pole of the input transistor T1 is connected to the first node P1.

For example, IN other embodiments, the gate and the first pole of the input transistor T1 may also be both connected to the input terminal IN to receive the input signal, so that the input signal is input to the first node P1 when turned on IN response to the input signal.

For example, as shown in fig. 9, the reset circuit 150 includes a reset transistor T12, a gate of the reset transistor T12 is connected to the overall reset terminal RST to receive an overall reset signal, a first pole of the reset transistor T12 and a first voltage terminal VGH are connected to receive a first voltage, and a second pole of the reset transistor T12 and a third node P3 are connected.

For example, the output noise reduction circuit 130 includes an output noise reduction transistor T10, a gate of the output noise reduction transistor T10 is connected to the third node P3, a first pole of the output noise reduction transistor T10 is connected to the second voltage terminal VGL to receive the second voltage, and a second pole of the output noise reduction transistor T10 is connected to the output terminal OUT.

For example, the output noise reduction circuit 130 further includes an output noise reduction capacitor C3, a first pole of the output noise reduction capacitor C3 is connected to the second voltage terminal VGL to receive the second voltage, and a second pole of the output noise reduction capacitor C3 is connected to the third node P3.

For example, in some examples, the output noise reduction circuit 130 may not include the output noise reduction capacitor C3, as shown in fig. 14, the parasitic capacitor C31 of the output noise reduction transistor T10 serves as the output noise reduction capacitor C3, since the size of the output noise reduction transistor T10 is relatively large, and the parasitic capacitor C31 itself is also relatively large, the parasitic capacitor C31 may serve as the output noise reduction capacitor C3, for example, the capacitance value of the parasitic capacitor C31 is less than or equal to that of the output noise reduction capacitor, the reduction of the capacitance value of the output noise reduction circuit 130 may increase the reset speed, the speed of resetting the third node P3 may also become fast, and the fluctuation margin of the threshold voltage Vth of the output transistor T10 may be increased, which is beneficial to prolonging the service life of the shift register unit; meanwhile, the occupied area and the size of the shift register unit can be reduced, and the narrow frame is favorably realized.

For example, as shown in fig. 9, the output circuit 140 includes an output transistor T9 and an output capacitor C2; for example, the gate of the output transistor T9 is connected to the fourth node P4, the first pole of the output transistor T9 is connected to the output terminal OUT, and the second pole of the output transistor T9 is connected to the first voltage terminal VGH to receive the first voltage; a first pole of the output capacitor C2 is connected to the fourth node P4, and a second pole of the output capacitor is connected to the first voltage terminal VGH to receive the first voltage.

For example, as shown in fig. 9, the first sub-circuit 161 includes a first control transistor T4, a second control transistor T5, and a first control capacitor C4; a gate of the first control transistor T4 is connected to the first control node P11, a first pole of the first control transistor T4 is connected to the second clock signal terminal CB to receive the second clock signal, and a second pole of the first control transistor T4 is connected to the first pole of the first control capacitor C4; the second pole of the first control capacitor C4 is connected to the first control node P11; the gate and first pole of the second control transistor T5 are connected to each other and both connected to the first control node P11, and the second pole of the second control transistor T5 is connected to the third node P3.

For example, the second sub-circuit 162 includes a third control transistor T13, a gate of the third control transistor T13 is connected to the second voltage terminal VGL, a first pole of the third control transistor T13 is connected to the first node P1, and a second pole of the third control transistor T13 is connected to the first control node P11.

For example, as shown in fig. 10, the sixth sub-circuit 163 includes a fourth control transistor T16; the gate of the fourth control transistor T16 is connected to the second control node P21, the first pole of the fourth control transistor T16 is connected to the first voltage terminal VGH to receive the first voltage, and the second pole of the fourth control transistor T16 is connected to the first pole of the first control capacitor C4, so that when the second control node P21 is at an active level, the voltage of the first pole of the first control capacitor C4 is stabilized at the first voltage, and when the level of the second clock signal provided by the second clock signal terminal CB connected to the first control transistor T4 is changed, due to the charge conservation principle of the first control capacitor C4, the level of the first control node P11 is changed along with the change of the second clock signal, thereby preventing the second clock signal terminal CB from affecting the level of the first control node P11, further affecting the leakage of the output noise reduction transistor T10, and reducing noise when a high level is output.

For example, as shown in fig. 9, the first control circuit 120 includes a sixth control transistor T2 and a seventh control transistor T3; a gate of the sixth control transistor T2 is connected to the first node P1, a first pole of the sixth control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, and a second pole of the sixth control transistor T2 is connected to the first node P1; the gate of the seventh control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, the first pole of the seventh control transistor T3 is connected to the second voltage terminal VGL to receive the second voltage, and the second pole of the seventh control transistor T3 is connected to the second node P2.

For example, as shown in fig. 9-11, the third sub-circuit 171 includes an eighth control transistor T6 and a third control capacitor C1, the fourth sub-circuit includes a ninth control transistor T7, and the fifth sub-circuit includes a tenth control transistor T14; a gate of the tenth control transistor T14 is connected to the second voltage terminal VGL to receive the second voltage, a first pole of the tenth control transistor T14 is connected to the second node P2, and a second pole of the tenth control transistor T14 is connected to the third control node P31; a first pole of the third control capacitor C1 is connected to the third control node P31, and a second pole of the third control capacitor C1 is connected to the second control node P21; a gate of the eighth control transistor T6 is connected to the third control node P31, a first pole of the eighth control transistor T6 is connected to the second clock signal terminal CB to receive the second clock signal, and a second pole of the eighth control transistor T6 is connected to the second control node P21; the gate of the ninth control transistor T7 is connected to the second clock signal terminal CB to receive the second clock signal, the first pole of the ninth control transistor T7 is connected to the second control node P2, and the second pole of the ninth control transistor T9 is connected to the fourth node P4.

For example, the third control transistor T13 may reduce the first control node P11 leakage, and the tenth control transistor T14 may reduce the third control node P31 leakage, thereby making the response speed of the gate driving signal output faster.

For example, the fourth control circuit 180 includes an eleventh control transistor T8, a gate of the eleventh control transistor T8 is connected to the first node P1, a first pole of the eleventh control transistor T8 is connected to the fourth node P4, and a second pole of the eleventh control transistor T8 is connected to the first voltage terminal VGH to receive the first voltage.

For example, the fifth control circuit 190 includes a twelfth control transistor T11, a gate of the twelfth control transistor T11 is connected to the second control node P21, a first pole of the twelfth control transistor T11 is connected to the third node P3, and a second pole of the twelfth control transistor P21 is connected to the first voltage terminal VGH to receive the first voltage.

Fig. 11 is a circuit diagram of a specific implementation manner of the shift register unit shown in fig. 8 in some examples, and in some embodiments of the present disclosure, the shift register unit 10 shown in fig. 8 may be implemented as the circuit structure shown in fig. 11. As shown in fig. 11, the shift register unit 10 further includes, in addition to the example shown in fig. 9: and a fifth control transistor T15. It should be noted that the circuit structure shown in fig. 11 is substantially the same as the circuit structure shown in fig. 9, and specific description may refer to the description in fig. 9, and is not repeated herein.

For example, as shown in fig. 11, the sixth control circuit 200 includes a fifth control transistor T15; the gate of the fifth control transistor T15 is connected to the total reset terminal RST to receive the total reset signal, the first pole of the fifth control transistor T15 is connected to the first voltage terminal VGH to receive the first voltage, and the second pole of the fifth control transistor T15 is connected to the first node P1.

Fig. 12 is a circuit diagram of a specific implementation manner of the shift register unit shown in fig. 2 in some examples, and in some embodiments of the present disclosure, the shift register unit 10 shown in fig. 2 may be implemented as the circuit structure shown in fig. 12. As shown in fig. 12, the second control circuit 160 of the shift register unit 10 includes only the first sub-circuit on the basis of the example shown in fig. 9, i.e., does not include the third control transistor T13 on the basis of the example shown in fig. 9. It should be noted that the circuit structure shown in fig. 12 is substantially the same as the circuit structure shown in fig. 9, and the detailed description may refer to the introduction in fig. 9, and is not repeated herein.

Fig. 13 is a circuit diagram of a specific implementation manner of the shift register unit shown in fig. 5 when the second sub-circuit and the sixth sub-circuit are not included, and in some embodiments of the present disclosure, the shift register unit 10 shown in fig. 5 may be implemented as the circuit structure shown in fig. 13 when the second sub-circuit and the sixth sub-circuit are not included. As shown in fig. 13, the second control circuit 160 of the shift register unit 10 only includes the first sub-circuit and the third control circuit 170 only includes the third sub-circuit and the fourth sub-circuit on the basis of the example shown in fig. 9, that is, the third control transistor T13 and the tenth control transistor T14 are not included on the basis of the example shown in fig. 9, and in this example, not only the function of the shift register unit is not affected, but also it is advantageous to realize a narrow bezel. It should be noted that the circuit structure shown in fig. 13 is substantially the same as the circuit structure shown in fig. 9, and the detailed description may refer to the introduction in fig. 9, and is not repeated herein.

As described above, in the shift register unit 10 provided in the embodiment of the present disclosure, the potential at the second control node P21 may be maintained by the third control capacitor C1, the potential at the fourth node P4 may be maintained by the output capacitor C2, the potential at the third node P3 may be maintained by the output noise reduction capacitor C3 or the parasitic capacitor C31, and the potential at the first control node P11 may be maintained by the first control capacitor C4. The third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4 may be capacitor devices manufactured by a process, for example, the capacitor devices are realized by manufacturing dedicated capacitor electrodes, each electrode of the capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), and the like, or in some examples, by designing circuit wiring parameters, the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4 may also be realized by a parasitic capacitor between each device. The connection modes of the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3 and the first control capacitor C4 are not limited to the above-described modes, and may be other suitable connection modes as long as the levels written into the second control node P21, the fourth node P4, the third node P3 and the first control node P11 can be stored.

It should be noted that in some embodiments of the present disclosure, VGH represents both the first voltage terminal and the first voltage, and VGL represents both the second voltage terminal and the second voltage. The first voltage VGH is, for example, a high level, and the second voltage VGL is, for example, a low level, and for example, the first voltage VGH is greater than the second voltage VGL.

In addition, it should be noted that in some embodiments of the present disclosure, the high level and the low level are relative terms. The high level represents a higher voltage range (for example, the high level may use 5V, 10V or other suitable voltages), and the high levels may be the same or different. Similarly, a low level represents a lower voltage range (e.g., the low level may be 0V, -5V, -10V or other suitable voltages), and the low levels may be the same or different. For example, the minimum value of the high level is larger than the maximum value of the low level.

It should be noted that, in some embodiments of the present disclosure, controlling the level of a node (e.g., the first node P1, etc.) includes charging the node to pull up the level of the node or discharging the node to pull down the level of the node. For example, a capacitor (e.g., capacitors C1-C4) may be provided that is electrically connected to the node, and charging the node means charging the capacitor that is electrically connected to the node; similarly, discharging the node means discharging a capacitor electrically connected to the node; the high or low level of the node can be maintained by the capacitor.

It should be noted that CK represents both the first clock signal terminal and the first clock signal, and CB represents both the second clock signal terminal and the second clock signal, which are the same as the following embodiments and are not described again.

In embodiments of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the term "pull-up" means charging a node or an electrode of a transistor such that an absolute value of a level of the node or the electrode is raised, thereby implementing an operation (e.g., conduction) of the corresponding transistor; "pull-down" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is lowered, thereby achieving operation (e.g., turning off) of the corresponding transistor.

For another example, when each circuit is implemented as a P-type transistor, the term "pull-up" means discharging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is lowered, thereby achieving operation (e.g., conduction) of the corresponding transistor; "pull down" means charging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is raised, thereby achieving operation (e.g., turning off) of the corresponding transistor.

It should be noted that, in the description of the various embodiments of the present disclosure, the first node P1, the second node P2, the third node P3, the fourth node P4, the first control node P11, the second control node P21, and the third control node P31 do not represent actually existing components, but represent junctions of relevant electrical connections in a circuit diagram.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors are used as examples in the embodiments of the present disclosure for description. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of the poles is directly described as a first pole, and the other pole is directly described as a second pole. Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the turn-off voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high level voltage (e.g., 5V, 10V, or other suitable voltage) and the turn-off voltage is a low level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

In addition, the transistors in the embodiments of the present disclosure are all exemplified by P-type transistors, and in this case, the first electrode of the transistor is a drain, and the second electrode of the transistor is a source. It is noted that the present disclosure includes but is not limited thereto. For example, one or more transistors in the shift register unit 10 provided in the embodiment of the present disclosure may also be N-type transistors, in which case, the first pole of the transistor is a source, and the second pole of the transistor is a drain, and it is only necessary to connect the poles of the selected type of transistors with reference to the poles of the corresponding transistors in the embodiment of the present disclosure, and make the corresponding voltage terminal provide the corresponding high level or low level. When an N-type transistor is used, indium Gallium Zinc Oxide (IGZO) may be used as an active layer of the thin film transistor, and compared to Low Temperature Polysilicon (LTPS) or amorphous Silicon (e.g., hydrogenated amorphous Silicon) as an active layer of the thin film transistor, the size of the transistor may be effectively reduced and leakage current may be prevented.

At least one embodiment of the present disclosure further provides a driving method of the shift register unit. Fig. 15A shows a signal timing chart when the shift register unit 10 shown in fig. 14 operates.

For example, as shown in fig. 15A, the driving method includes a first operation stage S1 and a second operation stage S2; in the first operating phase S1, the driving method comprises a first sub-phase t1, a second sub-phase t2 and a third sub-phase t3. One frame includes a first operation phase S1 (i.e., a display phase) and a second operation phase S2 (i.e., a blanking phase), the display phase is used for driving the display panel to display, and the blanking phase is a phase between the display phase of the current frame and the display phase of the next frame. The signal levels in the signal timing chart shown in fig. 15A are only schematic and do not represent real level values.

IN the first sub-phase t1, the input circuit 110 controls the level of the first node P1 IN response to the active level of the input signal input from the input terminal IN; the first control circuit 120 controls the level of the second node P2 under the control of the level of the first node P1 and the first clock signal provided from the first clock signal terminal CK.

In the second sub-phase t2, the output circuit 140 outputs the output signal at the output terminal OUT under the control of the level of the second node P2.

In the third sub-stage t3, the output noise reduction circuit 130 reduces noise at the output terminal OUT under the control of the level of the first node P1.

In further examples, the driving method further comprises a fourth sub-phase t4, a fifth sub-phase t5 and a sixth sub-phase t6.

The following describes in detail an operation method of the shift register unit 10 according to at least one embodiment of the present disclosure with reference to fig. 15A and fig. 14. For example, the first sub-phase t1 is an input phase t1, the second sub-phase t2 is an output phase t2, the third sub-phase t3 is a reset phase t3, the fourth sub-phase t4 is a first holding time period t4, the fifth sub-phase t5 is a second holding time period t5, and the sixth sub-phase t6 is a third holding time period t6. In the first operation stage S1, the total reset signal terminal RST provides a high level, and the reset transistor T12 is turned off in response to the high level of the total reset signal.

IN the input stage T1, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, the input terminal IN provides a high level, the input transistor T1 is turned on IN response to the low level of the first clock signal, the third control transistor T13 is turned on IN response to the second voltage provided by the second voltage terminal VGL, the potential of the first node P1 is a high level, the potential of the first control node P11 is a high level, and both the first control transistor T4 and the second control transistor T5 are turned off IN response to the high level of the first control node P11; the sixth control transistor T2 is turned off in response to a high level of the first node P1, the seventh control transistor T3 is turned on in response to a low level of the first clock signal, the tenth control transistor T14 is turned on in response to the second voltage supplied from the second voltage terminal VGL, the potential of the second node P2 is a low level, the potential of the third control node P31 is a low level, the eighth control transistor T6 is turned on in response to a low level of the third control node P31, the potential of the second control node P21 is a high level, the ninth control transistor T7 is turned off in response to a high level of the second clock signal, the eighth control transistor T8 is turned off in response to a high level of the first node, the twelfth control transistor T11 is turned off in response to a high level of the second control node P21, the potential of the third node P3 is maintained at a high level, the potential of the fourth node P4 is maintained at a high level, the output noise reduction transistor T10 is turned off in response to a high level of the third node, the ninth transistor T9 is turned off in response to a low level of the fourth node P4, and the output terminal OUT is turned off.

IN the output stage T2, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is turned off, the third control transistor T13 is turned on, and the potentials of the first node P1 and the first control node P11 are maintained at a high level; the first control transistor T4 is turned off, the second control transistor T5 is turned off, the sixth control transistor T2 and the seventh control transistor T3 are turned off, the potential of the second node P2 is maintained at a low level, the eighth control transistor T6 is turned on, the low level provided from the second clock signal terminal CB is inputted to the second control node P21, the second control node P21 is changed from a high level to a low level, the potential of the third control node P31 is further pulled down by the third control capacitor C1 according to the charge conservation principle of the third control capacitor C1, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned off, the twelfth control transistor T11 is turned on in response to the low level of the second control node P21, the potential of the fourth node P4 is a low level, the potential of the third node P3 is still at a high level, and therefore, the ninth transistor T9 is turned on, the output noise reduction transistor T10 is turned on, and the output terminal vgout is turned off.

IN the reset stage T3, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the input transistor T1 is turned on, the potential of the first node P1 is pulled down, the third control transistor T13 is turned on, the potential of the first control node P11 is pulled down, the second control transistor T5 is turned on, and the potential of the third node P3 is pulled down; the output noise reduction transistor T10 is turned on in response to the level of the third node P3, and outputs the second voltage provided by the second voltage terminal VGL to the output terminal OUT, and the output terminal OUT outputs a low level, thereby realizing noise reduction of the output terminal OUT; the sixth control transistor T2 and the seventh control transistor T3 are turned on, the potential of the second node P2 is at a low level, the tenth control transistor T14 is turned on, the eighth control transistor T6 is turned on, the second control node P21 becomes a high level provided by the second clock signal terminal CB, the potential of the third control node P3 is pulled high according to the charge conservation principle of the third control capacitor, and the ninth control transistor T7 is turned off; the eighth control transistor T8 is turned on in response to the low level of the first node, and the potential of the fourth node P4 is pulled high, and the ninth transistor T9 is turned off.

IN a first holding time period T4 included IN the holding phase, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is turned off, the potential of the first node P1 is maintained at the low level, the third control transistor T13 is turned on, the first control transistor T4 is turned on, the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4, the second control transistor T5 is turned on, so that the potential of the third node P3 is maintained to be lower than VGL + Vth, vth is a threshold voltage of the output noise reduction transistor T10, the output noise reduction transistor T10 is turned on, and further the potential of the gate driving signal output by the output terminal OUT is maintained at a second voltage, that is, maintained at the low level, and is not affected by noise interference; the seventh control transistor T3 is turned off, the sixth control transistor T2 is turned on, the potential of the second node P2 is at the high level provided by the first clock signal terminal CK, the tenth control transistor T14 is turned on, the potential of the third control node P31 is at the high level, the potential of the second control node P21 is at the high level, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned on, the potential of the fourth node P4 is at the high level, and the ninth transistor T9 is turned off.

During a second holding time period T5 included IN the holding phase, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the input transistor T1 is turned on, the potential of the first node P1 is a low level, the third control transistor T13 is turned on, the first control node P11 is a low level, the first control transistor T4 is turned on IN response to the low level of the first control node P11, the potential of the input clock signal provided by the second clock signal terminal CB is raised, according to the charge conservation principle of the first control capacitor C4, the potential of the first control node P11 is raised, the second control transistor T5 is turned off, the potential of the third node P3 is not affected, so that the potential of the third node P3 is maintained to be lower than VGL + Vth, vth is a threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, and further the potential of the gate driving signal output by the output terminal OUT is maintained to be a second voltage, that is not affected by noise interference; the seventh control transistor T3 is turned on, the potential of the second node P2 is at a low level, the sixth control transistor T2 is turned on, the tenth control transistor T14 is turned on, the potential of the third control node P31 is at a low level, the eighth control transistor T6 is turned on, the potential of the second control node P21 is at a high level, the ninth control transistor T7 is turned off, the eighth control transistor T8 is turned off, the potential of the fourth node P4 is maintained at a high level, and the ninth transistor T9 is turned off.

IN a third holding time period T6 included IN the holding phase, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is turned off, the potential of the first node P1 is maintained at the low level, the first control transistor T4 is turned on, the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4, the second control transistor T5 is turned on, so that the potential of the third node P3 is maintained lower than VGL + Vth, vth is a threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, and further the potential of the gate driving signal output by the output terminal OUT is maintained at the second voltage, that is, the low level, and is not affected by noise interference; the seventh control transistor T3 is turned off, the sixth control transistor T2 is turned on, the potential of the second node P2 is at a high level, the tenth control transistor T14 is turned on, the potential of the third control node P31 is at a high level, the eighth control transistor T6 is turned off, the potential of the second control node P21 is at a high level, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned on, the potential of the fourth node P4 is at a high level, and the ninth transistor T9 is turned off.

In the holding phase, the potential of the third node P1 may be maintained to be lower than VGL + Vth, where Vth is the threshold voltage of the output noise reduction transistor T10, so that the output noise reduction transistor T10 is turned on, and the potential of the gate driving signal output by the output end OUT is maintained to be the second voltage without being influenced by noise.

In the shift register unit shown in fig. 9-14, the first control transistor T4, the first control capacitor C4, and the second control transistor T5 form a charge pump structure, and the charge pump is a structure similar to a water pump in a circuit, and mainly realizes redistribution of charges and the purpose of boosting (or reducing) voltage through a capacitor, a clock signal, and a diode rectification structure (in fig. 9-14, the second control transistor T5 adopts a diode connection mode).

For example, as shown in fig. 15A, in the second operation stage S2, the driving method of the shift register unit includes at least one reset stage t7. Only 1 reset phase t7 is shown in fig. 15A, which is not limited by the embodiments of the present disclosure.

For example, in at least one reset period t7, an active level (e.g., a low level) of the total reset signal is applied to the total reset terminal RST, and an inactive level (e.g., a high level) of the first clock signal is applied to the first clock signal terminal CLK. The reset circuit 150 turns off the output noise reduction circuit 130 in response to the active level of the total reset signal.

For example, in the case that the shift register unit 10 further includes the second control circuit 160, the second control circuit 160 is connected to the first node P1, the third node P3 and the second clock signal terminal CB, and is configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB; the output noise reduction circuit 130 is further connected to the third node P3, and is configured to output an inactive level of the output signal at the output terminal OUT in response to a level of the third node P3; the reset phase t7 further comprises: the inactive level of the second clock signal is applied to the second clock signal terminal CB, and the reset circuit 150 resets the third node P3 in response to the active level of the total reset signal, so that the output noise reduction circuit 130 is turned off in response to the level of the third node P3.

As shown IN fig. 15A, during the reset period T7, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the total reset terminal RST provides a low level, the input transistor T1 is turned off, the potential of the first node P1 is maintained at a low level, the third control transistor T13 is turned on, the first control node P11 is at a low level, the first control transistor T4 is turned on IN response to the low level of the first control node P11, the potential of the input clock signal provided by the second clock signal terminal CB is raised, according to the principle of charge conservation of the first control capacitor C4, thereby raising the potential of the first control node P11, the second control transistor T5 is turned off, since the reset transistor T12 is turned on IN response to the low level of the total reset signal, the first voltage terminal VGH is connected to the third node P3, thereby raising the voltage of the third node P3, the output noise reduction transistor T10 is turned off, so that the output noise reduction transistor T10 is turned off during at least one reset period T7 of the second operation period S2, thereby the output noise reduction transistor T10 can be prevented from being turned on, thereby the output noise reduction transistor T10 can be used to improve the display quality of the display panel during the reset period S2, and the display quality of the display panel can be improved. At this stage, the sixth control transistor T2 is turned on, the seventh control transistor T3 is turned off, so that the second node P2 is connected to the first clock signal terminal CK, the potential of the second node P2 is at the high level of the first clock signal terminal CK, the tenth control transistor T14 is turned on, the potential of the third control node P31 is at the high level, the eighth control transistor T6 is turned off, the potential of the second control node P21 is maintained at the high level, the ninth control transistor T7 is turned off, the eighth control transistor T8 is turned on, the potential of the fourth node P4 is maintained at the high level, and the ninth transistor T9 is turned off.

It should be noted that the driving method of other circuits (e.g., the circuits shown in fig. 9-10 and 12-13) is similar to the driving method of the circuit shown in fig. 14, and reference may be made to the description of the driving method in fig. 14 and fig. 15A, which is not repeated herein.

Fig. 15B shows a signal timing chart when the shift register unit 10 shown in fig. 11 operates. Referring to fig. 15, the operation of the shift register unit shown in fig. 11 is similar to that of the shift register unit shown in fig. 14, except that: in the reset period T7, the fifth control transistor T15 is turned on in response to the high level of the reset signal, so that the first node P1 is connected to the first voltage terminal VGH, and thus the level of the first node P1 is a high level, and the third control transistor T13 is turned on, so that the first control node P11 is connected to the first node P1, and thus the level of the first control node P11 is a high level, and the rest of the processes may refer to the description of fig. 15A, and are not described herein again.

At least one embodiment of the present disclosure further provides a gate driving circuit 20, as shown in fig. 16, the gate driving circuit 20 includes a plurality of cascaded shift register units 10, where any one or more shift register units 10 may adopt the structure of the shift register unit 10 provided in any one of the embodiments of the present disclosure or a variation thereof.

At least one embodiment of the present disclosure further provides a display device 1, as shown in fig. 17, the display device 1 includes the gate driving circuit 20 provided in the embodiment of the present disclosure and a plurality of sub-pixel units 410 arranged in an array. For example, the display device 1 further includes a display panel 40, and a pixel array made up of a plurality of sub-pixel units 410 is provided in the display panel 40.

The output terminal OUT of each shift register unit 10 in the gate driving circuit 20 is electrically connected to the sub-pixel units 410 of one row, for example, the gate driving circuit 20 is electrically connected to the sub-pixel units 410 through the gate lines GL. The gate driving circuit 20 is used to provide driving signals to the pixel array, for example, the driving signals may drive the scan transistor and the sensing transistor in the sub-pixel unit 410.

For example, the display device 1 may further include a data driving circuit 30, and the data driving circuit 30 is configured to provide a data signal to the pixel array. For example, the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through the data line DL.

Note that, the display device 1 in the present embodiment may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator and the like.

The technical effects of the display device 1 provided by the embodiment of the present disclosure can refer to the corresponding descriptions about the gate driving circuit 20 in the above embodiments, and are not described herein again.

For the present disclosure, there are also several points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to general designs.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

A shift register cell comprising: the device comprises an input circuit, a first control circuit, an output noise reduction circuit and a reset circuit; wherein the content of the first and second substances,

the input circuit is connected with the input end and is configured to respond to an input signal input by the input end to control the level of the first node;

the first control circuit is connected with the first node, a second node and a first clock signal end and is configured to control the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal end;

the output circuit is connected with an output end and configured to output an output signal at the output end under the control of the level of the second node;

the output noise reduction circuit is connected with the output end and is configured to reduce noise of the output end under the control of the level of the first node;

the reset circuit is connected with a total reset terminal and a first voltage terminal and is configured to enable the output noise reduction circuit to be turned off in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is at an invalid level in a first operation stage and comprises at least one segment of valid level in a second operation stage.
The shift register cell of claim 1, further comprising a second control circuit, wherein,

the second control circuit is connected with the first node, a third node and a second clock signal end and is configured to control the level of the third node under the control of the level of the first node and a second clock signal provided by the second clock signal end;

the output noise reduction circuit is further coupled to the third node and configured to output an inactive level of the output signal at the output terminal in response to a level of the third node.
The shift register cell of claim 2, wherein the reset circuit is further coupled to the third node and configured to reset the third node in response to a global reset signal provided by the global reset terminal to turn off the output noise reduction circuit.
The shift register cell of claim 2 or 3, wherein the second control circuit comprises a first sub-circuit;

the first sub-circuit is connected to the first node, the second clock signal terminal, and the third node, and configured to control a level of the third node under control of a level of the first node.
The shift register cell of claim 4, wherein the second control circuit further comprises a second sub-circuit;

the second sub-circuit is connected with a second voltage terminal, the first node and a first control node, and is configured to control the level of the first control node in response to a second voltage provided by the second voltage terminal;

the first sub-circuit is also connected to the first control node and configured to control a level of the third node in response to a level of the first control node.
The shift register cell of any of claims 2-5, further comprising a third control circuit, wherein the third control circuit is coupled to the second node, a fourth node, and the second clock signal terminal and is configured to control a level of the fourth node under control of the level of the second node and a second clock signal provided by the second clock signal terminal.
The shift register cell of claim 6, wherein the third control circuit comprises a third sub-circuit and a fourth sub-circuit;

the third sub-circuit is connected with the second clock signal end and a second control node and is configured to control the level of the second control node under the control of the level of the second node;

the fourth sub-circuit is connected to the second clock signal terminal, the second control node, and the fourth node, and configured to control a level of the fourth node in response to a second clock signal provided from the second clock signal terminal.
The shift register cell of claim 7, wherein the third control circuit further comprises a fifth sub-circuit,

the fifth sub-circuit is connected to a second voltage terminal, the second node, and a third control node, and configured to control a level of the third control node in response to a second voltage provided from the second voltage terminal;

the third sub-circuit is further coupled to the third control node and configured to control a level of the second control node in response to a level of the third control node.
The shift register cell of claim 8, wherein the second control circuit further comprises a sixth sub-circuit,

the sixth sub-circuit is connected to the second control node, the first voltage terminal, and the first sub-circuit, and is configured to control a level of the first control node to be stable in response to a level of the second control node.
The shift register cell of any one of claims 7-9, further comprising a fourth control circuit, wherein the fourth control circuit is coupled to the first node, the first voltage terminal, and the fourth node, and is configured to control a level of the fourth node in response to a level of the first node.
The shift register cell of claim 8 or 9, further comprising a fifth control circuit, wherein the fifth control circuit is connected to the second control node, the third node and the first voltage terminal and configured to control a level of the third node in response to a level of the second control node.
The shift register cell of any one of claims 1-11, further comprising a sixth control circuit, wherein the sixth control circuit is coupled to the global reset terminal, the first voltage terminal, and the first node, and is configured to reset the first node under control of a reset signal provided by the global reset terminal.
The shift register cell of any of claims 1-12, wherein the input circuit comprises an input transistor,

the gate of the input transistor is coupled to the first clock signal terminal to receive the first clock signal, the first pole of the input transistor is coupled to the input terminal to receive the input signal, and the second pole of the input transistor is coupled to the first node.
The shift register cell of claim 3, wherein the reset circuit comprises a reset transistor,

the grid of the reset transistor is connected with the total reset end to receive the total reset signal, the first pole of the reset transistor is connected with the first voltage end to receive the first voltage, and the second pole of the reset transistor is connected with the third node.
The shift register cell of claim 3, wherein the output noise reduction circuit comprises an output noise reduction transistor,

the grid electrode of the output noise reduction transistor is connected with the third node, the first pole of the output noise reduction transistor is connected with the second voltage end to receive the second voltage, and the second pole of the output noise reduction transistor is connected with the output end.
The shift register cell of claim 15, wherein the output noise reduction circuit further comprises an output noise reduction capacitance,

the first pole of the output noise reduction capacitor is connected to the second voltage terminal to receive the second voltage, and the second pole of the output noise reduction capacitor is connected to the third node.
The shift register cell of any one of claims 2-16, wherein the output circuit comprises an output transistor and an output capacitor;

a gate of the output transistor is connected to the fourth node, a first pole of the output transistor is connected to the output terminal, and a second pole of the output transistor is connected to the first voltage terminal to receive a first voltage;

a first pole of the output capacitor is coupled to the fourth node, and a second pole of the output capacitor is coupled to the first voltage terminal to receive the first voltage.
The shift register cell of claim 9, wherein the first sub-circuit comprises a first control transistor, a second control transistor, and a first control capacitance;

a gate of the first control transistor is connected to the first control node, a first pole of the first control transistor is connected to the second clock signal terminal to receive the second clock signal, and a second pole of the first control transistor is connected to the first pole of the first control capacitor;

a second pole of the first control capacitor is connected with the first control node;

the gate and the first pole of the second control transistor are connected to each other and both connected to the first control node, and the second pole of the second control transistor is connected to the third node.
The shift register cell of claim 18, wherein the second sub-circuit comprises a third control transistor,

the gate of the third control transistor is connected to the second voltage terminal, the first pole of the third control transistor is connected to the first node, and the second pole of the third control transistor is connected to the first control node.
The shift register cell of claim 18 or 19, wherein the sixth sub-circuit comprises a fourth control transistor;

a gate of the fourth control transistor is connected to the second control node, a first pole of the fourth control transistor is connected to the first voltage terminal to receive the first voltage, and a second pole of the fourth control transistor is connected to the first pole of the first control capacitor.
The shift register cell of claim 12, wherein the sixth control circuit comprises a fifth control transistor;

a gate of the fifth control transistor is coupled to the total reset terminal to receive the total reset signal, a first pole of the fifth control transistor is coupled to the first voltage terminal to receive a first voltage, and a second pole of the fifth control transistor is coupled to the first node.
The shift register cell of any one of claims 1-21, wherein the first control circuit comprises a sixth control transistor and a seventh control transistor;

a gate of the sixth control transistor is connected to the first node, a first pole of the sixth control transistor is connected to the first clock signal terminal to receive the first clock signal, and a second pole of the sixth control transistor is connected to the second node;

a gate of the seventh control transistor is coupled to the first clock signal terminal to receive the first clock signal, a first pole of the seventh control transistor is coupled to the second voltage terminal to receive the second voltage, and a second pole of the seventh control transistor is coupled to the second node.
The shift register cell of claim 9, wherein the third sub-circuit comprises an eighth control transistor and a third control capacitance, the fourth sub-circuit comprises a ninth control transistor, and the fifth sub-circuit comprises a tenth control transistor;

a gate of the tenth control transistor is connected to the second voltage terminal to receive the second voltage, a first pole of the tenth control transistor is connected to the second node, and a second pole of the tenth control transistor is connected to the third control node;

a first pole of the third control capacitor is connected to the third control node, and a second pole of the third control capacitor is connected to the second control node;

a gate of the eighth control transistor is connected to the third control node, a first pole of the eighth control transistor is connected to the second clock signal terminal to receive the second clock signal, and a second pole of the eighth control transistor is connected to the second control node;

the gate of the ninth control transistor is connected to the second clock signal terminal to receive the second clock signal, the first pole of the ninth control transistor is connected to the second control node, and the second pole of the ninth control transistor is connected to the fourth node.
The shift register cell of claim 10, wherein the fourth control circuit comprises an eleventh control transistor,

a gate of the eleventh control transistor is coupled to the first node, a first pole of the eleventh control transistor is coupled to the fourth node, and a second pole of the eleventh control transistor is coupled to the first voltage terminal to receive a first voltage.
The shift register cell of claim 11, wherein the fifth control circuit comprises a twelfth control transistor,

a gate of the twelfth control transistor is connected to the second control node, a first pole of the twelfth control transistor is connected to the third node, and a second pole of the twelfth control transistor is connected to the first voltage terminal to receive the first voltage.
A gate drive circuit comprising a plurality of cascaded shift register cells as claimed in any one of claims 1 to 25.
A driving method of the shift register unit according to claim 1, comprising a first operation phase and a second operation phase;

wherein, in the first operation phase, the driving method comprises a first sub-phase, a second sub-phase and a third sub-phase:

in the first sub-phase, the input circuit controls the level of a first node in response to the effective level of the input signal input by the input end;

the first control circuit controls the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal terminal;

in the second sub-phase, the output circuit outputs an output signal at the output terminal under the control of the level of the second node;

in the third sub-stage, the output noise reduction circuit reduces noise of the output end under the control of the level of the first node;

in the second operating phase, the driving method comprises at least one reset phase,

applying an active level of a total reset signal to the total reset terminal, an inactive level of the first clock signal to the first clock signal terminal during the at least one reset phase,

the reset circuit turns off the output noise reduction circuit in response to an active level of the total reset signal.
The driving method according to claim 27, wherein in a case where the shift register unit further includes a second control circuit, wherein the second control circuit is connected to the first node, a third node, and a second clock signal terminal, and is configured to control a level of the third node under control of the level of the first node and a second clock signal provided from the second clock signal terminal;

the output noise reduction circuit is further coupled to the third node and configured to output an inactive level of the output signal at the output terminal in response to a level of the third node;

the reset phase further comprises: applying an inactive level of the second clock signal to the second clock signal terminal,

the reset circuit resets the third node in response to an active level of the total reset signal, so that the output noise reduction circuit is turned off in response to a level of the third node.
A display device comprising the gate driver circuit as claimed in claim 26.