CN102968950B - Shifting register unit and array substrate gate drive device - Google Patents
Shifting register unit and array substrate gate drive device Download PDFInfo
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- CN102968950B CN102968950B CN201210443861.8A CN201210443861A CN102968950B CN 102968950 B CN102968950 B CN 102968950B CN 201210443861 A CN201210443861 A CN 201210443861A CN 102968950 B CN102968950 B CN 102968950B
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Abstract
The invention discloses a shifting register unit and an array substrate gate drive device which are used for inhibiting output errors caused by drifting of self threshold voltage of elements and interference of adjacent elements and improving the stability of a shifting register. The shifting register unit comprises an input module providing an input signal to an output terminal, an output module providing a first clock signal to the output terminal, a pull-down control module providing a second clock signal to a second node and a third node and providing power supply negative electrode voltage to the third node, a pull-down module providing the power supply negative electrode voltage to a reset signal end, and a reset module providing the power supply negative electrode voltage to a first node and the output terminal.
Description
Technical field
The present invention relates to liquid crystal technology field, particularly relate to a kind of shift register cell and array substrate gate drive device.
Background technology
Thin Film Transistor-LCD TFT-LCD driver mainly comprises gate drivers and data driver, and wherein, gate drivers is added on the grid line of display panels after the clock signal of input being changed by shift register.Gate driver circuit has same process with the formation of TFT and is formed on the lcd panel together with TFT simultaneously.Gate driver circuit comprises and has multistage shift register.Every grade is all connected to corresponding gate line to export gate drive signal.The at different levels of gate driver circuit are connected with each other, start signal input at different levels in the first order and order export gate drive signal to gate line, wherein the input end of prime is connected to the output terminal of upper level, and the output terminal of next stage is connected to the control end of prime.
Arrange the gate driver circuit of said structure on the right side of LCD, its every one-level comprises structure as shown in Figure 1.But, because the drift of self threshold voltage of transistor in gate driver circuit and the interference of adjacent transistor may cause shift register signal output error and its shelf-life to decline.
Summary of the invention
Embodiments provide a kind of shift register cell and array substrate gate drive device, in order to suppress the output error caused by the drift of element self threshold voltage and the interference of adjacent elements, improve the stability of shift register.
A kind of shift register cell that the embodiment of the present invention provides, load module, output module, drop-down control module, drop-down module and reseting module, wherein,
Described load module, connects input signal end, in response to input signal, input signal is supplied to lead-out terminal;
Described output module is connected to the first node being positioned at load module, for the voltage in response to first node, the first clock signal is supplied to lead-out terminal;
Described drop-down control module, for in response to second clock signal, second clock signal is exported to the 3rd node being positioned at this drop-down control module by the Section Point being positioned at this drop-down control module, and in response to the voltage of first node, power cathode voltage is exported by the 3rd node;
Described drop-down module, for the voltage in response to the first clock signal and first node, is supplied to reset signal end by power cathode voltage;
Described reseting module, for power cathode voltage being supplied to first node in response to the voltage of reset signal and the 3rd node, and is supplied to lead-out terminal in response to second clock signal by power cathode voltage.
A kind of array substrate gate drive device that the embodiment of the present invention provides, comprise the shift register cells at different levels of cascade, wherein, the input signal end of first order shift register cell connects start signal end, and the reset signal end of first order shift register cell connects the lead-out terminal of second level shift register cell; The input signal end of afterbody shift register cell connects the lead-out terminal of previous stage shift register cell, and the reset signal end of afterbody shift register cell connects start signal end; Except the first order and afterbody shift register cell, the input signal end of all the other shift register cells at different levels connects the lead-out terminal of upper level shift register cell, and reset signal end connects the lead-out terminal of next stage shift register cell;
The shift register cell of all above-mentioned cascades is shift register cell provided by the invention.
Embodiments provide a kind of shift register cell and array substrate gate drive device, this shift register adds noise-reducing design on the basis of original signal transfer function, inhibit the output error caused by the drift of the threshold voltage of element self and the interference of adjacent elements, improve the output characteristics of shift register and the serviceable life of transistor further.
Accompanying drawing explanation
Fig. 1 is the structural representation of shift register cell elementary cell in prior art;
The structural representation of a kind of shift register cell that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of array substrate gate drive device that Fig. 3 provides for the embodiment of the present invention;
The clock signal figure of each signal end of a kind of shift register cell that Fig. 4 provides for the embodiment of the present invention.
Embodiment
Embodiments provide a kind of shift register cell and array substrate gate drive device, in order to suppress the output error caused by the drift of element self threshold voltage and the interference of adjacent elements, improve the stability of shift register.
Below in conjunction with accompanying drawing, the present invention will be described.
As shown in Figure 2, a kind of shift register cell that the embodiment of the present invention provides, comprising: load module 101, output module 102, drop-down control module 103, drop-down module 104 and reseting module 105, wherein,
Described load module 101, connects input signal end, in response to input signal, input signal is supplied to lead-out terminal;
Described output module 102 is connected to first node, for the voltage in response to first node, the first clock signal is supplied to lead-out terminal;
Described drop-down control module 103, for in response to second clock signal, second clock signal is exported to the 3rd node being positioned at this drop-down control module by the Section Point being positioned at this drop-down control module, and in response to the voltage of first node, power cathode voltage is exported by the 3rd node;
Described drop-down module 104, for the voltage in response to the first clock signal and first node, is supplied to reset signal end by power cathode voltage;
Described reseting module 105, for power cathode voltage being supplied to first node in response to the voltage of reset signal and the 3rd node, and is supplied to lead-out terminal in response to second clock signal by power cathode voltage.
Below in conjunction with specific embodiment, the present invention is described in detail.It should be noted that, be to better explain the present invention in the present embodiment, but do not limit the present invention.
Shift register cell as shown in Figure 1, comprise load module 101, output module 102, drop-down control module 103, drop-down module 104 and reseting module 105, wherein each module comprises each element accordingly, particularly,
Described load module 101, comprising:
The first film transistor M1, its source electrode is connected input signal end INPUT with grid, drain electrode connects first node P1.
Described output module 102, comprising:
Second thin film transistor (TFT) M2, its source electrode connects the first clock signal terminal CLK, and grid connects first node P1, and drain electrode connects lead-out terminal OUTPUT;
Electric capacity, its first end connects first node P1, and the second end connects lead-out terminal OUTPUT.
Described drop-down control module 103, comprising:
3rd thin film transistor (TFT) M3, its source electrode is connected second clock signal end CLKB with grid, drain as Section Point P2;
4th thin film transistor (TFT) M4, its source electrode connects second clock signal end CLKB, and grid connects Section Point P2, drains as the 3rd node P3;
5th thin film transistor (TFT) M5, its source electrode connects the 3rd node P3, and grid connects first node P1, and drain electrode connects power cathode voltage end VSS;
6th thin film transistor (TFT) M6, its source electrode connects Section Point P2, and grid connects first node P1, and drain electrode connects power cathode voltage end VSS.
Described drop-down module 104, comprising:
7th thin film transistor (TFT) M7, its source electrode connects reset signal end RESET, and grid connects first node P1, and drain electrode connects power cathode voltage end VSS;
8th thin film transistor (TFT) M8, its source electrode connects reset signal end RESET, and grid connects the first clock signal terminal CLK, connects power cathode voltage end VSS.
Described reseting module 105, comprising:
9th thin film transistor (TFT) M9, its source electrode connects first node P1, and grid connects reset signal end RESET, and drain electrode connects power cathode voltage end VSS;
Tenth thin film transistor (TFT) M10, its source electrode connects lead-out terminal OUTPUT, and grid connects second clock signal end CLKB, and drain electrode connects power cathode voltage end VSS;
11 thin film transistor (TFT) M11, its source electrode connects first node P1, and grid connects the 3rd node P3, and drain electrode connects power cathode voltage end VSS.
Preferably, above-mentioned all thin film transistor (TFT)s are N-type TFT TFT.
The above-mentioned shift register cell that the embodiment of the present invention provides, on the basis of existing technology, add noise-reducing design, restrained effectively the output error because the drift of transistor self threshold voltage and the interference of adjacent transistor cause, and improve the output characteristics of shift register and the serviceable life of transistor further.
Above-mentioned shift register cell cascade forms array base palte gate driver circuit, a kind of array substrate gate drive device that the embodiment of the present invention provides, comprise the shift register cells at different levels of cascade, wherein, the input signal end of first order shift register cell connects start signal end, and the reset signal end of first order shift register cell connects the lead-out terminal of second level shift register cell; The input signal end of afterbody shift register cell connects the lead-out terminal of previous stage shift register cell, and the reset signal end of afterbody shift register cell connects start signal end; Except the first order and afterbody shift register cell, the input signal end of all the other shift register cells at different levels connects the lead-out terminal of upper level shift register cell, and reset signal end connects the lead-out terminal of next stage shift register cell;
The shift register cell of all above-mentioned cascades is above-mentioned shift register cell.
Particularly, this array base palte gate driver circuit comprises N level, wherein N is grid line quantity, see Fig. 3, start signal STV is input to first order shift register as input signal, and order export gate drive signal to gate line, the input signal of n-th grade is provided by the output signal of (n-1)th grade, wherein n<N, reset signal is provided by the output signal of (n+1)th grade, the reset signal of N level is provided by the input signal of the first order and start signal STV, that is start signal STV mono-aspect is as the input signal of the first order, on the other hand as the reset signal of N level.
Below in conjunction with the sequential chart of each signal end shown in Fig. 4, the n-th (n<N in the array base palte gate driver circuit that the embodiment of the present invention is provided, N is the progression of array base palte grid circuit) method of work of level shift register cell is described, wherein, all TFT are high level conducting, and low level is ended.
First stage T1: clock signal clk is low level, second clock signal CLKB is high level, prime output signal G(n-1 as input signal) be high level, the subordinate output signal G(n+1 as reset signal) be low level, VSS is low level signal.The input signal G (n-1) of high level makes transistor M1 conducting and charges to electric capacity C1, cause P1 point to be high level, now transistor M2 gate switch is opened, but due to now clock signal clk be low level, M2 does not have conducting, output terminal G(n) output low level;
In this T1 stage, because second clock signal CLKB is high level, transistor M10 switch opens, constantly to output terminal G(n) put process of making an uproar, prevent the output error that may be caused by the drift of transistor self threshold voltage and the interference etc. of adjacent transistor, second clock signal CLKB is that high level makes transistor M3 conducting simultaneously, and P2 point is high level.By the breadth length ratio of design transistor M4 and M5, can obtain when P1 point and P2 point are simultaneously for high level, P3 point is low level.Transistor M11 affects by P3 point low level and is in cut-off state, and the transistor M3 gate switch preventing electric capacity C1 to leak electricity to cause is closed.In addition because P1 point is high level, transistor M7 gate switch is opened, to subordinate output signal G(n+1) put process of making an uproar, prevent because subordinate outputs signal G(n+1) noise at place causes P1 point to discharge;
Wherein, breadth length ratio must reach certain requirement could realize effect herein, but is not identical for the breadth length ratio that the panel product of different size requires, and differs greatly;
Subordinate phase T2: clock signal clk is high level, second clock signal CLKB is low level, input signal G(n-1) be low level, reset signal G(n+1) be low level.Now transistor M2 conducting, M4 ends, output terminal G(n) export high level;
In this T2 stage, because clock signal clk and P1 point are high level, transistor M7 and M8 gate switch are all opened, the two is simultaneously to subordinate output signal G(n+1) put process of making an uproar, preventing due to subordinate output signal G(n+1) noise at place causes P1 point to discharge, and then cause transistor M2 to end, output error.Because second clock signal CLKB is low level, transistor M10 ends, and effectively prevents output terminal G(n) output error caused of leaking electricity.In addition second clock signal CLKB is that low level also makes transistor M3 and M4 end, P3 point is low level, transistor M11 affects by P3 point low level and is in cut-off state, prevents electric capacity C1 from leaking electricity and causes transistor M2 end and finally cause output terminal G(n) output error;
Wherein, in cycle T 1 and T2, because P1 point is always high level, transistor M5 gate switch is in conducting state always, constantly process of making an uproar is put to P3 point, make P3 point be always low level in cycle T 1 and T2, ensure that transistor M11 is during this period of time in cut-off state, effectively prevent the conducting of transistor M11 from electric capacity C1 may be caused to leak electricity;
Phase III T3: clock signal clk is low level, second clock signal CLKB is high level, input signal G(n-1) be low level, reset signal G(n+1) be high level.Now transistor M9 conducting, electric capacity C1 makes rapidly P1 point reduce to low level by transistor M9 electric discharge, and transistor M2 ends.Because second clock signal CLKB is high level, transistor M10 conducting, to output terminal G(n) carry out rapid discharge and make to export as low level, achieve reset function;
Fourth stage T4: clock signal clk is high level, second clock signal CLKB low level, input signal G(n-1) be low level, reset signal G(n+1) be low level.Now transistor M1 ends, and P1 point is low level, and transistor M2 ends, output terminal G(n) output low level;
In this T4 stage, because clock signal clk is high level, the conducting of transistor M8 gate switch, constantly to reset signal G(n+1) put process of making an uproar, prevent from causing the gate switch of transistor M9 to be in conducting state all the time by the drift of transistor self threshold voltage and the interference etc. of adjacent transistor, cause electric capacity C1 to leak electricity at next frame signal temporarily, reduce the switch opening times of transistor M2.
Five-stage T5: clock signal clk is low level, second clock signal CLKB high level, input signal G(n-1) be low level, reset signal G(n+1) be low level.Now transistor M1 ends, and P1 point is low level, and transistor M2 ends, output terminal G(n) output low level;
In this T5 stage, because second clock signal CLKB is high level, transistor M10 gate switch is opened, constantly to output terminal G(n) put process of making an uproar, prevent the mistake that may be caused by the drift of transistor self threshold voltage and the interference etc. of adjacent transistor from exporting, second clock signal CLKB is that high level makes transistor M3 and M4 conducting simultaneously, transistor M5 ends due to P1 point low level, therefore P3 point is high level, transistor M11 gate switch is opened, constantly the noise of P1 point is put and make an uproar, P1 spot noise is effectively prevented to charge to electric capacity C1, finally cause transistor M2 conducting and run into output error when clock signal clk is high level when next time.
Preferably, before next frame signal arrives, along with the cyclical variation of two clock signal clks and CLKB, transistor M10, M11 and M8 are constantly to P1 node, P3 node and output terminal G(n) put process of making an uproar, prevent the mistake that may be caused by the drift of transistor self threshold voltage and the interference etc. of adjacent transistor from exporting, ensure the Stability and veracity exported.
In sum, embodiments provide a kind of shift register cell and array base palte gate driver circuit, this shift register cell adds unique noise-reducing design on the basis of original signal transfer function, effectively inhibit the output error that may be caused by the drift of transistor self threshold voltage and the interference etc. of adjacent transistor, and improve the signal output characteristics of shift register and the serviceable life of transistor further.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a shift register cell, is characterized in that, this shift register cell comprises load module, output module, drop-down control module, drop-down module and reseting module, wherein,
Described load module, connects input signal end, in response to input signal, input signal is supplied to lead-out terminal;
Described output module is connected to the first node being positioned at load module, for the voltage in response to first node, the first clock signal is supplied to lead-out terminal;
Described drop-down control module, for in response to second clock signal, second clock signal is exported to the 3rd node being positioned at this drop-down control module by the Section Point being positioned at this drop-down control module, and in response to the voltage of first node, power cathode voltage is exported by the 3rd node;
Described drop-down module, for the voltage in response to the first clock signal and first node, is supplied to reset signal end by power cathode voltage;
Described reseting module, for the voltage in response to reset signal and the 3rd node, is supplied to first node by power cathode voltage, and in response to second clock signal, power cathode voltage is supplied to lead-out terminal;
Wherein, described drop-down module, comprising:
7th thin film transistor (TFT), its source electrode connects reset signal end, and grid connects first node, and drain electrode connects power cathode voltage end;
8th thin film transistor (TFT), its source electrode connects reset signal end, and grid connects the first clock signal terminal, and drain electrode connects power cathode voltage end.
2. shift register cell according to claim 1, is characterized in that, described load module, comprising:
The first film transistor, its source electrode is connected input signal end with grid, and drain electrode connects first node.
3. shift register cell according to claim 1, is characterized in that, described output module, comprising:
Second thin film transistor (TFT), its source electrode connects the first clock signal terminal, and grid connects first node, and drain electrode connects lead-out terminal;
Electric capacity, its first end connects first node, and the second end connects lead-out terminal.
4. shift register cell according to claim 1, is characterized in that, described drop-down control module, comprising:
3rd thin film transistor (TFT), its source electrode is connected second clock signal end with grid, drains as Section Point;
4th thin film transistor (TFT), its source electrode connects second clock signal end, and grid connects Section Point, drains as the 3rd node;
5th thin film transistor (TFT), its source electrode connects the 3rd node, and grid connects first node, and drain electrode connects power cathode voltage end;
6th thin film transistor (TFT), its source electrode connects Section Point, and grid connects first node, and drain electrode connects power cathode voltage end.
5. shift register cell according to claim 1, is characterized in that, described reseting module, comprising:
9th thin film transistor (TFT), its source electrode connects first node, and grid connects reset signal end, and drain electrode connects power cathode voltage end;
Tenth thin film transistor (TFT), its source electrode connects lead-out terminal, and grid connects second clock signal end, and drain electrode connects power cathode voltage end;
11 thin film transistor (TFT), its source electrode connects first node, and grid connects the 3rd node, and drain electrode connects power cathode voltage end.
6. the shift register cell according to the arbitrary claim of Claims 1 to 5, is characterized in that, all thin film transistor (TFT)s are N-type TFT TFT.
7. an array substrate gate drive device, comprise the shift register cells at different levels of cascade, wherein, the input signal end of first order shift register cell connects start signal end, and the reset signal end of first order shift register cell connects the lead-out terminal of second level shift register cell; The input signal end of afterbody shift register cell connects the lead-out terminal of previous stage shift register cell, and the reset signal end of afterbody shift register cell connects start signal end; Except the first order and afterbody shift register cell, the input signal end of all the other shift register cells at different levels connects the lead-out terminal of upper level shift register cell, and reset signal end connects the lead-out terminal of next stage shift register cell; It is characterized in that, the shift register cell of all cascades is the shift register cell as described in claim as arbitrary in claim 1-6.
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| CN103390392B (en) | 2013-07-18 | 2016-02-24 | 合肥京东方光电科技有限公司 | GOA circuit, array base palte, display device and driving method |
| CN103456365A (en) * | 2013-08-30 | 2013-12-18 | 合肥京东方光电科技有限公司 | Shift register unit, shift register and display device |
| TWI517134B (en) * | 2014-05-06 | 2016-01-11 | 友達光電股份有限公司 | Scan circuit and shift register |
| CN104732950B (en) * | 2015-04-20 | 2017-03-29 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit and display device |
| CN105528986B (en) | 2016-02-03 | 2018-06-01 | 京东方科技集团股份有限公司 | Denoising method, denoising device, gate driving circuit and display device |
| CN108417183B (en) * | 2017-02-10 | 2020-07-03 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate drive circuit and display device |
| CN106920526B (en) | 2017-05-04 | 2020-02-14 | 合肥鑫晟光电科技有限公司 | Shift register and driving method thereof and grid driving circuit |
| CN108231028B (en) * | 2018-01-22 | 2019-11-22 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and its driving method, display device |
| CN109244669B (en) * | 2018-10-26 | 2023-12-19 | 北京华镁钛科技有限公司 | Driving system, driving method and antenna device of reconfigurable phased array antenna |
| CN109448656B (en) * | 2018-12-26 | 2021-01-26 | 惠科股份有限公司 | Shift register and gate drive circuit |
| CN114187873B (en) * | 2021-12-10 | 2023-05-30 | 武汉华星光电技术有限公司 | Gate driving circuit and display device |
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