CN110728943A - Noise reduction circuit, shift register unit, gate drive circuit and display device - Google Patents

Noise reduction circuit, shift register unit, gate drive circuit and display device Download PDF

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Publication number
CN110728943A
CN110728943A CN201911044189.3A CN201911044189A CN110728943A CN 110728943 A CN110728943 A CN 110728943A CN 201911044189 A CN201911044189 A CN 201911044189A CN 110728943 A CN110728943 A CN 110728943A
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China
Prior art keywords
noise reduction
shift register
clock signal
register unit
stage shift
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CN201911044189.3A
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Chinese (zh)
Inventor
王俊伟
陈维涛
崔晓鹏
张慧
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to CN201911044189.3A priority Critical patent/CN110728943A/en
Publication of CN110728943A publication Critical patent/CN110728943A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention provides a noise reduction circuit, a shift register unit, a gate drive circuit and a display device. The noise reduction circuit comprises a first noise reduction circuit and/or a second noise reduction circuit; the first noise reduction circuit controls the noise reduction of the grid drive signal output end under the control of a first noise reduction control signal provided by the first noise reduction control end; and the second noise reduction circuit controls the pull-up node to reduce noise under the control of a second noise reduction control signal provided by the second noise reduction control end. The invention can avoid the output time period, and can perform full-time noise reduction on the output end of the gate driving signal and/or the pull-up node, thereby improving the output stability of the gate driving signal.

Description

Noise reduction circuit, shift register unit, gate drive circuit and display device
Technical Field
The invention relates to the technical field of display, in particular to a noise reduction circuit, a shift register unit, a gate drive circuit and a display device.
Background
In the related art, due to the inherent characteristics of a TFT (thin film transistor) device, the TFT characteristics may drift with long-term reliability or under some specific use conditions, so that even though a gate of an output transistor included in a shift register unit maintains a good off-state voltage, the gate of the output transistor cannot maintain a good off-state characteristic, that is, in an output off-state maintaining period, the output transistor may be turned on, thereby causing noise interference to a gate driving signal output terminal when a clock signal provided by a clock signal terminal is at a high level in the output off-state maintaining period, causing picture mischarging and generating AD (abnormal display). In addition, the potential of the pull-up node can be prevented from being maintained at a low level due to characteristic drift of a transistor for controlling noise reduction in the output off-hold stage, so that noise interference can be generated on the output end of the gate driving signal.
Disclosure of Invention
The invention mainly aims to provide a noise reduction circuit, a shift register unit, a gate drive circuit and a display device, and solves the problem that noise interference is generated on a gate drive signal output end due to the fact that noise cannot be sufficiently reduced on the gate drive signal output end and/or a pull-up node in the prior art.
In order to achieve the above object, the present invention provides a noise reduction circuit for reducing noise at a gate driving signal output terminal included in a shift register unit and/or a pull-up node included in the shift register unit, the noise reduction circuit including a first noise reduction circuit and/or a second noise reduction circuit;
the first noise reduction circuit is respectively electrically connected with the gate drive signal output end and the first noise reduction control end and is used for controlling noise reduction of the gate drive signal output end under the control of a first noise reduction control signal provided by the first noise reduction control end;
the second noise reduction circuit is respectively electrically connected with the pull-up node and the second noise reduction control end and is used for controlling noise reduction of the pull-up node under the control of a second noise reduction control signal provided by the second noise reduction control end;
the potential of the first noise reduction control signal is an invalid voltage in an output period of the shift register unit, and the potential of the first noise reduction control signal is an effective voltage for at least part of the time in a period other than the output period included in a display period;
the potential of the second noise reduction control signal is an inactive voltage in an input period and an output period of the shift register unit, and the potential of the second noise reduction control signal is an active voltage for at least part of a period included in a display period other than the input period and the output period.
In practice, the first noise reduction circuit includes a first noise reduction transistor and at least one first noise reduction diode;
the anode of the first noise reduction diode is electrically connected with the first noise reduction control end, and the cathode of the first noise reduction diode is electrically connected with the control electrode of the first noise reduction transistor;
the first electrode of the first noise reduction transistor is electrically connected with the grid drive signal output end, and the second electrode of the first noise reduction transistor is electrically connected with the first noise reduction voltage end.
In practice, the second noise reduction circuit includes a second noise reduction transistor and at least one second noise reduction diode;
the anode of the second noise reduction diode is electrically connected with the second noise reduction control end, and the cathode of the second noise reduction diode is electrically connected with the control electrode of the second noise reduction transistor;
and the first pole of the second noise reduction transistor is electrically connected with the pull-up node, and the second pole of the second noise reduction transistor is electrically connected with a second noise reduction voltage end.
When the method is implemented, the number of the first noise reduction control ends is at least one;
the first noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the first noise reduction control end comprises at least one of other clock signal ends connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
When the method is implemented, the number of the second noise reduction control ends is at least one;
the second noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the second noise reduction control terminal comprises at least one of other clock signal terminals connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
The invention also provides a shift register unit which comprises the noise reduction circuit.
The invention also provides a grid driving circuit which comprises the multistage shift register unit.
In practice, the gate driving circuit of the present invention further includes a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-1) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit and the shift register unit of the N-1 th stage, which are included in the grid drive circuit; and/or the second noise reduction control terminal comprises the second clock signal terminal.
In practice, the gate driving circuit of the present invention further includes a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit; n is equal to 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid driving circuit; and/or the second noise reduction control terminal comprises the second clock signal terminal.
In practice, the gate driving circuit of the present invention further includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-2) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2N) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; n is an integer, N +2N is greater than 0;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; m is an integer, m is not equal to-1, and N +2m is greater than 0.
In practice, the gate driving circuit of the present invention further includes a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit; n is equal to 1 or 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; a is a positive integer;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control terminal comprises the third clock signal terminal.
The invention also provides a display device which comprises the grid drive circuit.
Compared with the prior art, the noise reduction circuit, the shift register unit, the gate drive circuit and the display device can avoid an output time period, carry out full-time noise reduction on the output end of the gate drive signal and/or the pull-up node, and improve the output stability of the gate drive signal.
Drawings
FIG. 1 is a block diagram of a noise reduction circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a noise reduction circuit according to another embodiment of the present invention;
FIG. 3 is a block diagram of a noise reduction circuit according to yet another embodiment of the present invention;
FIG. 4 is a circuit diagram of a noise reduction circuit according to yet another embodiment of the present invention;
FIG. 5 is a circuit diagram of a noise reduction circuit according to another embodiment of the present invention;
FIG. 6 is a circuit diagram of a noise reduction circuit according to yet another embodiment of the present invention;
FIG. 7 is a circuit diagram of a noise reduction circuit according to yet another embodiment of the present invention;
fig. 8 is a waveform diagram of the first clock signal CLK1, a waveform diagram of the second clock signal CLK2, a waveform diagram of the third clock signal CLK3, and a waveform diagram of the fourth clock signal CLK 4;
FIG. 9 is a block diagram of a first embodiment of a shift register cell according to the present invention;
FIG. 10 is a block diagram of a second embodiment of a shift register cell according to the present invention;
FIG. 11 is a timing diagram illustrating the operation of the shift register unit of FIG. 10 according to the second embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The switching tubes adopted in all the embodiments of the invention can be triodes, thin film switching tubes or field effect tubes or other devices with the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the switch except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In actual operation, when the switching tube is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In actual operation, when the switch tube is a thin film switch tube or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The noise reduction circuit provided by the embodiment of the invention is used for reducing noise of a grid driving signal output end included by a shift register unit and/or a pull-up node included by the shift register unit, and comprises a first noise reduction circuit and/or a second noise reduction circuit;
the first noise reduction circuit is respectively electrically connected with the gate drive signal output end and the first noise reduction control end and is used for controlling noise reduction of the gate drive signal output end under the control of a first noise reduction control signal provided by the first noise reduction control end;
the second noise reduction circuit is respectively electrically connected with the pull-up node and the second noise reduction control end and is used for controlling noise reduction of the pull-up node under the control of a second noise reduction control signal provided by the second noise reduction control end;
the potential of the first noise reduction control signal is an invalid voltage in an output period of the shift register unit, and the potential of the first noise reduction control signal is an effective voltage for at least part of the time in a period other than the output period included in a display period;
the potential of the second noise reduction control signal is an inactive voltage in an input period and an output period of the shift register unit, and the potential of the second noise reduction control signal is an active voltage for at least part of a period included in a display period other than the input period and the output period.
The noise reduction circuit provided by the embodiment of the invention can avoid the output time period, carry out full-time noise reduction on the output end of the gate drive signal and/or the pull-up node, and improve the output stability of the gate drive signal.
In the related art, the display period includes an input period, an output period, a reset period, and an output off-hold period, which are sequentially set, and when the shift register unit normally operates, that is, when there is no transistor characteristic drift,
in the input time period, the potential of a pull-up node is boosted through an input signal provided by an input end;
in an output time period, the electric potential of a pull-up node is boosted through bootstrap of a storage capacitor, and meanwhile, a clock signal provided by a clock signal end is at a high level, and an output transistor is conducted under the control of the electric potential of the pull-up node so as to control a grid electrode driving signal output end to output the high level;
in the reset stage, the potential of the pull-up node is reset through a reset signal provided by a reset end, the potential of the pull-down node is pulled up, and the grid driving signal reset transistor controls the grid driving signal provided by the grid driving signal output end to be reset under the control of the potential of the pull-down node;
in the output off hold period, the potential of the pull-up node is maintained at a low level, the potential of the pull-down node is at a high level for at least a part of the time, and the potential of the gate driving signal is maintained at a low level.
The control electrode of the output transistor may be electrically connected to the pull-up node, the first electrode of the output transistor may be electrically connected to the clock signal terminal, and the second electrode of the output transistor may be electrically connected to the gate driving signal output terminal, but not limited thereto.
However, in the related art, due to the inherent characteristics of a TFT (thin film transistor) device, the TFT characteristics may drift over a long term reliability or under some specific use conditions, and thus the gate of the output transistor included in the shift register unit may not maintain a good off-characteristic even though a good off-voltage is maintained, that is, the output transistor may be turned on during the output off-holding period, so that when the clock signal provided by the clock signal terminal is at a high level during the output off-holding period, noise interference may be generated on the gate driving signal output terminal, and a picture may be erroneously charged, thereby generating an AD.
Accordingly, embodiments of the present invention provide a noise reduction circuit to maintain the potential of the gate driving signal and/or the potential of the pull-up node at a low level during the output off hold period, so as to prevent noise interference from occurring at the output terminal of the gate driving signal and improve reliability.
As shown in fig. 1, the noise reduction circuit according to the embodiment of the present invention is configured to reduce noise at a gate driving signal Output terminal included in a shift register unit, where the noise reduction circuit includes a first noise reduction circuit 11;
the first noise reduction circuit 11 is electrically connected to the gate driving signal Output terminal Output and the first noise reduction control terminal Ctrl1, respectively, and is configured to control noise reduction of the gate driving signal Output terminal Output under the control of the first noise reduction control signal provided by the first noise reduction control terminal Ctrl 1;
the potential of the first noise reduction control signal is an invalid voltage in an output period of the shift register unit, and the potential of the first noise reduction control signal is an effective voltage for at least part of the time in a period other than the output period included in a display period.
In the noise reduction circuit according to the embodiment of the present invention, the potential of the first noise reduction control signal is set to be an invalid voltage in the output time period so as not to affect the output of the gate driving signal; and displaying at least part of the time periods included in the period except the Output time period, and setting the potential of the first noise reduction control signal to be effective voltage so as to control the noise reduction of the Output.
In this embodiment of the present invention, when the potential of the first noise reduction control signal is an effective voltage, the first noise reduction circuit 11 performs noise reduction on Output;
when the potential of the first noise reduction control signal is an invalid voltage, the first noise reduction circuit 11 does not reduce the noise of the Output.
In the embodiment of the present invention, when the first noise reduction transistor included in the first noise reduction circuit 11 is an n-type transistor, the effective voltage may be a high voltage, and the invalid voltage may be a low voltage, but not limited thereto.
As shown in fig. 2, the noise reduction circuit according to the embodiment of the present invention is configured to reduce noise of a pull-up node PU included in a shift register unit, where the noise reduction circuit includes a second noise reduction circuit 12;
the second noise reduction circuit 12 is electrically connected to the pull-up node PU and the second noise reduction control terminal Ctrl2, respectively, and is configured to control noise reduction of the pull-up node PU under the control of the first noise reduction control signal provided by the second noise reduction control terminal Ctrl 2;
the potential of the second noise reduction control signal is an inactive voltage in an input period and an output period of the shift register unit, and the potential of the second noise reduction control signal is an active voltage for at least part of a period included in a display period other than the input period and the output period.
In the noise reduction circuit according to the embodiment of the present invention, the potential of the second noise reduction control signal is set to be an invalid voltage in the input time period and the output time period so as not to affect the output of the gate driving signal; and displaying at least part of the time periods included in the period except the input time period and the output time period, and setting the potential of the second noise reduction control signal to be effective voltage so as to control the noise reduction of the PU.
In the embodiment of the present invention, when the potential of the second noise reduction control signal is an effective voltage, the second noise reduction circuit 12 performs noise reduction on the PU;
when the potential of the second noise reduction control signal is an invalid voltage, the second noise reduction circuit 12 does not reduce the noise of the PU.
In the embodiment of the present invention, when the second noise reduction transistor included in the second noise reduction circuit 12 is an n-type transistor, the effective voltage may be a high voltage, and the invalid voltage may be a low voltage, but not limited thereto.
As shown in fig. 3, the noise reduction circuit according to the embodiment of the present invention is configured to reduce noise of a gate driving signal Output terminal included in a shift register unit and a pull-up node PU included in the shift register unit, where the noise reduction circuit 30 includes a first noise reduction circuit 11 and a second noise reduction circuit 12;
the first noise reduction circuit 11 is electrically connected to the gate driving signal Output terminal Output and the first noise reduction control terminal Ctrl1, respectively, and is configured to control noise reduction of the gate driving signal Output terminal Output under the control of the first noise reduction control signal provided by the first noise reduction control terminal Ctrl 1;
the potential of the first noise reduction control signal is an invalid voltage in an output period of the shift register unit, and the potential of the first noise reduction control signal is an effective voltage for at least part of the time in a period other than the output period included in a display period;
the second noise reduction circuit 12 is electrically connected to the pull-up node PU and the second noise reduction control terminal Ctrl2, respectively, and is configured to control noise reduction of the pull-up node PU under the control of the first noise reduction control signal provided by the second noise reduction control terminal Ctrl 2;
the potential of the second noise reduction control signal is an inactive voltage in an input period and an output period of the shift register unit, and the potential of the second noise reduction control signal is an active voltage for at least part of a period included in a display period other than the input period and the output period.
In the noise reduction circuit according to the embodiment of the present invention, the potential of the first noise reduction control signal is set to be an invalid voltage in the output time period so as not to affect the output of the gate driving signal; displaying at least part of time in time periods except the Output time period included in the period, and setting the potential of the first noise reduction control signal to be effective voltage so as to control the noise reduction of the Output; setting the potential of the second noise reduction control signal to be an invalid voltage in an input period and an output period so as not to affect the gate driving signal output; and displaying at least part of the time periods included in the period except the input time period and the output time period, and setting the potential of the second noise reduction control signal to be effective voltage so as to control the noise reduction of the PU.
In this embodiment of the present invention, when the potential of the first noise reduction control signal is an effective voltage, the first noise reduction circuit 11 performs noise reduction on Output;
when the potential of the first noise reduction control signal is an invalid voltage, the first noise reduction circuit 11 does not reduce the noise of the Output;
when the potential of the second noise reduction control signal is an effective voltage, the second noise reduction circuit 12 performs noise reduction on the PU;
when the potential of the second noise reduction control signal is an invalid voltage, the second noise reduction circuit 12 does not reduce the noise of the PU.
Specifically, the first noise reduction circuit may include a first noise reduction transistor and at least one first noise reduction diode;
the anode of the first noise reduction diode is electrically connected with the first noise reduction control end, and the cathode of the first noise reduction diode is electrically connected with the control electrode of the first noise reduction transistor;
the first electrode of the first noise reduction transistor is electrically connected with the grid drive signal output end, and the second electrode of the first noise reduction transistor is electrically connected with the first noise reduction voltage end.
As shown in fig. 4, on the basis of the embodiment of the noise reduction circuit shown in fig. 1, the first noise reduction circuit includes a first noise reduction transistor MR1, a first noise reduction diode Dn11, a second first noise reduction diode Dn12 and a third first noise reduction diode Dn 13;
the shift register unit comprises an output transistor M3 and a storage capacitor C1;
the gate of the M3 is electrically connected to the pull-up node PU, the drain of the M3 is electrically connected to the first clock signal terminal, and the source of the M3 is electrically connected to the gate driving signal Output terminal Output; the first clock signal terminal is used for providing a first clock signal CLK 1;
the first noise reduction control end comprises a second clock signal end, an N +1 th-level gate driving signal output end OutputN +1 and an N +2 th-level shift register unit output end OutputN + 2; n is a positive integer; the second clock signal terminal is used for providing a second clock signal CLK 2;
the anode of Dn11 is connected to CLK2, and the cathode of Dn11 is electrically connected with the gate of MR 1;
the anode of Dn12 is electrically connected with OutputN +1, and the cathode of Dn12 is electrically connected with the gate of MR 1;
the anode of Dn13 is electrically connected with OutputN +2, and the cathode of Dn13 is electrically connected with the gate of MR 1;
the drain of the first noise reduction transistor MR1 is electrically connected to the gate drive signal Output terminal Output, and the source of the first noise reduction transistor MR1 is electrically connected to the low voltage terminal; the low voltage terminal is used for providing a low voltage VSS.
In the embodiment shown in fig. 4, the first noise reduction voltage terminal is the low voltage terminal, but not limited thereto.
In the embodiment shown in fig. 4, MR1 can be, but is not limited to, an n-type thin film transistor.
In actual operation, each noise reduction diode can realize the function of unidirectional cut-off.
In the embodiment shown in fig. 4, the shift register unit may be an nth stage shift register unit included in the gate driving circuit, and the shift register units of each stage included in the gate driving circuit are sequentially cascaded, and the first clock signal and the second clock signal are opposite in phase to each other; the first clock signal terminal is used for providing a first clock signal, and the second clock signal terminal is used for providing a second clock signal.
In the related art, by electrically connecting the control electrode of the transistor and the first electrode of the transistor, it is possible to be equivalent to a diode, in which case the control electrode of the transistor is equivalent to the anode of the diode and the second electrode of the transistor is equivalent to the cathode of the diode. In the embodiment of the present invention, the transistor equivalent to the diode is an n-type transistor.
As shown in fig. 5, on the basis of the embodiment of the noise reduction circuit shown in fig. 4, the first transistor Mn11 is equivalent to Dn11, the second transistor Mn12 is equivalent to Dn12, and the third transistor Mn13 is equivalent to Dn 13;
the gate of Mn11 and the drain of Mn11 are electrically connected with each other, the gate of Mn11 is electrically connected with CLK2, and the source of Mn11 is electrically connected with the gate of MR 1;
the gate of Mn12 and the drain of Mn12 are electrically connected with each other, the gate of Mn12 is electrically connected with OutputN +1, and the source of Mn12 is electrically connected with the gate of MR 1;
the gate of Mn13 and the drain of Mn13 are electrically connected to each other, and the gate of Mn13 is electrically connected to OutputN +2, and the source of Mn13 is electrically connected to the gate of MR 1.
In the embodiment shown in fig. 5, Mn11, Mn12, and Mn13 are all n-type thin film transistors, but are not limited thereto.
Specifically, the second noise reduction circuit comprises a second noise reduction transistor and at least one second noise reduction diode;
the anode of the second noise reduction diode is electrically connected with the second noise reduction control end, and the cathode of the second noise reduction diode is electrically connected with the control electrode of the second noise reduction transistor;
and the first pole of the second noise reduction transistor is electrically connected with the pull-up node, and the second pole of the second noise reduction transistor is electrically connected with a second noise reduction voltage end.
As shown in fig. 6, on the basis of the embodiment of the noise reduction circuit shown in fig. 2, the second noise reduction circuit includes a second noise reduction transistor MR2, a first second noise reduction diode Dn21, a second noise reduction diode Dn22 and a third second noise reduction diode Dn 23;
the shift register unit comprises an output transistor M3 and a storage capacitor C1;
the gate of the M3 is electrically connected to the pull-up node PU, the drain of the M3 is electrically connected to the first clock signal terminal, and the source of the M3 is electrically connected to the gate driving signal Output terminal Output; the first clock signal terminal is used for providing a first clock signal CLK 1;
the second noise reduction control end comprises a second clock signal end CLK2, an N +3 th stage gate driving signal output end outputN +3 and an N +4 th stage shift register unit output end outputN + 4; n is a positive integer; the second clock signal terminal is used for providing a second clock signal CLK 2;
the anode of Dn21 is connected to CLK2, and the cathode of Dn21 is electrically connected with the gate of MR 2;
the anode of Dn22 is electrically connected with OutputN +3, and the cathode of Dn22 is electrically connected with the gate of MR 2;
the anode of Dn23 is electrically connected with OutputN +4, and the cathode of Dn23 is electrically connected with the gate of MR 2;
the drain electrode of the second noise reduction transistor MR2 is electrically connected with the pull-up node PU, and the source electrode of the second noise reduction transistor MR2 is electrically connected with the low-voltage end; the low voltage terminal is used for providing a low voltage VSS.
In the embodiment shown in fig. 6, the second noise reduction voltage terminal is the low voltage terminal, but not limited thereto.
In the embodiment shown in fig. 6, MR2 can be, but is not limited to, an n-type thin film transistor.
In the embodiment shown in fig. 6, the shift register unit may be an nth stage shift register unit included in the gate driving circuit, and the shift register units of each stage included in the gate driving circuit are sequentially cascaded, and the first clock signal and the second clock signal are opposite in phase to each other; the first clock signal terminal is used for providing a first clock signal, and the second clock signal terminal is used for providing a second clock signal.
In the related art, by electrically connecting the control electrode of the transistor and the first electrode of the transistor, it is possible to be equivalent to a diode, in which case the control electrode of the transistor is equivalent to the anode of the diode and the second electrode of the transistor is equivalent to the cathode of the diode. In the embodiment of the present invention, the transistor equivalent to the diode is an n-type transistor.
As shown in fig. 7, on the basis of the embodiment of the noise reduction circuit shown in fig. 5, the fourth transistor Mn21 is equivalent to Dn21, the fifth transistor Mn22 is equivalent to Dn22, and the sixth transistor Mn23 is equivalent to Dn 23;
the gate of Mn21 and the drain of Mn21 are electrically connected with each other, the gate of Mn21 is connected to CLK2, and the source of Mn21 is electrically connected with the gate of MR 2;
the gate of Mn22 and the drain of Mn22 are electrically connected with each other, the gate of Mn22 is electrically connected with OutputN +3, and the source of Mn22 is electrically connected with the gate of MR 2;
the gate of Mn23 and the drain of Mn23 are electrically connected to each other, and the gate of Mn23 is electrically connected to OutputN +4, and the source of Mn23 is electrically connected to the gate of MR 2.
In the embodiment shown in fig. 7, Mn21, Mn22, and Mn23 are all n-type thin film transistors, but are not limited thereto.
In the embodiment of the present invention, the number of the first noise reduction control terminals may be at least one;
the first noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the first noise reduction control end comprises at least one of other clock signal ends connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
In a specific implementation, the number of the first noise reduction control terminals may be at least one, in the gate driving circuit, shift registers of different levels are cascaded with each other, all the shift registers of different levels may be cascaded in sequence, or odd-level shift register units may be cascaded with each other, and even-level shift registers are cascaded with each other, but not limited to this. In actual operation, the cascaded shift register units may be regarded as being included in the same group of shift register units, and the first noise reduction control terminal may include a gate driving signal output terminal of another shift register unit in the same group as the shift register unit;
and, the first noise reduction control terminal may include a noise reduction clock signal terminal; the noise reduction clock signal provided by the noise reduction clock signal terminal may be mutually inverted with respect to the clock signal provided by the clock signal terminal connected to the output transistor in the shift register unit, but not limited thereto.
In the embodiment of the present invention, the number of the second noise reduction control terminals may be at least one;
the second noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the second noise reduction control terminal comprises at least one of other clock signal terminals connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
In a specific implementation, the number of the second noise reduction control terminals may be at least one, in the gate driving circuit, shift registers of different levels are cascaded with each other, all the shift registers of different levels may be cascaded in sequence, or odd-level shift register units may be cascaded with each other, and even-level shift registers are cascaded with each other, but not limited to this. In actual operation, the cascaded shift register units may be regarded as being included in the same group of shift register units, and the second noise reduction control terminal may include a gate driving signal output terminal of a predetermined shift register unit in the same group as the shift register unit; the predetermined shift register unit is not an adjacent previous stage shift register unit of the shift register unit.
And, the second noise reduction control terminal may include a noise reduction clock signal terminal; the noise reduction clock signal provided by the noise reduction clock signal terminal may be mutually inverted with respect to the clock signal provided by the clock signal terminal connected to the output transistor in the shift register unit, but not limited thereto.
The noise reduction circuit of the embodiment of the invention can utilize the existing signal to avoid the output stage (the grid drive signal is output in the output stage) to carry out full-time noise reduction, and compared with the noise reduction circuit which only uses other clock signals, the noise reduction circuit of the embodiment of the invention is more sufficient.
The noise reduction circuit of the embodiment of the invention can reversely inject the gate driving signals output by other shift register units in the same group of shift register units back to the gate driving signal output end of the current stage (the noise reduction circuit is applied to the gate driving signal output end of the current stage), thereby achieving the purpose of noise reduction in the output cut-off holding stage. Compared with the traditional noise reduction means, the embodiment of the invention has the obvious advantage that the multi-signal control noise reduction is adopted to replace the single-signal control noise reduction, and the working time of each noise reduction control signal is shorter, so that the drift degree of the corresponding transistor is smaller. As for MR1 and MR2, it is also possible to realize high potential at the potential of the gate of MR1 and/or high potential at the potential interval of the gate of MR2 by using the timing characteristics of a TFT (thin film transistor) with a precharge structure, thereby improving the lifetime.
In addition, the noise reduction circuit is located in a Gate On Array (GOA) area, and the embodiment of the invention can improve the product reliability under the condition that the product structure is basically not changed, and basically does not increase the occupied space of the GOA area.
In the embodiment of the present invention, when the shift register unit is included in the gate driving circuit, the gate driving circuit employs two clock signal terminals: when the clock signals provided by the two clock signal ends are mutually opposite, the odd-level shift register unit can be electrically connected with the first clock signal end, and the even-level shift register unit can be electrically connected with the second clock signal end; the grid driving circuit comprises a plurality of stages of shift register units which are sequentially cascaded, namely, the input end of the A-stage shift register unit is electrically connected with the grid signal output end of the A-1-stage shift register unit, and the reset end of the A-stage shift register unit is electrically connected with the grid driving signal output end of the A + 1-stage shift register unit; a is an integer greater than 1, and A +1 is less than or equal to the total number of stages of the shift register units included in the gate driving circuit; the input end of the first stage shift register unit is accessed with an initial signal; at this time, all the shift register units included in the gate driving circuit are the same group of shift register units, and the first clock signal terminal and the second clock signal terminal are the same group of clock signal terminals.
In the embodiment of the present invention, when the gate driving signal adopts four clock signal terminals: the first clock signal terminal for providing the first clock signal CLK1, the second clock signal terminal for providing the second clock signal CLK2, the third clock signal terminal for providing the third clock signal CLK3, the fourth clock signal terminal for providing the fourth clock signal CLK4, the waveform of CLK1, the waveform of CLK2, the waveform of CLK3, and the waveform of CLK4 may be as shown in fig. 8(CLK1 is inverted from CLK3, and CLK2 is inverted from CLK 4), and the 4C-3 th stage shift register unit is accessed to CLK1, the 4C-2 th stage shift register unit is accessed to CLK2, the 4C-1 th stage shift register unit is accessed to CLK3, the 4C th stage shift register unit is accessed to CLK4, C is a positive integer, and 4C is less than or equal to the total stage number of the shift register units included in the grid drive circuit; at this time, the cascade relationship of the multi-stage shift register units included in the gate driving circuit may be as follows: odd-level shift register units are mutually cascaded, and even-level shift registers are mutually cascaded; that is, the reset end of the first stage shift register unit is electrically connected with the gate driving signal output end of the third stage shift register unit, the input end of the third stage shift register unit is electrically connected with the gate driving signal output end of the first stage shift register unit, the reset end of the third stage shift register unit is electrically connected with the gate driving signal output end of the fifth stage shift register unit, and so on; the reset end of the second-stage shift register unit is electrically connected with the gate drive signal output end of the fourth-stage shift register unit, the input end of the fourth-stage shift register unit is electrically connected with the gate drive signal output end of the second-stage shift register unit, the reset end of the fourth-stage shift register unit is connected with the gate drive signal output end of the sixth-stage shift register unit through a circuit, and so on; the input end of the first stage shift register unit is accessed with a first starting signal, and the input end of the second stage shift register unit is accessed with a second starting signal; at this time, the odd-numbered stage shift register units are the same group of shift register units, the even-numbered stage shift register units are the same group of shift register units, the first clock signal end and the third clock signal end are the same group of clock signal ends, and the second clock signal end and the fourth clock signal end are the same group of clock signal ends.
In the embodiment of the present invention, when the gate driving signal adopts six clock signal terminals: a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a fourth clock signal terminal, a fifth clock signal terminal and a sixth clock signal terminal, wherein the first clock signal terminal is used for providing a first clock signal CLK1, the second clock signal terminal is used for providing a second clock signal CLK2, the third clock signal terminal is used for providing a third clock signal CLK3, the fourth clock signal terminal is used for providing a fourth clock signal CLK4, the fifth clock signal terminal is used for providing a fifth clock signal CLK5, and the sixth clock signal terminal is used for providing a sixth clock signal CLK6(CLK1 is inverted to CLK4, CLK2 is inverted to CLK5, and CLK3 is inverted to CLK6, and at this time, the first clock signal terminal and the fourth clock signal terminal are the same group of clock signal terminals, the second clock signal terminal and the fifth clock signal terminal are the same group of clock signal terminals, and the third clock signal terminal and the sixth clock signal terminal are the same group of clock signal terminals); the 6D-5 stage shift register unit is accessed to CLK1, the 6D-4 stage shift register unit is accessed to CLK2, the 6D-3 stage shift register unit is accessed to CLK3, the 6D-2 stage shift register unit is accessed to CLK4, the 6D-1 stage shift register unit is accessed to CLK5, the 6D stage shift register unit is accessed to CLK6, D is a positive integer, and 6D is less than or equal to the total number of stages of the shift register units included in the gate driving circuit; at this time, the shift register units accessed to the CLK1 and the shift register units accessed to the CLK4 are a first group of shift register units, the shift register units accessed to the CLK2 and the shift register units accessed to the CLK5 are a second group of shift register units, the shift register units accessed to the CLK3 and the shift register units accessed to the CLK6 are a third group of shift register units, all the shift register units in the first group of shift register units are sequentially cascaded, all the shift register units in the second group of shift register units are sequentially cascaded, and all the shift register units in the third group of shift register units are sequentially cascaded; for example, a first stage shift register unit, a fourth stage shift register unit, a seventh stage shift register unit and a tenth shift register unit are sequentially cascaded, a second stage shift register unit, a fifth stage shift register unit, an eighth stage shift register unit and an eleventh stage shift register unit are sequentially cascaded, and a third stage shift register unit, a sixth stage shift register unit, a ninth stage shift register unit and a twelfth stage shift register unit are sequentially cascaded.
In the embodiment of the present invention, when the gate driving signal adopts eight clock signal terminals: a first clock signal terminal for providing a first clock signal CLK1, a second clock signal terminal for providing a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal terminal for providing a fourth clock signal CLK4, a fifth clock signal terminal for providing a fifth clock signal CLK5, a sixth clock signal terminal for providing a sixth clock signal CLK6, a seventh clock signal terminal for providing a seventh clock signal CLK7, an eighth clock signal terminal for providing an eighth clock signal CLK8(CLK1 is inverted with respect to CLK5, CLK2 is inverted with respect to CLK6, CLK3 and CLK7 are inverted, CLK4 and CLK8, when the first clock signal terminal and the fifth clock signal terminal are the same clock signal terminal, the second clock signal end and the sixth clock signal end are the same group of clock signal ends, the third clock signal end and the seventh clock signal end are the same group of clock signal ends, and the fourth clock signal end and the eighth clock signal end are the same group of clock signal ends); the 8E-7 stage shift register unit is accessed with CLK1, the 8E-6 stage shift register unit is accessed with CLK2, the 8E-5 stage shift register unit is accessed with CLK3, the 8E-4 stage shift register unit is accessed with CLK4, the 8E-3 stage shift register unit is accessed with CLK5, the 8E-2 stage shift register unit is accessed with CLK6, the 8E-1 stage shift register unit is accessed with CLK7, the 8E stage shift register unit is accessed with CLK8, E is a positive integer, and 8E is less than or equal to the total stage number of the shift register units included in the gate drive circuit; at this time, the shift register unit accessed to the CLK1 and the shift register unit accessed to the CLK5 are a first group of shift register units, the shift register unit accessed to the CLK2 and the shift register unit accessed to the CLK6 are a second group of shift register units, the shift register unit accessed to the CLK3 and the shift register unit accessed to the CLK7 are a third group of shift register units, the shift register unit accessed to the CLK4 and the shift register unit accessed to the CLK8 are a fourth group of shift register units, all the shift register units in the first group of shift register units are sequentially cascaded, all the shift register units in the second group of shift register units are sequentially cascaded, all the shift register units in the third group of shift register units are sequentially cascaded, and all the shift register units in the fourth group of shift register units are sequentially cascaded; for example, a first-stage shift register unit, a fifth-stage shift register unit, a ninth-stage shift register unit and a thirteenth-stage shift register unit are sequentially cascaded, a second-stage shift register unit, a sixth-stage shift register unit, a tenth-stage shift register unit and a fourteenth-stage shift register unit are sequentially cascaded, a third-stage shift register unit, a seventh-stage shift register unit, an eleventh-stage shift register unit and a fifteenth-stage shift register unit are sequentially cascaded, and a fourth-stage shift register unit, an eighth-stage shift register unit, a twelfth-stage shift register unit and a sixteenth-stage shift register unit are sequentially cascaded.
The shift register unit provided by the embodiment of the invention comprises the noise reduction circuit.
The gate driving circuit according to the embodiment of the invention includes a plurality of stages of the shift register units.
According to a specific implementation manner, the gate driving circuit according to the embodiment of the invention may further include a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-1) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit and the shift register unit of the N-1 th stage, which are included in the grid drive circuit; and/or the second noise reduction control terminal comprises the second clock signal terminal.
As shown in FIG. 9, the first embodiment of the shift register unit of the present invention comprises a first clock terminal for providing a first clock signal CLK1 and a second clock terminal for providing a second clock signal CLK 2;
the first specific embodiment of the gate driving circuit of the invention comprises M stages of shift register units which are sequentially cascaded;
in fig. 9, reference numeral S1 denotes a first-stage shift register unit, reference numeral SN-1 denotes an N-1 th-stage shift register unit, reference numeral SN denotes an nth-stage shift register unit, reference numeral N +1 denotes an N +1 th-stage shift register unit, reference numeral SM denotes an mth-stage shift register unit, N is an integer greater than 1, M is a positive integer, and M is greater than N + 1;
in fig. 9, the gate driving signal Output terminal denoted by Output1 is S1; a gate drive signal output terminal labeled OutputM for SM;
the input end of the S1 is connected with the initial signal STV, the input end of the SN is electrically connected with the gate driving signal output end outputN-1 of the SN-1, the reset end of the SN is electrically connected with the gate driving signal output end outputN +1 of the SN +1, and the input end of the SN +1 is electrically connected with the gate driving signal output end outputN of the SN; the reset end of the SM is connected with a reset signal RST;
s1 is accessed into CLK1, SN-1 is accessed into CLK2, SN is accessed into CLK1, SN +1 is accessed into CLK2, and SM is accessed into CLK 1;
the SN includes a first noise reduction control terminal and a second noise reduction control terminal,
the first noise reduction control terminal may include at least one of the gate driving signal output terminals of the shift register units of each stage other than SN in the first embodiment of the gate driving circuit, and/or the first noise reduction control terminal may include a second clock signal terminal;
the second noise reduction control terminal may include at least one of the gate driving signal output terminals of the shift register units of each stage other than SN and SN-1 in the first embodiment of the gate driving circuit, and/or the second noise reduction control terminal may include a second clock signal terminal;
in the embodiment of the present invention, the gate driving circuit of the present invention may further include a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit; n is equal to 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid driving circuit; and/or the second noise reduction control end comprises the second clock signal end;
that is, when the shift register unit of one stage is the shift register unit of the first stage included in the gate driving circuit,
the first noise reduction control terminal in the first stage shift register unit may include at least one of the gate driving signal output terminals of the other shift register units except the first stage shift register unit, and/or the first noise reduction control terminal in the first stage shift register unit may include a second clock signal terminal;
the second noise reduction control terminal in the first stage shift register unit may include at least one of gate driving signal output terminals of other shift register units except the first stage shift register unit, and/or the second noise reduction control terminal in the first stage shift register unit may include a second clock signal terminal.
According to another specific implementation manner, the gate driving circuit according to the embodiment of the present invention may further include a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-2) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2N) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; n is an integer, N +2N is greater than 0;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2) th stage shift register unit included in the gate drive circuit; and/or the second noise reduction control end comprises the third clock signal end; m is an integer, m is not equal to-1, and N +2m is greater than 0.
In a specific implementation, the gate driving circuit according to the embodiment of the present invention may include four clock signal terminals, the odd shift register units are cascaded with each other, and the even shift register units are cascaded with each other, that is, the odd shift register units belong to a same group of shift register units, the even shift register units belong to a same group of shift register units, the first clock signal terminal and the third clock signal terminal are a same group of clock signal terminals, the second clock signal terminal and the fourth clock signal terminal are a same group of clock signal terminals, and the nth shift register unit is electrically connected to the first clock signal terminal, so that the first noise reduction control terminal in the nth shift register unit may include at least one of the gate driving signal output terminals of the N +2N shift register units included in the gate driving circuit; and/or the first noise reduction control end comprises the third clock signal end, and the second noise reduction control end in the Nth-stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 m) -th-stage shift register unit included in the gate drive circuit; and/or the second noise reduction control terminal comprises the third clock signal terminal.
In the embodiment of the present invention, the gate driving circuit of the present invention may further include a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit; n is equal to 1 or 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; a is a positive integer;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the second noise reduction control terminal comprises the third clock signal terminal.
That is, when the gate driving circuit according to the embodiment of the present invention includes four clock signal terminals, and N is equal to 1, and the first stage shift register unit is connected to the first clock signal terminal, the first noise reduction control terminal in the first stage shift register unit includes at least one of the gate driving signal output terminals of the 1+2a stage shift register unit included in the gate driving circuit; and/or the first noise reduction control end comprises the third clock signal end, and the second noise reduction control end in the first-stage shift register unit comprises at least one of the grid driving signal output ends of the 1+2 a-stage shift register unit included in the grid driving circuit; and/or the second noise reduction control terminal comprises the third clock signal terminal.
When the gate driving circuit according to the embodiment of the present invention includes four clock signal terminals, and N is equal to 2, and the second stage shift register unit is connected to the first clock signal terminal, the first noise reduction control terminal in the second stage shift register unit includes at least one of the gate driving signal output terminals of the 2+2a stage shift register unit included in the gate driving circuit; and/or the first noise reduction control end comprises the third clock signal end, and the second noise reduction control end in the second-stage shift register unit comprises at least one of the gate drive signal output ends of the 2+2 a-stage shift register unit included in the gate drive circuit; and/or the second noise reduction control terminal comprises the third clock signal terminal.
As shown in fig. 10, the second embodiment of the gate driving circuit according to the present invention may include a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal, and the second embodiment of the gate driving circuit further includes a multi-stage shift register unit;
a first clock signal terminal for providing a first clock signal CLK1, a second clock signal terminal for providing a second clock signal CLK2, a third clock signal terminal for providing a third clock signal CLK3, and a fourth clock signal terminal for providing a fourth clock signal CLK 4; CLK1 and CLK3 are inverted with respect to each other, and CLK2 and CLK4 are inverted with respect to each other;
the second specific embodiment of the gate driving circuit of the invention comprises M stages of shift register units which are sequentially cascaded;
in fig. 10, a reference numeral S1 denotes a first-stage shift register unit, a reference numeral SN-2 denotes an N-2-th-stage shift register unit, a reference numeral SN-1 denotes an N-1-th-stage shift register unit, a reference numeral SN denotes an nth-stage shift register unit, a reference numeral SN +1 denotes an N + 1-th-stage shift register unit, a reference numeral N +2 denotes an N + 2-th-stage shift register unit, a reference numeral N +3 denotes an N + 3-th-stage shift register unit, a reference numeral SN +4 denotes an N + 4-th-stage shift register unit, a reference numeral SM denotes an mth-stage shift register unit, N is an integer greater than 2, M is a positive integer, and M is greater than N + 4;
in fig. 10, the gate driving signal Output terminal denoted by Output1 as S1, the gate driving signal Output terminal denoted by Output m as SM,
the input end of S1 is connected with the starting signal STV;
the input end of the SN is electrically connected with the gate driving signal output end OutputN-2 of the SN-2, and the reset end of the SN is electrically connected with the gate driving signal output end OutputN +2 of the SN + 2; the reset end of the SN-2 is electrically connected with the gate driving signal output end OutputN of the SN;
the input end of SN +1 is electrically connected with the gate driving signal output end OutputN-1 of SN-1, and the reset end of SN +1 is electrically connected with the gate driving signal output end OutputN +3 of SN + 3;
the input end of SN +2 is electrically connected with the gate driving signal output end OutputN of SN, and the reset end of SN +2 is electrically connected with the gate driving signal output end OutputN +4 of SN + 4;
the input end of SN +3 is electrically connected with the gate driving signal output end OutputN +1 of SN +1, and the input end of SN +4 is electrically connected with the gate driving signal output end OutputN +2 of SN + 2;
SN access CLK1, SN +1 access CLK2, SN +2 access CLK3, SN +3 access CLK4, SN +4 access CLK1, SN-1 access CLK4, SN-2 access CLK3, S1 access CLK1, SM access CLK 4;
shown in fig. 11 are a waveform diagram of CLK1, a waveform diagram of CLK2, a waveform diagram of CLK3, a timing chart of the potential of a pull-up node PU-N in a waveform diagram SN of CLK4, a waveform diagram of a gate drive signal output by OutputN +1, a waveform diagram of a gate drive signal output by OutputN +2, a waveform diagram of OutputN-1, a waveform diagram of ouptn-2, and, when the noise reduction circuit in SN includes a first noise reduction circuit and the first noise reduction control terminal includes OutputN +2N (N is an integer, N +2N is greater than 0), the first noise reduction control terminal further includes a third clock signal terminal, a waveform of the potential Mr of the gate of the first noise reduction transistor in the first noise reduction circuit;
as shown in fig. 11, CLK1 is inverted with respect to CLK3, CLK2 is inverted with respect to CLK4, an input phase of SN is denoted by t0, an output phase of SN is denoted by t1, a reset phase of SN is denoted by t2, and an output-off holding phase of SN is denoted by t 3;
at t0, the potential of CLK1 is low, the potential of PU-N is pulled up, OutputN-2 outputs high, OutputN outputs low, and OutputN +2 outputs low;
at t1, the potential of CLK2 is high, the potential of PU-N is bootstrapped up, OutputN-2 outputs low, OutputN outputs high, and OutputN +2 outputs low;
at t2, the potential of PU-N is pulled low, the potential of CLK1 is low, the potential of OutputN is low, and OutputN +2 outputs high;
at t3, the potential of PU-N is kept at low level, OutputN +2h outputs high level in sequence, h is an integer greater than 1, so as to pull down the potential of PU-N continuously.
And in a blank period set between two adjacent frame display times, the potential Mr of the gate of the first noise reduction transistor in the first noise reduction circuit may be at a low level, but is not limited thereto.
The display device provided by the embodiment of the invention comprises the gate drive circuit.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display device, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A noise reduction circuit is used for reducing noise of a grid driving signal output end included by a shift register unit and/or a pull-up node included by the shift register unit, and is characterized by comprising a first noise reduction circuit and/or a second noise reduction circuit;
the first noise reduction circuit is respectively electrically connected with the gate drive signal output end and the first noise reduction control end and is used for controlling noise reduction of the gate drive signal output end under the control of a first noise reduction control signal provided by the first noise reduction control end;
the second noise reduction circuit is respectively electrically connected with the pull-up node and the second noise reduction control end and is used for controlling noise reduction of the pull-up node under the control of a second noise reduction control signal provided by the second noise reduction control end;
the potential of the first noise reduction control signal is an invalid voltage in an output period of the shift register unit, and the potential of the first noise reduction control signal is an effective voltage for at least part of the time in a period other than the output period included in a display period;
the potential of the second noise reduction control signal is an inactive voltage in an input period and an output period of the shift register unit, and the potential of the second noise reduction control signal is an active voltage for at least part of a period included in a display period other than the input period and the output period.
2. The noise reduction circuit of claim 1, wherein the first noise reduction circuit comprises a first noise reduction transistor and at least one first noise reduction diode;
the anode of the first noise reduction diode is electrically connected with the first noise reduction control end, and the cathode of the first noise reduction diode is electrically connected with the control electrode of the first noise reduction transistor;
the first electrode of the first noise reduction transistor is electrically connected with the grid drive signal output end, and the second electrode of the first noise reduction transistor is electrically connected with the first noise reduction voltage end.
3. The noise reduction circuit of claim 1, wherein the second noise reduction circuit comprises a second noise reduction transistor and at least one second noise reduction diode;
the anode of the second noise reduction diode is electrically connected with the second noise reduction control end, and the cathode of the second noise reduction diode is electrically connected with the control electrode of the second noise reduction transistor;
and the first pole of the second noise reduction transistor is electrically connected with the pull-up node, and the second pole of the second noise reduction transistor is electrically connected with a second noise reduction voltage end.
4. The noise reduction circuit according to any one of claims 1 to 3, wherein the number of the first noise reduction control terminals is at least one;
the first noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the first noise reduction control end comprises at least one of other clock signal ends connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
5. The noise reduction circuit according to any one of claims 1 to 3, wherein the number of the second noise reduction control terminals is at least one;
the second noise reduction control end comprises at least one of grid driving signal ends of other stages of shift register units; and/or the second noise reduction control terminal comprises at least one of other clock signal terminals connected with the grid drive circuit;
the other stage shift register units are all stage shift register units except the shift register unit in the grid driving circuit;
and the other clock signal ends are the clock signal ends except the clock signal end connected with the shift register unit in the clock signal ends connected with the gate drive circuit.
6. A shift register cell comprising a noise reduction circuit according to any of claims 1 to 5.
7. A gate drive circuit comprising a plurality of stages of the shift register cell of claim 6.
8. The gate drive circuit of claim 7, further comprising a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-1) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit and the shift register unit of the N-1 th stage, which are included in the grid drive circuit; and/or the second noise reduction control terminal comprises the second clock signal terminal.
9. The gate drive circuit of claim 7, further comprising a first clock signal terminal and a second clock signal terminal;
the grid driving signal end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 1) th-stage shift register unit included in the grid driving circuit; n is equal to 1;
the Nth-stage shift register unit is electrically connected with the first clock signal end;
the first noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid drive circuit; and/or the first noise reduction control end comprises the second clock signal end;
the second noise reduction control end in the Nth stage shift register unit comprises at least one of the shift register units of other stages except the Nth stage shift register unit, which are included in the grid driving circuit; and/or the second noise reduction control terminal comprises the second clock signal terminal.
10. The gate drive circuit of claim 7, further comprising a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit, and the grid driving signal output end of the Nth-stage shift register unit is electrically connected with the reset end of the (N-2) th-stage shift register unit included in the grid driving circuit; n is an integer greater than 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2N) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; n is an integer, N +2N is greater than 0;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N + 2) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; m is an integer, m is not equal to-1, and N +2m is greater than 0.
11. The gate drive circuit of claim 7, further comprising a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, and a fourth clock signal terminal;
the grid driving signal output end of the Nth-stage shift register unit included in the grid driving circuit is electrically connected with the input end of the (N + 2) th-stage shift register unit included in the grid driving circuit; n is equal to 1 or 2;
the Nth-stage shift register unit is electrically connected with the first clock signal end, a first clock signal provided by the first clock signal end and a third clock signal provided by the third clock signal end are mutually in opposite phase, and a second clock signal provided by the second clock signal end and a fourth clock signal provided by the fourth clock signal end are mutually in opposite phase;
the first noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control end comprises the third clock signal end; a is a positive integer;
the second noise reduction control end in the nth stage shift register unit comprises at least one of the gate drive signal output ends of the (N +2 a) th stage shift register unit included in the gate drive circuit; and/or the first noise reduction control terminal comprises the third clock signal terminal.
12. A display device comprising the gate driver circuit according to any one of claims 7 to 11.
CN201911044189.3A 2019-10-30 2019-10-30 Noise reduction circuit, shift register unit, gate drive circuit and display device Pending CN110728943A (en)

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Application publication date: 20200124