CN109448656A - Shift register and gate drive circuit - Google Patents
Shift register and gate drive circuit Download PDFInfo
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- CN109448656A CN109448656A CN201811600791.6A CN201811600791A CN109448656A CN 109448656 A CN109448656 A CN 109448656A CN 201811600791 A CN201811600791 A CN 201811600791A CN 109448656 A CN109448656 A CN 109448656A
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- 230000004044 response Effects 0.000 claims abstract description 26
- 230000005611 electricity Effects 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000006073 displacement reaction Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 8
- 239000010409 thin film Substances 0.000 abstract description 8
- 230000009467 reduction Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
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- 238000005516 engineering process Methods 0.000 description 2
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Logic Circuits (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The present application relates to a shift register and a gate driving circuit. The shift register comprises a pull-up circuit, an output circuit, a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The first pull-down control circuit provides a high level signal to the pull-down control node in response to a high level signal, provides a high level signal to the pull-down node in response to a voltage signal of the pull-down control node, and provides low level signals to the pull-down node and the pull-down control node in response to the first switching signal, the second switching signal, and the voltage signal of the pull-up node, respectively. The second pull-down control circuit responds to the first pull-down control signal and the second pull-down control signal and provides the low level signal to the pull-down node and the pull-down control node respectively, so that the time of the pull-down node in a direct-current high-level working state is reduced, the possibility of the drift of the threshold voltage of the related thin film transistor is reduced, and the noise reduction effect is improved.
Description
Technical field
This application involves display field more particularly to a kind of shift registors and gate driving circuit.
Background technique
Thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-
LCD) driver mainly includes gate driving circuit and data drive circuit, wherein gate driving circuit believes the clock of input
Number by shift registor convert after be added on the grid line of liquid crystal display panel, gate driving circuit can with TFT formed have
Same process is simultaneously simultaneously formed together on the lcd panel with TFT.Gate driving circuit includes the shift registor with multistage,
Every grade of shift registor is all connected to corresponding grid line to export gate drive signal.The phases each other at different levels of gate driving circuit
Even, initial signal is input to the exporting gate drive signal to grid line of the first order at different levels and sequence, wherein current n-th
The input terminal of grade is connected to the n-th -2 grades of output end, and the first pulldown signal input terminal is connected to the n-th+4 grades of output end, and second
Pulldown signal input terminal is connected to the pull-down node of bottom n-1, and first switch signal input part connects (n-1)th grade of pull-up node,
Second switch signal input part connects (n+1)th grade of pull-up node.
It is general by setting in the gate driving circuit of LCD panel setting above structure, at present gate driving circuit design
It sets pull-down node to drag down the current potential of the output terminal of non-output row, still, if pull-down node is chronically at direct current high level
Working condition, the threshold voltage that may result in relevant thin film transistor (TFT) drift about, and influence noise reduction effect.
Summary of the invention
Based on this, this application provides a kind of shift registor and gate driving circuits, are located for a long time with improving pull-down node
In the direct current high level working condition the case where.
The embodiment of the present application provides a kind of shift registor, comprising:
Pull-up circuit connects the input signal end of the shift registor, to respond input signal, and by the input
Signal is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, to respond the electricity of the pull-up node
Signal is pressed, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, the first pulldown signal input terminal of connection, the second pulldown signal input terminal and pull-down node, to sound
The voltage signal of the first pulldown signal, the second pulldown signal and the pull-down node is answered, and low level signal is provided respectively
First output end of pull-up node and the shift registor to the shift registor；
First pull-down control circuit connects high level signal input terminal, first switch signal input part, second switch signal
Input terminal, drop-down control node, the pull-down node and the pull-up node, to respond the high level signal, by institute
It states high level signal and is supplied to the drop-down control node, respond the voltage signal of the drop-down control node, by the high electricity
Ordinary mail number is supplied to the pull-down node, and the electricity of response first switch signal, second switch signal and the pull-up node
Signal is pressed, and the low level signal is respectively supplied to the pull-down node and the drop-down control node；And
Second pull-down control circuit, connection first drop-down control signal input, second drop-down control signal input and
The pull-down node to respond the first drop-down control signal and the second drop-down control signal, and the low level signal is divided
Indescribably supply the pull-down node and the drop-down control node.
First pull-down control circuit includes: in one of the embodiments,
First switch branch, connection first switch signal input part, the drop-down control node and the pull-down node, is used
To respond the first switch signal, and the low level signal is respectively supplied to the pull-down node and drop-down control
Node；
Second switch branch connects the pull-up node, the drop-down control node and the pull-down node, to respond
The voltage signal of the pull-up node, and the low level signal is respectively supplied to the pull-down node and drop-down control
Node；
Third switching branches connect the second switch signal input part, the drop-down control node and drop-down section
Point, to respond the second switch signal, and by the low level signal be respectively supplied to the pull-down node and it is described under
Draw control node；And
Drop-down input branch, connects the high level signal input terminal, the drop-down control node and the pull-down node,
To respond the high level signal, the high level signal is supplied to the drop-down control node, and under response is described
The voltage signal for drawing control node, is supplied to the pull-down node for the high level signal.
Second pull-down control circuit includes: in one of the embodiments,
First drop-down controlling brancher, connects the first drop-down control signal input and the pull-down node, to sound
The first drop-down control signal is answered, and the low level signal is supplied to the pull-down node；And
Second drop-down controlling brancher, connects the second drop-down control signal input and the pull-down node, to sound
The second drop-down control signal is answered, and the low level signal is supplied to the pull-down node.
The pull-down circuit includes: in one of the embodiments,
First drop-down branch, connects the first pulldown signal input terminal, to respond first pulldown signal, and will
Low level signal is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；
Second drop-down branch, connects the second pulldown signal input terminal, to respond second pulldown signal, and will
Low level signal is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；And
Third pulls down branch, connects the pull-down node, to respond the voltage signal of the pull-down node, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor.
The pull-up circuit includes: in one of the embodiments,
First switch tube, grid and drain electrode are connect with the input signal end, and source electrode is connect with the pull-up node.
The output circuit includes: in one of the embodiments,
Second switch, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and institute
State the first output end connection of shift registor；
Third switching tube, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and institute
State the second output terminal connection of shift registor；And
Capacitor, one end are connect with the pull-up node, and the other end is connect with the first output end of the shift registor.
The first drop-down branch includes: in one of the embodiments,
4th switching tube, grid are connect with the first pulldown signal input terminal, drain electrode and the of the shift registor
One output end and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
5th switching tube, grid are connect with the first pulldown signal input terminal, and drain electrode is connect with the pull-up node, source
Pole is connect with the low level voltage signal input part；
Described second, which pulls down branch, includes:
6th switching tube, grid are connect with the second pulldown signal input terminal, drain electrode and the of the shift registor
One output end and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
7th switching tube, grid are connect with the second pulldown signal input terminal, and drain electrode is connect with the pull-up node, source
Pole is connect with the low level voltage signal input part；
The third pulls down branch
8th switching tube, grid are connect with the pull-down node, drain electrode and the first output end of the shift registor with
And the capacitance connection, source electrode are connect with the low level voltage signal input part；And
9th switching tube, grid are connect with the pull-down node, drain electrode connect with the pull-up node, source electrode with it is described low
The connection of level voltage signal input terminal.
The drop-down input branch includes: in one of the embodiments,
Tenth switching tube, grid and drain electrode are connect with the high level signal input terminal, and source electrode and the drop-down control
Node connection；And
11st switching tube, grid are connect with the drop-down control node, and drain electrode connects with the high level signal input terminal
It connects, source electrode is connect with the pull-down node；
The first switch branch includes:
12nd switching tube, grid are connect with the first switch signal input part, drain electrode and the drop-down control node
Connection, source electrode are connect with the low level signal input terminal；And
13rd switching tube, grid are connect with the first switch signal input part, and drain electrode is connect with pull-down node, source electrode
It is connect with the low level signal input terminal；
The second switch branch includes:
14th switching tube, grid are connect with the pull-up node, drain electrode connect with the drop-down control node, source electrode and
The low level signal input terminal connection；And
15th switching tube, grid are connect with the pull-up node, and drain electrode is connect with pull-down node, source electrode and the low electricity
Flat signal input part connection；
The third switching branches include:
Sixteenmo closes pipe, and grid is connect with the second switch signal input part, drain electrode and the drop-down control node
Connection, source electrode are connect with the low level signal input terminal；And
17th switching tube, grid are connect with the second switch signal input part, and drain electrode is connect with pull-down node, source electrode
It is connect with the low level signal input terminal.
The first drop-down controlling brancher includes that eighteenmo pass is managed in one of the embodiments, under grid and first
Control signal input connection is drawn, drain electrode is connect with the pull-down node, and source electrode is connect with the low level signal input terminal；With
And
The second drop-down controlling brancher includes the 19th switching tube, and grid and the second drop-down control signal input connect
It connects, drain electrode is connect with the pull-down node, and source electrode is connect with the low level signal input terminal.
Based on the same inventive concept, present invention also provides a kind of gate driving circuit, including cascade displacement at different levels are temporary
Storage, the shift registor include:
Pull-up circuit connects the second output terminal of the n-th -2 grades shift registors, temporary to respond the n-th -2 grades displacements
The output signal of storage, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, to respond the electricity of the pull-up node
Signal is pressed, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, connect the pull-down node of (n-1)th grade of shift registor, the pull-down node of the shift registor and
First output end of the n-th+4 grades shift registors, to respond the electricity of the first output end of the n-th+4 grades shift registors output
Signal is pressed, and low level signal is respectively supplied to the pull-up node of the shift registor and the first output of the shift registor
End；
First pull-down control circuit, connection high level signal input terminal, the pull-up node of (n+1)th grade of buffer, (n-1)th grade
The pull-up node of shift registor, the pull-up node of the shift registor, drop-down control node and the pull-down node, to
The high level signal is responded, the high level signal is supplied to the drop-down control node, responds the drop-down control section
The high level signal is supplied to the pull-down node, and the pull-up section of (n+1)th grade of buffer of response by the voltage signal of point
The pull-up node of the voltage signal of point, the voltage signal of the pull-up node of (n-1)th grade of shift registor, the shift registor
The low level signal is respectively supplied to the pull-down node and the drop-down control node by voltage signal；And
The clock signal input terminal of second pull-down control circuit, connection n-th+5 and n+6 grades of shift registors, to sound
The clock signal of n-th+5 and n+6 grades of shift registors is answered, and the low level signal is respectively supplied to the pull-down node
With the drop-down control node；
Wherein, 2 < n < N-6, N is grid line quantity, and n and N are positive integer.
To sum up, this application provides a kind of shift registor and gate driving circuits.The shift registor includes pull-up
Circuit, output circuit, pull-down circuit, the first pull-down control circuit and the second pull-down control circuit.The pull-up circuit connects institute
The input signal end for stating shift registor is supplied to pull-up node to respond input signal, and by the input signal.It is described
Output circuit connects the pull-up node and clock signal input terminal, to respond the voltage signal of the pull-up node, and
Clock signal is supplied to the first output end and second output terminal of the shift registor.Under the pull-down circuit connection first
Signal input part, the second pulldown signal input terminal and pull-down node are drawn, to respond the first pulldown signal, the second pulldown signal
And the voltage signal of the pull-down node, and low level signal is respectively supplied to the pull-up node of the shift registor and is somebody's turn to do
First output end of shift registor.First pull-down control circuit connects high level signal input terminal, first switch signal
Input terminal, second switch signal input part, drop-down control node, the pull-down node and the pull-up node, to respond
The high level signal is supplied to the drop-down control node by the high level signal, responds the drop-down control node
The high level signal is supplied to the pull-down node, and response first switch signal, second switch signal by voltage signal
With the voltage signal of the pull-up node, and the low level signal is respectively supplied to the pull-down node and the drop-down and is controlled
Node processed.Second pull-down control circuit, the first drop-down of connection control signal input, the second drop-down control signal input
With the pull-down node, to respond the first drop-down control signal and the second drop-down control signal, and by the low level signal
It is respectively supplied to the pull-down node and the drop-down control node.In the application, in non-output stage, the shift registor
In response to the first drop-down control signal and the second drop-down control signal, and the low level signal is respectively supplied to described
Pull-down node and the drop-down control node, so that the time that the pull-down node is in direct current high level working condition is reduced,
And then a possibility that threshold voltage of relevant thin film transistor (TFT) drifts about is reduced, raising noise reduction effect.
Detailed description of the invention
Fig. 1 is the electrical structure schematic diagram of exemplary display panel；
Fig. 2 is thompson electrical block diagram；
Fig. 3 is the charging process schematic diagram of pull-up node in thompson circuit；
Fig. 4 is the electrical block diagram of illustrative shift registor；
Fig. 5 is the electrical block diagram of the shift registor of another exemplary；
Fig. 6 is the timing diagram of each signal end of the shift registor in Fig. 5；
Fig. 7 is a kind of electrical block diagram of shift registor provided by the embodiments of the present application；
Fig. 8 is a kind of cascade structure schematic diagram of gate driving circuit provided by the present application；
Fig. 9 is the timing diagram of each signal end of the shift registor in Fig. 7.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this Shen
Please.But the application can be implemented with being much different from other way described herein, those skilled in the art can be not
Similar improvement is done in the case where violating the application intension, therefore the application is not limited by following public specific implementation.
Referring to Figure 1, shift registor (Gate On Array, GOA) is an important technology in panel design,
Major advantage is can to replace grid drive chip (Gate driver IC), reduces production cost, is mainly exactly to pass through
Exposure development technology generates logic circuit to drive grid signal.
Fig. 2 and Fig. 3 are referred to, gate driving circuit is developed on the basis of thompson circuit at present,
In scanning process, can all there be a preliminary filling signal to carry out preliminary filling to the point at pull-up node Q (boost point), so that the point
Voltage signal increase lofty perch position, and then be connected respective switch pipe export clock signal.
Fig. 4 and Fig. 5 are referred to, general shift registor includes main circuit, secondary pull-down circuit and secondary drop-down control electricity
Road.By taking the fourth stage shift registor during the gate driving circuit being made of 8 cascade shift registors is as an example, the 4th
The shift registor that grade moves gate driving circuit is only high electricity in the voltage signal and its clock signal CK4 when its pull-up node
Scanning signal is usually exported, to realize grid line turntable driving function.But the pull-down node in the shift registor is for a long time
In direct current high level working condition, Fig. 6 is referred to, the threshold voltage that may result in relevant thin film transistor (TFT) floats
It moves, and then influences noise reduction effect.
To reduce the time that pull-down node is in direct current high level working condition, this application provides a kind of shift registers
Device refers to Fig. 7.The shift registor includes pull-up circuit 100, output circuit 200, the drop-down control of pull-down circuit 300, first
Circuit 400 processed and the second pull-down control circuit 500.
The pull-up circuit 100 connects the input signal end F (n-2) of the shift registor, to respond input signal,
And the input signal is supplied to pull-up node Q (n).
The output circuit 200 connects the pull-up node Q (n) and clock signal CK (n) input terminal, to respond
It states the voltage signal of pull-up node Q (n), and clock signal is supplied to the first output end G (n) and the of the shift registor
Two output end F (n).
The pull-down circuit 300 connects the first pulldown signal input terminal G (n+4), the second pulldown signal input terminal P (n-1)
And pull-down node P (n), to respond the voltage signal of the first pulldown signal, the second pulldown signal and the pull-down node,
And low level signal is respectively supplied to the pull-up node Q (n) of the shift registor and the first output end G of the shift registor
(n)。
First pull-down control circuit 400 connects high level signal VDD input terminal, first switch signal input part Q (n+
1), second switch signal input part Q (n-1), drop-down control node H (n), the pull-down node p (n) and the pull-up node
The high level signal is supplied to the drop-down control node H (n), responds institute by Q (n) to respond the high level signal
The high level signal VDD is supplied to the pull-down node P (n), and rung by the voltage signal for stating drop-down control node H (n)
The voltage signal of first switch signal, second switch signal and the pull-up node Q (n) is answered, and the low level signal is divided
Indescribably supply the pull-down node and the drop-down control node.
The described connection of second pull-down control circuit 500 first drop-down control signal CK (n+6) input terminal, the second drop-down control
Signal CK (n+5) input terminal and the pull-down node P (n), to respond the first drop-down control signal CK (n+6) and the second drop-down
It controls signal CK (n+5), and the low level signal is respectively supplied to the pull-down node and the drop-down control node.
It is appreciated that in non-output stage, the shift registor is in response to the first drop-down control signal CK (n+6) and the
Two drop-down controls signal CK (n+5), and the low level signal is respectively supplied to the pull-down node P (n) and the drop-down
Control node H (n) to reduce the time that the pull-down node P (n) is in direct current high level working condition, and then reduces phase
A possibility that threshold voltage of the thin film transistor (TFT) of pass drifts about, to improve noise reduction effect.
First pull-down control circuit 400 is opened including first switch branch 410, second in one of the embodiments,
Close branch 420, third switching branches 430 and drop-down input branch 440.
The first switch branch 410 connects first switch signal Q (n+1) input terminal, the drop-down control node H (n)
With the pull-down node P (n), to respond the first switch signal Q (n+1), and the low level signal is provided respectively
To the pull-down node P (n) and the drop-down control node H (n).
The second switch branch 420 connect the pull-up node Q (n), the drop-down control node H (n) and it is described under
It draws node P (n), is respectively supplied to respond the voltage signal of the pull-up node Q (n), and by the low level signal VSS
The pull-down node P (n) and the drop-down control node H (n).
The third switching branches 430 connect second switch signal Q (n-1) input terminal, the drop-down control node H
(n) with the pull-down node P (n), to respond the second switch signal Q (n-1), and the low level signal is mentioned respectively
Supply the pull-down node P (n) and the drop-down control node H (n).
Drop-down input branch 440 connect the high level signal VDD input terminal, the drop-down control node H (n) with
The high level signal VDD is supplied to the drop-down to respond the high level signal VDD by the pull-down node P (n)
Control node H (n), and the voltage signal of response drop-down control node H (n), the high level signal VDD is supplied to
The pull-down node P (n).
In the present embodiment, believed using the voltage signal of the pull-up node of rear stage shift registor as the first switch
Number to control first switch branch 410, using the voltage signal of the pull-up node of current shift buffer as controlling described the
Two switching branches 420 are believed using the voltage signal of the pull-up node of the previous stage shift registor as the second switch
Number to control the third switching branches 430, so that the pull-down node described in output stage keeps low level signal, not to described
First output end discharges.
Second pull-down control circuit 500 includes: in one of the embodiments,
First drop-down controlling brancher 510, connects the first drop-down control signal CK (n+6) input terminal and drop-down section
Point P (n), to respond it is described first drop-down control signal CK (n+6), and by the low level signal VSS be supplied to it is described under
It draws node P (n)；
Second drop-down controlling brancher 520, connects the second drop-down control signal CK (n+5) input terminal and drop-down section
Point P (n), to respond it is described second drop-down control signal CK (n+5), and by the low level signal VSS be supplied to it is described under
It draws node P (n).
In this implementation, using the n-th+6 grades of clock signals as the first drop-down control signal when prime, described the is controlled
One drop-down controlling brancher 510.It is pulled down using the n-th+5 grades of clock signals as work as prime second and controls signal, described in control
Second drop-down controlling brancher 520.
It is appreciated that being saved in non-output stage when the drop-down can not be reduced by first pull-down control circuit 400
Point voltage when, can further by it is described first drop-down controlling brancher 510 and second drop-down controlling brancher 520 reduce it is described under
Node is drawn be in time of high direct voltage state, keeping the pull-down node in the voltage signal of non-output stage is alternating voltage
Signal, to effectively inhibit the output of the mistake as caused by the drift of the threshold voltage of element itself.
The pull-down circuit 300 includes that the first drop-down branch 310, second pulls down branch 320 in one of the embodiments,
Branch 330 is pulled down with third.
The first drop-down branch 310 connects the first pulldown signal Q (n+4) input terminal, to respond described first
Pulldown signal Q (n+4), and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the displacement
First output end G (n) of buffer；
The second drop-down branch 320 connects the second pulldown signal P (n-1) input terminal, to respond described second
Pulldown signal P (n-1), and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the displacement
First output end G (n) of buffer；And
The third drop-down branch 330 connects the pull-down node P (n), to respond the electricity of the pull-down node P (n)
Signal is pressed, and low level signal VSS is respectively supplied to the pull-up node Q (n) and the shift registor of the shift registor
First output end G (n).
In the present embodiment, using the n-th+4 grades of output signal Q (n+4) as first pulldown signal, described in control
First drop-down branch 310.Using the voltage signal P (n-1) of (n-1)th grade of pull-down node as second pulldown signal, with control
Make the second drop-down branch 320.The third, which is controlled, using the voltage signal as prime pull-down node P (n) pulls down branch
330.It is appreciated that by pulling down 330 pairs of branch pull-up of branch 320 and third drop-down to the first drop-down branch 310, second
Node Q (n) and the first output end G (n) carries out continual electric discharge, and the noise reduction effect of the shift registor can be improved.
The pull-up circuit 100 includes first switch tube T1 in one of the embodiments,.The first switch tube T1's
Grid and drain electrode are connected with the input signal F (n-2) end, and source electrode is connect with the pull-up node Q (n).
In the present embodiment, as the input signal for working as prime, described first opens described the n-th -2 grades of output signal F (n-2)
It closes pipe T1 grid and drain electrode is connect with described the n-th -2 grades of second output terminal.
The output circuit 200 includes second switch T2, third switch transistor T 3 and capacitor in one of the embodiments,
C。
The grid of the second switch T2 is connect with the pull-up node Q (n), drain electrode and the clock signal CK (n)
Input terminal connection, source electrode connect G (n) with the first output end of the shift registor.
The grid of the third switch transistor T 3 is connect with the pull-up node Q (n), drain electrode and the clock signal input terminal
Connection, source electrode are connect with the second output terminal F (n) of the shift registor.
The one end the capacitor C is connect with the pull-up node Q (n), the first output of the other end and the shift registor
G (n) connection is held, for keeping the current potential of pull-up node Q (n).
In the present embodiment, first output end is connect with scan line, provides scanning signal for display panel, and described second
The output signal of output end is as the n-th+2 grades of input signal, to realize continuous scanning.
The first drop-down branch 310 includes the 4th switch transistor T 4 and the 5th switch transistor T 5 in one of the embodiments,.
The grid of 4th switch transistor T 4 is connect with the first pulldown signal input terminal G (n+4) input terminal, drain electrode with
First output end of the shift registor and the capacitor C connection, source electrode and the low level voltage signal VSS input terminal
Connection.
The grid of 5th switch transistor T 5 is connect with the first pulldown signal input terminal G (n+4) input terminal, drain electrode with
Pull-up node Q (n) connection, source electrode are connect with the low level voltage signal VSS input terminal.
The second drop-down branch 320 includes the 6th switch transistor T 6 and the 7th switch transistor T 7.
The grid of 6th switch transistor T 6 is connect with the second pulldown signal P (n-1) input terminal, drain electrode and the shifting
First output end G (n) of position buffer and the capacitor C connection, source electrode and the low level voltage signal VSS input terminal connect
It connects.
The grid of 7th switch transistor T 7 is connect with the second pulldown signal P (n-1) input terminal, drain electrode with it is described on
Node Q (n) connection is drawn, source electrode is connect with the low level voltage signal VSS input terminal.
The third drop-down branch 330 includes the 8th switch transistor T 8 and the 9th switch transistor T 9.
The grid of 8th switch transistor T 8 is connect with the pull-down node P (n), drain electrode and the of the shift registor
One output end G (n) and the capacitor C connection, source electrode are connect with the low level voltage signal VSS input terminal.
The grid of 9th switch transistor T 9 is connect with the pull-down node P (n), and drain electrode connects with the pull-up node Q (n)
It connects, source electrode is connect with the low level voltage signal VSS input terminal.
The drop-down input branch 440 includes the tenth switch transistor T 10, the 11st switching tube in one of the embodiments,
T11。
The grid of tenth switch transistor T 10 and drain electrode are connect with the high level signal VDD input terminal, source electrode and institute
State drop-down control node H (n) connection.
The grid of 11st switch transistor T 11 is connect with the drop-down control node H (n), drain electrode and the high level
The connection of signal VDD input terminal, source electrode are connect with the pull-down node P (n).
The first switch branch 410 includes the 12nd switch transistor T 12 and the 13rd switch transistor T 13.
The grid of 12nd switch transistor T 12 is connect with first switch signal Q (n+1) input terminal, drain electrode and institute
Drop-down control node H (n) connection is stated, source electrode is connect with the low level signal VSS input terminal；And
The grid of 13rd switch transistor T 13 is connect with first switch signal Q (n+1) input terminal, and drain electrode is under
Node P (n) connection is drawn, source electrode is connect with the low level signal VSS input terminal.
The second switch branch 420 includes the 14th switch transistor T 14 and the 15th switch transistor T 15.
The grid of 14th switch transistor T 14 is connect with the pull-up node Q (n), and drain electrode is saved with drop-down control
Point H (n) connection, source electrode are connect with the low level signal VSS input terminal.
The grid of 15th switch transistor T 15 is connect with the pull-up node Q (n), and drain electrode connects with pull-down node P (n)
It connects, source electrode is connect with the low level signal VSS input terminal.
The third switching branches 430 include that sixteenmo closes pipe T16 and the 17th switch transistor T 17.
The grid that the sixteenmo closes pipe T16 is connect with second switch signal Q (n-1) input terminal, drain electrode and institute
Drop-down control node H (n) connection is stated, source electrode is connect with the low level signal VSS input terminal；And
The grid of 17th switch transistor T 17 is connect with second switch signal Q (n-1) input terminal, and drain electrode is under
Node P (n) connection is drawn, source electrode is connect with the low level signal VSS input terminal.
In the present embodiment, the grid of the 12nd switch transistor T 12 and the 13rd switch transistor T 13 with (n+1)th grade
Pull-up node Q (n+1) connection, respond the voltage signal of (n+1)th grade of the pull-up node Q (n+1).14th switch
Pipe T14 and the grid of the 15th switch transistor T 15 are connect with the pull-up node Q (n) when prime (i.e. n-th grade), and response is worked as
The voltage signal of the pull-up node Q (n) of prime.The sixteenmo closes pipe T16 and the grid of the 17th switch transistor T 17 is equal
It is connect with (n-1)th grade of pull-up node Q (n-1), the voltage signal of the pull-up node Q (n-1) of (n-1)th grade of response.Therefore pass through
The control signal, it is ensured that when prime pull-down node P (n) at (n-1)th grade, when prime and (n+1)th grade of output
Low level is persistently kept in period.
The first drop-down controlling brancher 510 includes that eighteenmo closes pipe T18 in one of the embodiments, and described the
The grid that eighteenmo closes pipe T18 is connect with first drop-down control signal CK (n+6) input terminal, drain electrode and the pull-down node P (n)
Connection, source electrode are connect with the low level signal VSS input terminal.The second drop-down controlling brancher 520 includes the 19th switch
Pipe T19, the grid of the 19th switch transistor T 19 with second drop-down control signal CK (n+5) input terminal connect, drain with it is described
Pull-down node P (n) connection, source electrode are connect with the low level signal VSS input terminal.
In the present embodiment, by the n-th+6 grades of clock signal CK (n+6) as the first drop-down control signal when prime, institute
The grid for stating eighteenmo pass pipe T18 is connect with the n-th+6 grades clock signal CK (n+6) input terminal.The n-th+5 grades of clock is believed
Number CK (n+5) as the second drop-down control signal when prime, the grid of the 19th switch transistor T 19 and the n-th+5 grades when
The connection of clock signal CK (n+5) input terminal.
Switching tube all in the application example is N type switch tube in one of the embodiments,.
The switching tube is field-effect tube or is triode in one of the embodiments,.When the switching tube is equal
When using field-effect tube or being all made of triode, it is convenient for circuit design.Further, it is also possible to according to actual design needs, portion
Divide and use field-effect tube, another uses triode.
Based on the same inventive concept, present invention also provides a kind of gate driving circuit, grid provided by the embodiments of the present application
Pole driving circuit includes cascade shift registor at different levels, and the cascade shift registor is in any of the above-described embodiment
Shift registor.Specifically, which includes N grades, and N is grid line quantity, and 2 < n < N-6.
In the present embodiment, the shift registor includes pull-up circuit 100, output circuit 200, pull-down circuit 300, first
Pull-down control circuit 400 and the second pull-down control circuit 500.
The pull-up circuit 100 connects the second output terminal of the n-th -2 grades shift registors, to respond described the n-th -2 grades
The output signal of shift registor, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node Q (n).
The output circuit 200 connects the pull-up node Q (n) and clock signal input terminal, to respond on described
The voltage signal of node Q (n) is drawn, and clock signal is supplied to the first output end and second output terminal of the shift registor.
The pull-down circuit 300 connects the pull-down node P (n-1) of (n-1)th grade of shift registor, the shift registor
The first output end G (n+4) of pull-down node P (n) and the n-th+4 grades shift registors, to respond (n-1)th grade of shift registor
Pull-down node P (n-1), the pull-down node P (n) and the n-th+4 grades shift registors, first output end voltage letter
Number, and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the shift registor first
Output end.
First pull-down control circuit 400 connects the pull-up section of high level signal VDD output end, (n+1)th grade of buffer
Point Q (n+1), the pull-up node Q (n-1) of (n-1)th grade of shift registor, the pull-up node Q (n) of the shift registor, drop-down
Control node H (n) and the pull-down node P (n), to respond the high level signal VDD, by the high level signal VDD
It is supplied to the drop-down control node H (n), the voltage signal of drop-down control node H (n) is responded, the high level is believed
Number VDD is supplied to the pull-down node P (n), and (n+1)th grade of buffer of response pull-up node Q (n+1) voltage signal,
The electricity of the voltage signal of the pull-up node Q (n-1) of (n-1)th grade of shift registor, the pull-up node Q (n) of the shift registor
Signal is pressed, the low level signal VSS is respectively supplied to the pull-down node P (n) and the drop-down control node H (n).
Second pull-down control circuit 500 connects the clock signal input terminal of n-th+5 and n+6 grades of shift registors,
Institute is respectively supplied to respond the clock signal of n-th+5 and n+6 grades of shift registors, and by the low level signal VSS
State pull-down node P (n) and the drop-down control node H (n)；
Wherein, 2 < n < N-6, N are the number of cascade shift registor, and n and N are positive integer.
In addition, in the present embodiment, the first pull-down circuit 300 of signal input part and last level Four for preceding two-stage with
The connection of initial signal input terminal.
Fig. 8 is the cascade structure schematic diagram of gate driving circuit, and Fig. 9 is the timing of each signal end of the shift registor
Figure, the work below with reference to Fig. 8 and Fig. 9 to n-th grade of shift registor in gate driving circuit provided by the embodiments of the present application
Method is illustrated, specifically with the 4th grade of shift registor in the gate driving circuit that is made of 8 shift registors
Working method is illustrated.
First stage S1, clock signal CK4 be low level signal, clock signal CK2 and CK8 be high level signal, second
The high level signal of the output of grade shift registor, the first switch tube T1 are opened, and are charged for pull-up node Q (4), pull-up section
Point Q (4) rises to high level, the second switch T2 and the third switch transistor T 3 conducting, but because CK4 is still low level,
Therefore the first output end G (4) and second output terminal F (4) keeps low level, meanwhile, respond the voltage signal of pull-up node Q (4)
The 14th switch transistor T 14 and the 15th switch transistor T 15 be also switched on, by low level signal VSS be supplied to pull-down node P (4) and
It pulls down control node H (4), therefore pull-down node P (4) keeps low potential at this time.
Second stage S2, clock signal CK4 be high level signal, clock signal CK2 and CK8 be low level signal, second
The low level signal of the output of grade shift registor, the first switch tube T1 are disconnected, but due to the presence of capacitor C, pull-up section
Point Q (4) still keeps high potential；Clock signal CK4 is high level simultaneously, due to the bootstrap effect of capacitor C
(Bootstrapping), the current potential of pull-up node Q (4) continues to increase, in response to the voltage signal of the pull-up node Q (4)
Second switch T2 and third switch transistor T 3 are connected.
Meanwhile the 14th switch transistor T 14 and the 15th switching tube of the voltage signal in response to the pull-up node Q (4)
T15 is also switched on, and low level signal VSS is supplied to pull-down node P (4) and drop-down control node H (4), therefore drop-down section at this time
Point P (4) keeps low potential, and the 8th switch transistor T 8 and the 9th switch transistor T 9 disconnect；The drop-down section of the third level shift registor
Point P (3) keeps low potential, disconnects in response to the 6th switch and the 7th switch transistor T 7 of the voltage signal of pull-down node P (3)；When
Clock signal CK8 is low level, and the output signal of the first output end G (8) of the 8th grade of shift registor is low level signal, the 4th
Switch transistor T 4 and the 5th switch transistor T 5 disconnect, to prevent from discharging to pull-up node Q (4).
Therefore, the output signal of the first output end G (4) and second output terminal F (4) is high level signal at this time.
Phase III S3, clock signal CK2, CK4 and CK8 are low level signal, and clock signal CK6 is high level.
Third level shift registor pull-down node P (3) is high level within the clock signal CK6 later half output period,
The 6th switch transistor T 6 in response to the voltage signal of pull-down node P (3) and the conducting of the 7th switch transistor T 7, to pull-up node Q (4) into
Row electric discharge, when the presence due to capacitor C, the pull-up node Q (4) still keeps high potential.
The pull-up node Q (4) is high potential simultaneously, the 12nd switch transistor T 12 in response to pull-up node Q (4) and the
Low level signal VSS is supplied to pull-down node P (4) and drop-down control node H (4), therefore this by the conducting of 13 switch transistor Ts 13
Shi Suoshu pull-down node P (4) keeps low level.
Fourth stage S4, within the first half period of fourth stage, clock signal CK1, CK2, CK3, CK4, CK5 and CK6 are equal
For low level signal, clock signal CK7 and CK8 are high level signal, therefore, corresponding pull-up node Q (3), pull-up node Q
(4) and the voltage signal of pull-up node Q (5) is low level signal, at this time the first pull-down control circuit 400 and the second drop-down control
All switching tubes in circuit processed disconnect, and the voltage signal of drop-down control node H (4) is high level voltage signal, and described the
The conducting of 11 switch transistor Ts 11, the high level signal VDD is supplied to pull-down node P (4), the voltage letter of pull-down node P (4)
Number be high level voltage signal.
Within the later half period of fourth stage, clock signal CK2, CK3, CK4, CK5, CK6 and CK7 are low level signal,
Clock signal CK1 and CK8 are high level signal, at this point, corresponding pull-up node Q (3), pull-up node Q (4) and pull-up node Q
(5) voltage signal is low level signal, and all switching tubes of the first pull-down control circuit 400 disconnect, in response to clock
The eighteenmo of signal CK1 closes pipe T18 conducting, and low level signal VSS is supplied to pull-down node P (4), pull-down node P's (4)
Voltage signal is low level voltage signal VSS.
5th stage S5, within the first half period in the 5th stage, clock signal CK3, CK4, CK5, CK6, CK7 and CK8 are
Low level signal, clock signal CK1 and CK2 are high level signal, are led in response to the eighteenmo pass pipe T18 of clock signal CK1
It is logical, it is also switched in response to the 19th switch transistor T 19 of clock signal CK2, pipe T18 and the 19th switching tube is closed by eighteenmo
Low level signal VSS is supplied to pull-down node P (4) by T19, and the voltage signal of pull-down node P (4) is low level voltage signal
VSS。
Within the later half period in the 5th stage, clock signal CK1, CK4, CK5, CK6, CK7 and CK8 are low level signal,
Clock signal CK2 and CK3 are high level signal, are connected in response to the 19th switch transistor T 19 of clock signal CK2, by low level
Signal VSS is supplied to pull-down node P (4), and the voltage signal of pull-down node P (4) is low level voltage signal VSS.
6th stage S6, within the first half period in the 6th stage, clock signal CK1, CK2, CK5, CK6, CK7 and CK8 are
Low level signal, clock signal CK3 and CK4 are high level signal, at this time the first pull-down control circuit 400 and the second drop-down control
Switching tube in circuit 500 disconnects, drop-down control node H (4) voltage signal be high level voltage signal, the described 11st
Switch transistor T 11 is connected, and the high level signal VDD is supplied to pull-down node P (4), the voltage signal of pull-down node P (4) is
High level voltage signal.
Within the later half period in the 6th stage, clock signal CK1, CK2, CK3, CK6, CK7 and CK8 are low level signal,
Clock signal CK4 and CK5 are high level signal, at this time in the first pull-down control circuit 400 and the second pull-down control circuit 500
Switching tube disconnects, and the voltage signal of drop-down control node H (4) is high level voltage signal, and the 11st switch transistor T 11 is led
It is logical, the high level signal VDD is supplied to pull-down node P (4), the voltage signal of pull-down node P (4) is high level voltage letter
Number.
To sum up, this application provides a kind of shift registor and gate driving circuits.The shift registor includes pull-up
Circuit 100, output circuit 200, pull-down circuit 300, the first pull-down control circuit 400 and the second pull-down control circuit 500.It is described
Pull-up circuit 100 connects the input signal end of the shift registor, mentions to respond input signal, and by the input signal
It supplies pull-up node Q (n).The output circuit 200 connects the pull-up node Q (n) and clock signal input terminal, to sound
The voltage signal of the pull-up node Q (n) is answered, and clock signal is supplied to the first output end and of the shift registor
Two output ends.The pull-down circuit 300 connects first pulldown signal input terminal G (n+4) input terminal, the second pulldown signal P (n-1)
Input terminal and pull-down node P (n), to respond the first pulldown signal input terminal G (n+4), the second pulldown signal P (n-1) with
And the voltage signal of the pull-down node P (n), and low level signal VSS is respectively supplied to the pull-up section of the shift registor
The first output end of point Q (n) and the shift registor.First pull-down control circuit 400, connection high level signal VDD are defeated
Outlet, second switch signal Q (n-1) input terminal, pulls up control node Q (n), is described first switch signal Q (n+1) input terminal
Pull-down node P (n) and the pull-up node Q (n), to respond the high level signal VDD, by the high level signal
VDD is supplied to the drop-down control node H (n), the voltage signal of drop-down control node H (n) is responded, by the high level
Signal VDD is supplied to the pull-down node P (n), and response first switch signal Q (n+1), second switch signal Q (n-1) and
The voltage signal of the pull-up node Q (n), and by the low level signal VSS be respectively supplied to the pull-down node P (n) and
The drop-down control node H (n).Second pull-down control circuit 500, connection the first drop-down control signal input, second
Control signal input and the pull-down node P (n) are pulled down, to respond the first drop-down control signal and the second drop-down control letter
Number, and the low level signal VSS is respectively supplied to the pull-down node P (n) and the drop-down control node H (n).This Shen
Please in, in non-output stage, the shift registor in response to the first drop-down control signal and the second drop-down control signal,
And the low level signal VSS is respectively supplied to the pull-down node P (n) and the drop-down control node H (n), to subtract
Few pull-down node P (n) is in the time of direct current high level working condition, and then reduces the threshold value of relevant thin film transistor (TFT)
A possibility that voltage drifts about, to improve noise reduction effect.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of shift registor characterized by comprising
Pull-up circuit connects the input signal end of the shift registor, to respond input signal, and by the input signal
It is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, and the voltage to respond the pull-up node is believed
Number, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, the first pulldown signal input terminal of connection, the second pulldown signal input terminal and pull-down node, to respond the
The voltage signal of one pulldown signal, the second pulldown signal and the pull-down node, and low level signal is respectively supplied to this
The pull-up node of shift registor and the first output end of the shift registor；
First pull-down control circuit, connection high level signal input terminal, first switch signal input part, the input of second switch signal
End, drop-down control node, the pull-down node and the pull-up node, to respond the high level signal, by the height
Level signal is supplied to the drop-down control node, responds the voltage signal of the drop-down control node, the high level is believed
Number it is supplied to the pull-down node, and the voltage letter of response first switch signal, second switch signal and the pull-up node
Number, and the low level signal is respectively supplied to the pull-down node and the drop-down control node；And
Second pull-down control circuit, the first drop-down of connection control signal input, the second drop-down control signal input and described
Pull-down node to respond the first drop-down control signal and the second drop-down control signal, and the low level signal is mentioned respectively
Supply the pull-down node and the drop-down control node.
2. shift registor as described in claim 1, which is characterized in that first pull-down control circuit includes:
First switch branch, connection first switch signal input part, the drop-down control node and the pull-down node, to sound
The first switch signal is answered, and the low level signal is respectively supplied to the pull-down node and drop-down control section
Point；
Second switch branch connects the pull-up node, the drop-down control node and the pull-down node, described to respond
The voltage signal of pull-up node, and the low level signal is respectively supplied to the pull-down node and drop-down control section
Point；
Third switching branches connect the second switch signal input part, the drop-down control node and the pull-down node, use
To respond the second switch signal, and the low level signal is respectively supplied to the pull-down node and drop-down control
Node；And
Drop-down input branch, connects the high level signal input terminal, the drop-down control node and the pull-down node, to
The high level signal is responded, the high level signal is supplied to the drop-down control node, and the response drop-down control
The high level signal is supplied to the pull-down node by the voltage signal of node processed.
3. shift registor as claimed in claim 2, which is characterized in that second pull-down control circuit includes:
First drop-down controlling brancher, connects the first drop-down control signal input and the pull-down node, to respond
The first drop-down control signal is stated, and the low level signal is supplied to the pull-down node；And
Second drop-down controlling brancher, connects the second drop-down control signal input and the pull-down node, to respond
The second drop-down control signal is stated, and the low level signal is supplied to the pull-down node.
4. shift registor as claimed in claim 3, which is characterized in that the pull-down circuit includes:
First drop-down branch, connects the first pulldown signal input terminal, to respond first pulldown signal, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；
Second drop-down branch, connects the second pulldown signal input terminal, to respond second pulldown signal, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；And
Third pulls down branch, connects the pull-down node, believes to respond the voltage signal of the pull-down node, and by low level
Number it is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor.
5. shift registor as claimed in claim 4, which is characterized in that the pull-up circuit includes:
First switch tube, grid and drain electrode are connect with the input signal end, and source electrode is connect with the pull-up node.
6. shift registor as claimed in claim 5, which is characterized in that the output circuit includes:
Second switch, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and the shifting
The first output end connection of position buffer；
Third switching tube, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and the shifting
The second output terminal connection of position buffer；And
Capacitor, one end are connect with the pull-up node, and the other end is connect with the first output end of the shift registor.
7. shift registor as claimed in claim 6, which is characterized in that
Described first, which pulls down branch, includes:
4th switching tube, grid are connect with the first pulldown signal input terminal, drain with it is the first of the shift registor defeated
Outlet and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
5th switching tube, grid are connect with the first pulldown signal input terminal, drain electrode connect with the pull-up node, source electrode and
The low level voltage signal input part connection；
Described second, which pulls down branch, includes:
6th switching tube, grid are connect with the second pulldown signal input terminal, drain with it is the first of the shift registor defeated
Outlet and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
7th switching tube, grid are connect with the second pulldown signal input terminal, drain electrode connect with the pull-up node, source electrode and
The low level voltage signal input part connection；
The third pulls down branch
8th switching tube, grid are connect with the pull-down node, first output end and institute of the drain electrode with the shift registor
Capacitance connection is stated, source electrode is connect with the low level voltage signal input part；And
9th switching tube, grid are connect with the pull-down node, and drain electrode is connect with the pull-up node, source electrode and the low level
Voltage signal inputs connection.
8. shift registor as claimed in claim 7, which is characterized in that
The drop-down inputs branch
Tenth switching tube, grid and drain electrode are connect with the high level signal input terminal, source electrode and the drop-down control node
Connection；And
11st switching tube, grid are connect with the drop-down control node, and drain electrode is connect with the high level signal input terminal, source
Pole is connect with the pull-down node；
The first switch branch includes:
12nd switching tube, grid are connect with the first switch signal input part, and drain electrode is connect with the drop-down control node,
Source electrode is connect with the low level signal input terminal；And
13rd switching tube, grid are connect with the first switch signal input part, and drain electrode is connect with pull-down node, source electrode and institute
State the connection of low level signal input terminal；
The second switch branch includes:
14th switching tube, grid are connect with the pull-up node, drain electrode connect with the drop-down control node, source electrode with it is described
The connection of low level signal input terminal；And
15th switching tube, grid are connect with the pull-up node, and drain electrode is connect with pull-down node, and source electrode and the low level are believed
The connection of number input terminal；
The third switching branches include:
Sixteenmo closes pipe, and grid is connect with the second switch signal input part, and drain electrode is connect with the drop-down control node,
Source electrode is connect with the low level signal input terminal；And
17th switching tube, grid are connect with the second switch signal input part, and drain electrode is connect with pull-down node, source electrode and institute
State the connection of low level signal input terminal.
9. shift registor as claimed in claim 8, which is characterized in that
The first drop-down controlling brancher includes that eighteenmo closes pipe, and grid connect with the first drop-down control signal input, leaks
Pole is connect with the pull-down node, and source electrode is connect with the low level signal input terminal；And
The second drop-down controlling brancher includes the 19th switching tube, and grid connect with the second drop-down control signal input, leaks
Pole is connect with the pull-down node, and source electrode is connect with the low level signal input terminal.
10. a kind of gate driving circuit, including cascade shift registor at different levels, which is characterized in that the shift registor packet
It includes:
Pull-up circuit connects the second output terminal of the n-th -2 grades shift registors, to respond the n-th -2 grades shift registors
Output signal, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, and the voltage to respond the pull-up node is believed
Number, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, connect the pull-down node of (n-1)th grade of shift registor, the pull-down node of the shift registor and n-th+
First output end of 4 grades of shift registors, to respond the voltage letter of the first output end of the n-th+4 grades shift registors output
Number, and low level signal is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；
First pull-down control circuit, connection high level signal input terminal, the pull-up node of (n+1)th grade of buffer, (n-1)th grade of displacement
The pull-up node of buffer, the pull-up node of the shift registor, drop-down control node and the pull-down node, to respond
The high level signal is supplied to the drop-down control node by the high level signal, responds the drop-down control node
The high level signal is supplied to the pull-down node by voltage signal, and respond the pull-up node of (n+1)th grade of buffer
The voltage of the pull-up node of voltage signal, the voltage signal of the pull-up node of (n-1)th grade of shift registor, the shift registor
The low level signal is respectively supplied to the pull-down node and the drop-down control node by signal；And
The clock signal input terminal of second pull-down control circuit, connection n-th+5 and n+6 grades of shift registors, to respond n-th
The clock signal of+5 and n+6 grades of shift registor, and the low level signal is respectively supplied to the pull-down node and institute
State drop-down control node；
Wherein, 2 < n < N-6, N is grid line quantity, and n and N are positive integer.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110459191A (en) * | 2019-08-26 | 2019-11-15 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display device |
| CN111192550A (en) * | 2020-02-26 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| WO2021072750A1 (en) * | 2019-10-18 | 2021-04-22 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, gate drive circuit, and display device |
| CN113421516A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and display panel |
| CN114241973A (en) * | 2021-08-11 | 2022-03-25 | 友达光电股份有限公司 | Gate driving circuit and display panel comprising same |
| US11645981B2 (en) | 2021-07-08 | 2023-05-09 | Lg Display Co., Ltd. | Gate driver and display panel including the same |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604551A (en) * | 2008-06-10 | 2009-12-16 | 北京京东方光电科技有限公司 | Shift register and grid line drive device thereof |
| CN102968950A (en) * | 2012-11-08 | 2013-03-13 | 京东方科技集团股份有限公司 | Shifting register unit and array substrate gate drive device |
| CN103489484A (en) * | 2013-09-22 | 2014-01-01 | 京东方科技集团股份有限公司 | Shifting register unit and gate drive circuit |
| CN104240765A (en) * | 2014-08-28 | 2014-12-24 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, gate drive circuit and display device |
| CN104575430A (en) * | 2015-02-02 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, drive method thereof, gate drive circuit and display device |
| CN105374314A (en) * | 2015-12-24 | 2016-03-02 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof as well as grid driving circuit and display device |
| CN106652875A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, grid integrated drive circuit and display device |
| CN107705762A (en) * | 2017-09-27 | 2018-02-16 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate drive apparatus and display device |
| CN108648686A (en) * | 2018-07-27 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and gate driving circuit |
| CN108831403A (en) * | 2018-08-29 | 2018-11-16 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108986732A (en) * | 2018-08-13 | 2018-12-11 | 惠科股份有限公司 | shift register circuit and display device |
| CN109064964A (en) * | 2018-09-18 | 2018-12-21 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
-
2018
- 2018-12-26 CN CN201811600791.6A patent/CN109448656B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604551A (en) * | 2008-06-10 | 2009-12-16 | 北京京东方光电科技有限公司 | Shift register and grid line drive device thereof |
| CN102968950A (en) * | 2012-11-08 | 2013-03-13 | 京东方科技集团股份有限公司 | Shifting register unit and array substrate gate drive device |
| CN103489484A (en) * | 2013-09-22 | 2014-01-01 | 京东方科技集团股份有限公司 | Shifting register unit and gate drive circuit |
| CN104240765A (en) * | 2014-08-28 | 2014-12-24 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, gate drive circuit and display device |
| CN104575430A (en) * | 2015-02-02 | 2015-04-29 | 京东方科技集团股份有限公司 | Shifting register unit, drive method thereof, gate drive circuit and display device |
| CN105374314A (en) * | 2015-12-24 | 2016-03-02 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof as well as grid driving circuit and display device |
| CN106652875A (en) * | 2017-01-04 | 2017-05-10 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof, grid integrated drive circuit and display device |
| CN107705762A (en) * | 2017-09-27 | 2018-02-16 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate drive apparatus and display device |
| CN108648686A (en) * | 2018-07-27 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and gate driving circuit |
| CN108986732A (en) * | 2018-08-13 | 2018-12-11 | 惠科股份有限公司 | shift register circuit and display device |
| CN108831403A (en) * | 2018-08-29 | 2018-11-16 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN109064964A (en) * | 2018-09-18 | 2018-12-21 | 合肥鑫晟光电科技有限公司 | Shift register cell, driving method, gate driving circuit and display device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11176863B2 (en) | 2019-08-26 | 2021-11-16 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit and display device |
| CN110459191A (en) * | 2019-08-26 | 2019-11-15 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display device |
| CN110459191B (en) * | 2019-08-26 | 2021-11-16 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| US11710435B2 (en) | 2019-10-18 | 2023-07-25 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit and driving method thereof, gate driving circuit, and display device |
| WO2021072750A1 (en) * | 2019-10-18 | 2021-04-22 | 京东方科技集团股份有限公司 | Shift register unit and driving method therefor, gate drive circuit, and display device |
| CN113168802A (en) * | 2019-10-18 | 2021-07-23 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN113168802B (en) * | 2019-10-18 | 2023-05-09 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, grid driving circuit and display device |
| CN111192550B (en) * | 2020-02-26 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| US11257411B2 (en) | 2020-02-26 | 2022-02-22 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate driver on array (GOA) circuit and display panel |
| CN111192550A (en) * | 2020-02-26 | 2020-05-22 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and display panel |
| CN113421516A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and display panel |
| US11645981B2 (en) | 2021-07-08 | 2023-05-09 | Lg Display Co., Ltd. | Gate driver and display panel including the same |
| TWI822163B (en) * | 2021-07-08 | 2023-11-11 | 南韓商Ｌｇ顯示器股份有限公司 | Gate driver and display panel including the same |
| CN114241973A (en) * | 2021-08-11 | 2022-03-25 | 友达光电股份有限公司 | Gate driving circuit and display panel comprising same |
| CN114241973B (en) * | 2021-08-11 | 2023-11-03 | 友达光电股份有限公司 | Gate driving circuit and display panel comprising same |
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