CN109872699A - Shift register, gate driving circuit and display device - Google Patents
Shift register, gate driving circuit and display device Download PDFInfo
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- CN109872699A CN109872699A CN201910299331.2A CN201910299331A CN109872699A CN 109872699 A CN109872699 A CN 109872699A CN 201910299331 A CN201910299331 A CN 201910299331A CN 109872699 A CN109872699 A CN 109872699A
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Abstract
Present disclose provides a kind of shift register, which includes: pre-charge module, for being charged to pull-up node in pre-charging stage；Pull-up module, in output stage, the clock signal transmission that clock signal terminal is exported to the first output end and second output terminal；Reseting module, for the first power supply being connected to pull-up node, to be resetted to pull-up node in reseting stage；Pull-down control module, under the control of the second source signal of second source output, the first pull-down node to be written in second source signal in the noise reduction stage；Noise reduction module, for in the noise reduction stage, under the control of the second source signal of the first pull-down node output, pull-up node to be written in the third power supply signal that third power supply is exported, so that pull-up module does not work under the control of the third power supply signal of pull-up node output in the noise reduction stage.The disclosure additionally provides gate driving circuit and display device.
Description
Technical field
The embodiment of the present disclosure is related to field of display technology, in particular to a kind of shift register, gate driving circuit and aobvious
Showing device.
Background technique
For liquid crystal display panel during display, gate driving circuit is used to generate the gated sweep voltage of pixel, passes through
Gate driving circuit exports gated sweep signal, progressively scans each row pixel.Wherein, array substrate gate driving (Gate
Driver On Array, referred to as: GOA) it is a kind of technology being integrated in gate driving circuit in TFT substrate, each GOA is mono-
Scanning signal is successively passed to next GOA unit as a shift register by member, opens the corresponding TFT of every row pixel line by line
Switch completes the data-signal input of pixel unit.
Summary of the invention
The embodiment of the present disclosure provides a kind of shift register, gate driving circuit and display device.
In a first aspect, the embodiment of the present disclosure provides a kind of shift register, which includes:
Pre-charge module is connect with signal input part and pull-up node, is used in pre-charging stage, in signal input part
Under the control of the input signal of output, charge to the pull-up node；
Pull-up module connect with the pull-up node, clock signal terminal, the first output end and second output terminal, is used for
In output stage, under the control of the voltage of pull-up node output, the clock signal that the clock signal terminal is exported is passed
Transport to first output end and the second output terminal；
Reseting module is connect with reset signal end, the first power supply and the pull-up node, in reseting stage,
Under the control of the reset signal of the reset signal end output, first power supply is connected to the pull-up node, to institute
Pull-up node is stated to be resetted；
Pull-down control module is connect with second source and the first pull-down node, is used in the noise reduction stage, described second
Under the control of the second source signal of power supply output, first pull-down node is written into the second source signal；
Noise reduction module is connect with the pull-up node, first pull-down node and third power supply, in noise reduction rank
Section, under the control of the second source signal of first pull-down node output, third power supply signal that third power supply is exported
The pull-up node is written, so that the pull-up module is in the noise reduction stage, in the third power supply signal of pull-up node output
Control under do not work.
In some embodiments, the pre-charge module includes the first transistor, the first pole of the first transistor and
Control electrode is connected to the signal input part, and the second pole of the first transistor is connected to the pull-up node.
In some embodiments, the reseting module includes second transistor, the control electrode connection of the second transistor
To the reset signal end, the first pole of the second transistor is connected to the pull-up node, and the of the second transistor
Two poles are connected to first power supply.
In some embodiments, the pull-up module includes third transistor, the 15th transistor and capacitor；
First pole of the third transistor is connected to the clock signal terminal, the second pole connection of the third transistor
To the second output terminal, the control electrode of the third transistor is connected to the pull-up node；
First pole of the 15th transistor is connected to the clock signal terminal, the second pole of the 15th transistor
It is connected to first output end, the control electrode of the 15th transistor is connected to the pull-up node；
The first end of the capacitor is connected to the pull-up node, and the second end of the capacitor is connected to second output
End.
In some embodiments, the noise reduction module includes the 16th transistor, the first pole of the 16th transistor
It is connect with the third power supply, the second pole of the 16th transistor is connect with the pull-up node, the 16th crystal
The control electrode of pipe is connect with first pull-down node.
In some embodiments, the noise reduction module also with first power supply, first output end, described second defeated
Outlet is connected with the 4th power supply；
The noise reduction module was also used in the noise reduction stage, in the control of the second source signal of first pull-down node output
Under system, the pull-up node and first output end is written into the first power supply signal of first power supply output, it will be described
The second output terminal is written in 4th power supply signal of the 4th power supply output.
In some embodiments, the noise reduction module further includes the tenth transistor, the tenth two-transistor and the 13rd crystal
Pipe；
First pole of the tenth transistor is connected to the pull-up node, and the second pole of the tenth transistor is connected to
The control electrode of first power supply, the tenth transistor is connected to first pull-down node；
First pole of the tenth two-transistor is connected to first output end, the second pole of the tenth two-transistor
It is connected to first power supply, the control electrode of the tenth two-transistor is connected to first pull-down node；
First pole of the 13rd transistor is connected to the second output terminal, the second pole of the 13rd transistor
It is connected to the 4th power supply, the control electrode of the 13rd transistor is connected to first pull-down node.
In some embodiments, the shift register further include:
Pull-down module, with the pull-up node, first power supply, first pull-down node and the second pull-down node
Connection is used in output stage, under the control of the voltage of pull-up node output, by the first of first power supply output
First pull-down node and second pull-down node is written in power supply signal.
In some embodiments, the pull-down module includes the 6th transistor and the 8th transistor；
First pole of the 6th transistor is connected to first pull-down node, and the second pole of the 6th transistor connects
It is connected to first power supply, the control electrode of the 6th transistor is connected to the pull-up node；
First pole of the 8th transistor is connected to second pull-down node, and the second pole of the 8th transistor connects
It is connected to first power supply, the control electrode of the 8th transistor is connected to the pull-up node.
In some embodiments, the pull-down control module is also connect with the second pull-down node, the pull-down control module
Including the 5th transistor and the 9th transistor；
First pole of the 5th transistor is connected to first pull-down node, and the second pole of the 5th transistor connects
It is connected to the second source, the control electrode of the 5th transistor is connected to second pull-down node；
First pole of the 9th transistor and control electrode are respectively connected to the second source, the 9th transistor
Second pole is connected to second pull-down node.
Second aspect, the embodiment of the present disclosure also provide a kind of gate driving circuit, which includes: m grade
The above-mentioned shift register of connection, in addition to preceding three-level shift register, the signal input part and n-th-of n-th grade of shift register
First output end of 3 grades of shift register connects, wherein m is more than or equal to 4, n and is greater than 3 and is less than or equal to m.
The third aspect, the embodiment of the present disclosure also provide a kind of display device, which includes above-mentioned gate driving
Circuit.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram for shift register that the embodiment of the present disclosure provides；
Fig. 2 is a kind of schematic diagram of specific implementation of shift register provided by the embodiment of the present disclosure；
Fig. 3 is a kind of working timing figure of the shift register in Fig. 2.
Specific embodiment
To make those skilled in the art more fully understand the technical solution of the disclosure, the disclosure is mentioned with reference to the accompanying drawing
Shift register, gate driving circuit and the display device of confession are described in detail.
Fig. 1 is a kind of structural schematic diagram for shift register that the embodiment of the present disclosure provides, as shown in Figure 1, the displacement is posted
Storage includes: pre-charge module 1, pull-up module 2, reseting module 3, pull-down control module 4 and noise reduction module 5.
Wherein, pre-charge module 1 is connect with signal input part INPUT and pull-up node PU, in pre-charging stage,
Under the control of the input signal of signal input part INPUT output, charge to pull-up node PU.
Pull-up module 2 and pull-up node PU, clock signal terminal CLK, the first output end OC and second output terminal OUTPUT connect
It connects, in output stage, under the control of the voltage of pull-up node PU output, the clock that clock signal terminal CLK is exported to be believed
Number it is transmitted to the first output end OC and second output terminal OUTPUT.
Reseting module 3 is connect with reset signal end Reset, the first power supply G1 and pull-up node PU, is used in reseting stage,
Under the control of the reset signal of reset signal end Reset output, the first power supply G1 is connected to pull-up node PU, to pull-up
Node PU is resetted.
Pull-down control module 4 is connect with second source G2 and the first pull-down node PD, is used in the noise reduction stage, in the second electricity
The second source signal V of source G2 outputGHControl under, by second source signal VGHThe first pull-down node PD is written.
Noise reduction module 5 is connect with pull-up node PU, the first pull-down node PD and third power supply G3, is used in the noise reduction stage,
Under the control of the second source signal of the first pull-down node PD output, by the third power supply signal V of third power supply G3 outputGNIt writes
Enter pull-up node PU, so that pull-up module 2 is in the noise reduction stage, in the third power supply signal V of pull-up node PU outputGNControl under
It does not work.
In the embodiments of the present disclosure, the first output end is used to cascade the signal input part of other shift registers, to constitute
Gate driving circuit, second output terminal with the controlling grid scan line of display device for connecting, to transmit gate drive signal.Pass through
First output end and second output terminal are set, so that pixel is separated with gate driving circuit, reduce the every of gate driving circuit
Load corresponding to a output end can further reduce the size of related transistor, reduce the power consumption of gate driving circuit.
On the other hand, in the noise reduction stage of present frame, due to outside or inside, if pull-up node generates noise (electricity
The irregular lifting in position), it will lead to the normal output stage in next frame, the clock that clock signal terminal is exported by pull-up module
Can completely is not output to the first output end to signal, so that pixel in the ranks charge differential, causes to show that band is bad, or make
Pixel in the ranks fill by mistake, causes to show that horizontal black line is bad.Therefore in the embodiments of the present disclosure, noise reduction module is in the noise reduction stage,
Under the control of the second source signal of one pull-down node output, the third power supply signal write-in pull-up that third power supply is exported is saved
Point, so that pull-up module does not work, thus effectively in the noise reduction stage under the control of the third power supply signal of pull-up node output
Pull-up node clock signal terminal caused by generating noise (the irregular lifting of current potential) in the noise reduction stage of present frame is avoided to exist
Clock signal the problem of can completely is not output to the first output end of the normal output stage output of next frame, avoid pixel column
Between the display band that occurs of charge differential it is bad, or avoid pixel in the ranks the wrong display horizontal black line for filling appearance be bad.
In the embodiments of the present disclosure, the input exported in pre-charging stage, pre-charge module 1 in signal input part INPUT
It under the control of signal, charges to pull-up node PU, the current potential of pull-up node PU is pulled to first voltage V1.
In the embodiments of the present disclosure, pull-up module 2 is specifically used in output stage, in the first electricity of pull-up node PU output
Under the control of pressure, clock signal transmission that clock signal terminal CLK is exported to the first output end OC and second output terminal OUTPUT,
Meanwhile the current potential of pull-up node PU is further pulled to second voltage V2, wherein second voltage is greater than first voltage.
In some embodiments, as shown in Figure 1, shift register further includes pull-down module 6, pull-down module 6 and pull-up are saved
Point PU, the first power supply G1, the first pull-down node PD and the second pull-down node PD_CN connection, for being saved in pull-up in output stage
Under the control of the voltage of point PU output, by the first power supply signal V of the first power supply G1 outputGL1Be written the first pull-down node PD and
Second pull-down node PD_CN.In such cases, the voltage of pull-up node PU output is the second voltage V2.
In some embodiments, as shown in Figure 1, pull-down control module 4 is also connect with the second pull-down node PD_CN, drop-down
Control module 4 was also used in the noise reduction stage, in the second source signal V of second source G2 outputGHControl under, by second source
Signal VGHThe second pull-down node PD_CN is written.
In some embodiments, as shown in Figure 1, noise reduction module 5 also with the first power supply G1, the first output end OC, second defeated
Outlet OUTPUT and the 4th power supply G4 connection.Noise reduction module 5 was also used in the noise reduction stage, the of the first pull-down node PD output
Two power supply signal VGHControl under, by the first power supply G1 export the first power supply signal VGL1It is defeated that pull-up node PU and first is written
Outlet OC, the 4th power supply signal V that the 4th power supply G4 is exportedGL2Be written second output terminal OUTPUT, with to pull-up node PU,
First output end OC and second output terminal OUTPUT carries out noise reduction.
Fig. 2 is a kind of schematic diagram of specific implementation of shift register provided by the embodiment of the present disclosure, some
In embodiment, as shown in Fig. 2, pre-charge module 1 includes the first transistor M1, the first pole of the first transistor M1 and control electrode are equal
It is connected to signal input part INPUT, the second pole of the first transistor M1 is connected to pull-up node PU.
In some embodiments, as shown in Fig. 2, reseting module 3 includes second transistor M2, the control of second transistor M2
Pole is connected to reset signal end Reset, and the first pole of second transistor M2 is connected to pull-up node PU, and the of second transistor M2
Two poles are connected to the first power supply G1.
In some embodiments, as shown in Fig. 2, pull-up module 2 include third transistor M3, the 15th transistor M15 and
Capacitor C1.
Wherein, the first pole of third transistor M3 is connected to clock signal terminal CLK, the second pole connection of third transistor M3
To second output terminal OUTPUT, the control electrode of third transistor M3 is connected to pull-up node PU；The first of 15th transistor M15
Pole is connected to clock signal terminal CLK, and the second pole of the 15th transistor M15 is connected to the first output end OC, the 15th transistor
The control electrode of M15 is connected to pull-up node PU；The first end of capacitor C1 is connected to pull-up node PU, the second end connection of capacitor C1
To second output terminal OUTPUT.
In some embodiments, as shown in Fig. 2, noise reduction module 5 includes the 16th transistor M16, the 16th transistor M16
The first pole connect with third power supply G3, the second pole of the 16th transistor M16 is connect with pull-up node PU, the 16th transistor
The control electrode of M16 is connect with the first pull-down node PD.It can be appreciated that in the second pole of the 16th transistor M16 and pull-up module 2
The 15th transistor M15 control electrode connection.
In some embodiments, as shown in Fig. 2, noise reduction module 5 further includes the tenth transistor M10, the tenth two-transistor M12
With the 13rd transistor M13.
Wherein, the first pole of the tenth transistor M10 is connected to pull-up node PU, the second pole connection of the tenth transistor M10
To the first power supply G1, the control electrode of the tenth transistor M10 is connected to the first pull-down node PD；The first of tenth two-transistor M12
Pole is connected to the first output end OC, and the second pole of the tenth two-transistor M12 is connected to the first power supply G1, the tenth two-transistor M12
Control electrode be connected to the first pull-down node PD；The first pole of 13rd transistor M13 is connected to second output terminal OUTPUT, the
The second pole of 13 transistor M13 is connected to the 4th power supply G4, and the control electrode of the 13rd transistor M13 is connected to the first drop-down section
Point PD.
In some embodiments, as shown in Fig. 2, pull-down module 6 includes the 6th transistor M6 and the 8th transistor M8.
Wherein, the first pole of the 6th transistor M6 is connected to the first pull-down node PD, and the second pole of the 6th transistor M6 connects
It is connected to the first power supply G1, the control electrode of the 6th transistor M6 is connected to pull-up node PU；The first pole of 8th transistor M8 connects
To the second pull-down node PD_CN, the second pole of the 8th transistor M8 is connected to the first power supply G1, the control electrode of the 8th transistor M8
It is connected to pull-up node PU.
In some embodiments, as shown in Fig. 2, pull-down control module 4 includes the 5th transistor M5 and the 9th transistor M9.
Wherein, the first pole of the 5th transistor M5 is connected to the first pull-down node PD, and the second pole of the 5th transistor M5 connects
It is connected to second source G2, the control electrode of the 5th transistor M5 is connected to the second pull-down node PD_CN；The first of 9th transistor M9
Pole and control electrode are respectively connected to second source G2, and the second pole of the 9th transistor M9 is connected to the second pull-down node PD_CN.
Fig. 3 is a kind of working timing figure of the shift register in Fig. 2, below with reference to Fig. 2 and Fig. 3, is implemented to the disclosure
The working principle of shift register provided by example is described in detail.
In practical applications, shift register can form gate driving electricity by cascade mode in the embodiment of the present disclosure
Road.In some embodiments, gate driving circuit is cascaded by m shift register, in addition to preceding three-level shift register,
The signal input part of n-th grade of shift register is connect with the first output end of the n-th -3 grades of shift register, wherein m, n are
Positive integer, m are more than or equal to 4, n and are greater than 3 and are less than or equal to m.Wherein, which is applied in display device, is used for
The controlling grid scan line of display device is progressively scanned, is shown being realized in data-signal writing pixel.
By taking shift register is n-th grade of shift register as an example, to shift register provided by the embodiment of the present disclosure
Working principle is described in detail.
For n-th grade of shift register, as shown in Figures 2 and 3, in pre-charging stage T1, the first transistor M1 is in signal
It is connected under the control of the input signal of input terminal INPUT output, wherein the input signal of signal input part INPUT output is height
Level signal.In some embodiments, the input signal of signal input part INPUT output is the of the n-th -3 grades shift registers
The output signal of one output end OC (n-3) output, the output of the first output end OC (n-3) output of the n-th -3 grades shift registers
Signal is high level signal.
At this point, the input signal of signal input part INPUT output passes through the first transistor M1 write-in pull-up section after conducting
Point PU, so that the current potential of pull-up node PU is pulled to first voltage V1, to charge to capacitor C1.Meanwhile it being pre-charged
Stage T1, since the voltage of pull-up node PU is raised, so that the 6th transistor M6 and the 8th transistor M8 are defeated in pull-up node
It is connected under the control of voltage (first voltage V1) out, the first power supply signal V of the first power supply G1 outputGL1Pass through the of conducting
First power supply signal V of six transistor M6 write-in the first pull-down node PD, the first power supply G1 outputGL1It is brilliant by the 8th of conducting the
The second pull-down node PD_CN is written in body pipe M8, wherein the first power supply signal V of the first power supply G1 outputGL1For low level signal,
Such as -8V, the current potential of the current potential of the first pull-down node PD and the second pull-down node PD_CN is dragged down.
On the other hand, it is exported in pre-charging stage T1, third transistor M3 and the 15th transistor M15 in pull-up node PU
Voltage (first voltage V1) control under be connected, but due to clock signal terminal CLK output clock signal be low level signal,
So when the first output end OC and second output terminal OUTPUT export low level signal.
In output stage T2, the input signal of signal input part INPUT output is low level signal, and the first transistor M1 is closed
It closes, third transistor M3 is connected under the control for the voltage (first voltage V1) that pull-up node PU is exported, the 15th transistor M15
It is connected under the control of the voltage (first voltage V1) of pull-up node PU output, the clock signal of clock signal terminal CLK output is logical
The 15th transistor M15 for crossing conducting is transmitted to the first output end OC, and the clock signal of clock signal terminal CLK output passes through conducting
Third transistor M3 be transmitted to second output terminal OUTPUT, wherein first voltage V1 be high level signal, clock signal terminal
The clock signal of CLK output is high level signal.It is given at this point, the first output end OC exports the clock signal (high level signal)
Cascade shift register signal input part, second output terminal OUTPUT exports the clock signal (high level signal) and gives
Connected controlling grid scan line, to realize the display output of the cascaded-output and pixel region of gate driving circuit.
At the same time, in output stage T2, since the clock signal (high level signal) of clock signal terminal CLK output passes through
The second end (second output terminal OUTPUT) of the third transistor M3 write-in capacitor C1 of conducting, in the work of the bootstrap effect of capacitor C1
Under, the current potential of the first end (pull-up node PU) of capacitor C1 is further raised, at this point, the current potential of pull-up node PU is pulled up
To second voltage V2, wherein second voltage V2 is high level signal.At the same time, in output stage T2, due to pull-up node PU
Current potential continue to be lifted, therefore, voltage that the 6th transistor M6 and the 8th transistor M8 are exported in pull-up node PU (the second electricity
Pressure V2) control under tend to remain on so that the first power supply VGL1 continue to the first pull-down node PD be written the first power supply letter
Number (low level signal), i.e. the first pull-down node PD keep low level signal output state.
It is connected under the control of the reset signal end Reset reset signal exported in reseting stage T3, second transistor M2,
Wherein, reset signal is high level signal.At this point, pull-up node PU and the first power supply G1 is connected by the second transistor M2 of conducting
It is logical, the first power supply signal V of the first power supply G1 outputGL1Pull-up node PU, the current potential of pull-up node PU is written in (low level signal)
It is pulled low to the first power supply signal VGL1, to realize the reset of pull-up node PU.At this point, the 6th transistor M6 and the 8th crystal
Pipe M8 is closed.
In the noise reduction stage, second source signal V that the 9th transistor M9 is exported in second source G2GHControl under be connected,
Wherein, second source signal VGHFor high level signal.At this point, the second source signal V of second source G2 outputGH(high level letter
Number) by the 9th transistor M9 the second pull-down node PD_CN of write-in of conducting, the current potential of the second pull-down node PD_CN is raised,
Voltage (the second source signal V that 5th transistor M5 is exported in the second pull-down node PD_CNGH) control under be connected, second electricity
The second source signal V of source G2 outputGHThe first pull-down node PD is written by the 5th transistor M5 of conducting in (high level signal),
At this point, the current potential of the first pull-down node PD is raised, the first pull-down node PD exports high level signal.
At the same time, the tenth transistor M10 is under the control for the voltage (high level signal) that the first pull-down node PD is exported
The tenth transistor M10 connection of conducting, pull-up node PU and the first power supply G1 by conducting, the first electricity of the first power supply G1 output
Source signal VGL1Pull-up node PU is written, to carry out noise reduction to pull-up node PU；Meanwhile the tenth two-transistor M12 under first
It draws and is connected under the control of the voltage (high level signal) of node PD output, the first output end OC and the first power supply G1 pass through conducting
Tenth two-transistor M12 connection, the first power supply signal V of the first power supply G1 outputGL1The first output end OC is written, thus to
One output end OC carries out noise reduction；Meanwhile the 13rd voltage (high level signal) for being exported in the first pull-down node PD of transistor M13
Control under be connected, the 13rd transistor M13 connection of second output terminal OUTPUT and the 4th power supply G4 by conducting, the 4th electricity
4th power supply signal V of source G4 outputGL2Second output terminal OUTPUT is written, so that noise reduction is carried out to second output terminal OUTPUT,
Wherein, the 4th power supply signal VGL2For low level signal, the 4th power supply signal VGL2Less than the first power supply signal VGL1, such as VGL2
=-10V, VGL1=-8V.At this point, the voltage V of the first output end OCOCFirst power supply signal V of the=the first power supply outputGL1, second
The voltage V of output end OUTPUTOUTPUTEqual to the 4th power supply signal V of the 4th power supply outputGL2。
Meanwhile the 16th transistor M16 led under the control for the voltage (high level signal) that the first pull-down node PD is exported
It is logical, the third power supply signal V of third power supply G3 outputGNThe 15th transistor M15 is written by the 16th transistor M16 of conducting
Control electrode (pull-up node PU), further to pull-up node PU carry out noise reduction, at this point, the control electrode of the 15th transistor M15
Voltage Vg=VGN=VPU, VPUFor the voltage of pull-up node PU, the voltage V of the second pole of the 15th transistor M15s=VOC=
VGL1, wherein the third power supply signal V of third power supply G3 outputGNEqual to the 4th power supply signal V of the 4th power supply G4 outputGL2, therefore
The gate source voltage V of 15th transistor M15gs=Vg-Vs=VGN-VGL1=VGL2-VGL1<Vth=0, wherein VthIt is the described tenth
The threshold voltage of five transistor M15, at this point, the 15th transistor M15 is in close state and (does not work).Therefore, in noise reduction rank
Section T4, is in high level signal state in the current potential of the first pull-down node PD, as long as third power supply G3 passes through the 16th of conducting
Transistor M16 persistently exports third power supply signal VGNTo the control electrode of the 15th transistor M15, then the 15th transistor M15
It thoroughly will preferably close, so as to effectively solve the 15th transistor M15 in the electric leakage drifting problem in noise reduction stage.
It should be noted that if being not provided with the 16th transistor M16, in noise reduction stage T4, due to the tenth transistor M10's
It acts on, is in low level (V on the potential theory of pull-up node PUGL1) state, but due to clock signal terminal CLK output
It is periodic square-wave signal, and lasting output, add between third transistor M3 control electrode and the first pole (or control electrode
Between the second pole) formed capacitor boot strap, cause pull-up node PU to will appear the noise of very little, i.e. pull-up node PU
Current potential there is irregular lifting, inevitably will lead to the 15th transistor M15 pipe in this way in the noise reduction stage, due to pull-up
The current potential of node PU have it is irregular lift, lead to the gate source voltage V of the 15th transistor M15gs=Vg-Vs=VPU-VGL1> 0,
VPUFor the voltage of pull-up node PU, the 15th transistor M15 will lead to its threshold voltage V in this casethGenerate drift, M15
In the presence of drift electrical leakage problems, and due to the difference and display device of pixel region and the payload size of gate driving circuit region
Narrow frame etc. require, the size of the 15th transistor M15 is generally less than normal, threshold voltage VthIt is more easier to cause after generating drift
In the normal output stage of next frame, can completely is not output to the first output end OC to the voltage of clock signal terminal output, thus
Be easy to cause charge differential in the ranks, cause show band it is bad, or cause in the ranks mistake fill so that display horizontal black line it is bad.
Therefore, in the embodiments of the present disclosure, by the way that the 16th transistor M16 is arranged in noise reduction module 5, in noise reduction
In the stage, under the control of the voltage of the first pull-down node PD output, the third power supply signal write-in that third power supply is exported is pulled up
The control electrode of 15th transistor M15 of module 2, the 15th transistor M15 of control does not work (closing), thus when effectivelying prevent
In the clock signal of the normal output stage output of next frame, can completely is not output to the first output end to clock signal end, avoids picture
The element display band that in the ranks charge differential occurs is bad, or avoids pixel in the ranks the wrong display horizontal black line for filling appearance is bad.
In the embodiments of the present disclosure, the quantity of pull-down control module 4 is 1 or 2, the quantity of pull-down module 6 be 1 or
2.Fig. 2 illustrate only the quantity of pull-down control module 4 be 1, the case where quantity of pull-down module 6 is 1, in such cases, ginseng
Fig. 3 is seen, due to the second source signal V of second source G2 outputGHFor periodic square-wave signal, therefore, in noise reduction stage T4,
The voltage and second source signal V of pull-down node PDGHIt is identical, as periodic square-wave signal, i.e., in noise reduction stage, drop-down section
Point PD has the time of half to be in high level state.
When the quantity of pull-down control module 4 is 2, and the quantity of pull-down module 6 is 2, a pull-down control module 4 is right
The second source signal V for the second source G2 output answeredGHFor periodic square wave signal shown in Fig. 3, another drop-down control mould
The second source signal V of the corresponding second source G2 of block 4 outputGHWith V shown in Fig. 3GHSignal it is opposite.Therefore, by this two
The control of a pull-down control module 4 may make pull-down node PD to be constantly in high level state, i.e. Fig. 3 in noise reduction stage T4
Shown in state.
In the embodiments of the present disclosure, before next frame picture is shown to, which repeats always noise reduction rank
Section constantly carries out noise reduction process.
In the embodiments of the present disclosure, as shown in Fig. 2, reseting module 3 further includes the 7th transistor M7, the 7th transistor M7's
First pole is connected to pull-up node PU, and the second pole of the 7th transistor M7 is connected to the first power supply G1, the control of the 7th transistor M7
Pole processed is connected to initializing signal end TRST, and the 7th transistor M7 opens for realizing Total Reset function in each frame
When (before the first row picture element scan), control of the 7th transistor M7 in the initializing signal end TRST initializing signal exported
Lower conducting, wherein initializing signal is the 7th transistor of high level signal, the first power supply G1 and pull-up node PU by conducting
M7 connection, the first power supply signal V of the first power supply G1 outputGL1Pull-up node PU is written, to pull-up node PU and output end drop
It makes an uproar.
In the embodiments of the present disclosure, the 4th power supply G4 is also used to realize XON function, when repeated switching, passes through
4th power supply signal V of the 4th power supply G4 outputGL2Height is set, meanwhile, the 13rd transistor M13 is opened, second output terminal is passed through
The opening of every a line controlling grid scan line is realized in OUTPUT output, to realize the effect of noise (DC), electrostatic in release pixel.
Shift register provided by the embodiment of the present disclosure, noise reduction module export in the noise reduction stage in the first pull-down node
Second source signal control under, the pull-up node is written in the third power supply signal that third power supply is exported, so that pull-up
Module does not work under the control of the third power supply signal of pull-up node output in the noise reduction stage, so that pull-up effectively be avoided to save
Point present frame the noise reduction stage generate noise (the irregular lifting of current potential) caused by clock signal terminal next frame just
The clock signal of normal output stage output the problem of can completely is not output to the first output end, avoid pixel charge differential in the ranks
The display band of appearance is bad, or avoids pixel in the ranks the wrong display horizontal black line for filling appearance is bad.
Correspondingly, a kind of gate driving circuit that the embodiment of the present disclosure also provides, including m cascade shift registers,
In addition to preceding three-level shift register, the first of the signal input part of n-th grade of shift register and the n-th -3 grades of shift register
Output end connection, wherein m is more than or equal to 4, n and is greater than 3 and is less than or equal to m.
For example, m be 7, then except first order shift register, the second Ghandler motion bit register and third level shift register with
Outside, n=4 is enabled, since n-th grade of shift register, the signal input part and the n-th -3 grades shift LDs of n-th grade of shift register
First output end of device connects, the first output of the signal input part and the n-th -2 grades shift registers of (n+1)th grade of shift register
End connection, the signal input part of the n-th+2 grades shift registers are connect with the first output end of (n-1)th grade of shift register ..., according to
This analogizes.
In the embodiments of the present disclosure, gate driving circuit is GOA circuit.
In gate driving circuit provided by the embodiment of the present disclosure, shift register includes above-mentioned shift register, tool
Body description can be found in the above-mentioned description to shift register, and details are not described herein again.
Correspondingly, the embodiment of the present disclosure also provides a kind of display device, including gate driving circuit, the gate driving circuit
Including above-mentioned gate driving circuit, specifically describes and can be found in the above-mentioned description to gate driving circuit, details are not described herein again.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (12)
1. a kind of shift register characterized by comprising
Pre-charge module is connect with signal input part and pull-up node, for being exported in signal input part in pre-charging stage
Input signal control under, charge to the pull-up node；
Pull-up module is connect with the pull-up node, clock signal terminal, the first output end and second output terminal, for defeated
In the stage out, under the control of the voltage of pull-up node output, the clock signal transmission that the clock signal terminal is exported is extremely
First output end and the second output terminal；
Reseting module is connect with reset signal end, the first power supply and the pull-up node, is used in reseting stage, described
Under the control of the reset signal of reset signal end output, first power supply is connected to the pull-up node, on described
Node is drawn to be resetted；
Pull-down control module is connect with second source and the first pull-down node, is used in the noise reduction stage, in the second source
Under the control of the second source signal of output, first pull-down node is written into the second source signal；
Noise reduction module is connect with the pull-up node, first pull-down node and third power supply, is used in the noise reduction stage,
Under the control of the second source signal of first pull-down node output, the third power supply signal that third power supply is exported is written
The pull-up node, so that the pull-up module is in the noise reduction stage, in the control of the third power supply signal of pull-up node output
It does not work under system.
2. shift register according to claim 1, which is characterized in that the pre-charge module includes the first transistor,
First pole of the first transistor and control electrode are connected to the signal input part, and the second pole of the first transistor connects
It is connected to the pull-up node.
3. shift register according to claim 1, which is characterized in that the reseting module includes second transistor, institute
The control electrode for stating second transistor is connected to the reset signal end, and the first pole of the second transistor is connected to the pull-up
Node, the second pole of the second transistor are connected to first power supply.
4. shift register according to claim 1, which is characterized in that the pull-up module includes third transistor,
15 transistors and capacitor；
First pole of the third transistor is connected to the clock signal terminal, and the second pole of the third transistor is connected to institute
Second output terminal is stated, the control electrode of the third transistor is connected to the pull-up node；
First pole of the 15th transistor is connected to the clock signal terminal, the second pole connection of the 15th transistor
To first output end, the control electrode of the 15th transistor is connected to the pull-up node；
The first end of the capacitor is connected to the pull-up node, and the second end of the capacitor is connected to the second output terminal.
5. shift register according to claim 1, which is characterized in that the noise reduction module includes the 16th transistor,
First pole of the 16th transistor is connect with the third power supply, the second pole of the 16th transistor and the pull-up
Node connection, the control electrode of the 16th transistor are connect with first pull-down node.
6. shift register according to claim 5, which is characterized in that the noise reduction module also with first power supply,
First output end, the second output terminal are connected with the 4th power supply；
The noise reduction module was also used in the noise reduction stage, in the control of the second source signal of first pull-down node output
Under, the pull-up node and first output end is written into the first power supply signal of first power supply output, by described the
The second output terminal is written in 4th power supply signal of four power supplys output.
7. shift register according to claim 6, which is characterized in that the noise reduction module further include the tenth transistor,
Tenth two-transistor and the 13rd transistor；
First pole of the tenth transistor is connected to the pull-up node, and the second pole of the tenth transistor is connected to described
The control electrode of first power supply, the tenth transistor is connected to first pull-down node；
First pole of the tenth two-transistor is connected to first output end, the second pole connection of the tenth two-transistor
To first power supply, the control electrode of the tenth two-transistor is connected to first pull-down node；
First pole of the 13rd transistor is connected to the second output terminal, the second pole connection of the 13rd transistor
To the 4th power supply, the control electrode of the 13rd transistor is connected to first pull-down node.
8. shift register according to claim 1, which is characterized in that further include:
Pull-down module connects with the pull-up node, first power supply, first pull-down node and the second pull-down node
It connects, is used in output stage, under the control of the voltage of pull-up node output, by the first electricity of first power supply output
First pull-down node and second pull-down node is written in source signal.
9. shift register according to claim 8, which is characterized in that the pull-down module includes the 6th transistor and the
Eight transistors；
First pole of the 6th transistor is connected to first pull-down node, and the second pole of the 6th transistor is connected to
The control electrode of first power supply, the 6th transistor is connected to the pull-up node；
First pole of the 8th transistor is connected to second pull-down node, and the second pole of the 8th transistor is connected to
The control electrode of first power supply, the 8th transistor is connected to the pull-up node.
10. shift register according to claim 1, which is characterized in that the pull-down control module is also pulled down with second
Node connection, the pull-down control module include the 5th transistor and the 9th transistor；
First pole of the 5th transistor is connected to first pull-down node, and the second pole of the 5th transistor is connected to
The control electrode of the second source, the 5th transistor is connected to second pull-down node；
First pole of the 9th transistor and control electrode are respectively connected to the second source, and the second of the 9th transistor
Pole is connected to second pull-down node.
11. a kind of gate driving circuit characterized by comprising any displacement of m cascade claims 1 to 10
Register, in addition to preceding three-level shift register, the signal input part and the n-th -3 grades of shift LD of n-th grade of shift register
First output end of device connects, wherein m is more than or equal to 4, n and is greater than 3 and is less than or equal to m.
12. a kind of display device, which is characterized in that including the gate driving circuit described in claim 11.
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