CN107516492A - A kind of shift register, gate driving circuit and display device - Google Patents
A kind of shift register, gate driving circuit and display device Download PDFInfo
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- CN107516492A CN107516492A CN201710859739.1A CN201710859739A CN107516492A CN 107516492 A CN107516492 A CN 107516492A CN 201710859739 A CN201710859739 A CN 201710859739A CN 107516492 A CN107516492 A CN 107516492A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of shift register, gate driving circuit and display device, including：First control module, the second control module, the first output module and the second output module；Wherein, by the mutual cooperation of aforementioned four module, the output of driving signal output end can be realized by simple structure and less signal wire, so as to simplify preparation technology, reduces production cost.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of shift register, gate driving circuit and display device.
Background technology
With the rapid development of Display Technique, display panel increasingly develops towards the direction of high integration and low cost.
Wherein, array base palte row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film
Transistor, TFT) gate switch circuit is integrated on the array base palte of display panel and driven with forming scanning to display panel
It is dynamic, so as to save binding (Bonding) region of grid integrated circuits (Integrated Circuit, IC) and be fanned out to
(Fan-out) wiring space in region, not only product cost, Er Qieke can be reduced in material cost and the aspect of preparation technology two
So that display panel accomplishes that both sides are symmetrical and the design for aesthetic of narrow frame；Also, this integrated technique may be omitted with grid and sweep
The Bonding techniques in line direction are retouched, so as to improve production capacity and yield.
In general gate driving circuit is made up of the shift register of multiple cascades, real by shift registers at different levels
Now input scanning signal to each row grid line on display panel successively.At present, although can be by inputting more difference in functionality
Control signal realize the output of scanning signal, but so cause to form shift registers at different levels in gate driving circuit
The number of switching transistor is more, and the concrete structure connected between each switching transistor is also more complicated, causes technique difficult
Degree increases, production cost increase, or even due to needing to use more signal wire to input the control signal of a variety of difference in functionalitys
Shift registers at different levels, so as to cause the frame of display panel to increase so that the display panel does not possess competitiveness.
The content of the invention
The embodiment of the present invention provides a kind of shift register, gate driving circuit and display device, is not only simple in structure, and
And the signal wire for the difference in functionality for being used to realize scanning signal output for needing to connect is less, can simplify process complexity, drop
Low production cost.
Therefore, the embodiments of the invention provide a kind of shift register, including：First control module, the second control module,
First output module and the second output module；
First control module is respectively with input signal end, reset signal end, the first reference signal end, second with reference to letter
Number end and first node be connected, for the letter at the input signal end, the reset signal end and the first node
Number co- controlling under the signal at the first reference signal end is supplied to the first node, and in the input signal
End by the signal at the second reference signal end under the co- controlling of the signal of the first node with being supplied to the first segment
Point；
Second control module respectively with the input signal end, the reset signal end and the first node phase
Even, for the signal at the input signal end to be supplied into the first node under the control at the reset signal end；
First output module respectively with clock signal terminal, the first node, the section point and the shifting
The driving signal output end of bit register is connected, current potential and the first node of the signal for controlling the section point
The current potential of signal is anti-phase, and under the co- controlling of the signal of signal and the section point of the first node will described in
The signal of clock signal terminal is supplied to the signal output part；
Second output module respectively with output control signal end, the second reference signal end, the section point
And the driving signal output end is connected, in the common of the output control signal end and the signal of the section point
The signal at the second reference signal end is supplied to the driving signal output end under control.
Alternatively, in shift register provided in an embodiment of the present invention, first control module includes：First or non-
Door, first switch transistor, second switch transistor and the 3rd switching transistor；
The first input end of first nor gate is connected with the input signal end, and the second of first nor gate is defeated
Enter end with the first node to be connected, the output end of first nor gate control pole with the second switch transistor respectively
And the control pole of the 3rd switching transistor is connected；
The control pole of the first switch transistor is connected with the reset signal end, and the of the first switch transistor
One pole is connected with the first reference signal end, the second pole of the first switch transistor and the second switch transistor
First is extremely connected；
Second pole of the second switch transistor is connected with the first node；
First pole of the 3rd switching transistor is connected with the second reference signal end, the 3rd switching transistor
The second pole be connected with the first node.
Alternatively, in shift register provided in an embodiment of the present invention, first control module includes：Second or non-
Door, the first phase inverter, the 4th switching transistor, the 5th switching transistor and the 6th switching transistor；
The first input end of second nor gate is connected with the input signal end, and the second of second nor gate is defeated
Enter end with the first node to be connected, the output end of second nor gate is connected with the input of first phase inverter；
The output end of first phase inverter is opened with the control pole of the 5th switching transistor and the described 6th respectively
The control pole for closing transistor is connected；
The control pole of 4th switching transistor is connected with the reset signal end, and the of the 4th switching transistor
One pole is connected with the first reference signal end, the second pole and the 5th switching transistor of the 4th switching transistor
First is extremely connected；
Second pole of the 5th switching transistor is connected with the first node；
First pole of the 6th switching transistor is connected with the second reference signal end, the 6th switching transistor
The second pole be connected with the first node.
Alternatively, in shift register provided in an embodiment of the present invention, second control module includes：7th switch
Transistor；
The control pole of 7th switching transistor is connected with the reset signal end, and the of the 7th switching transistor
One pole is connected with the input signal end, and the second pole of the 7th switching transistor is connected with the first node.
Alternatively, in shift register provided in an embodiment of the present invention, first output module includes：Transmission gate with
Second phase inverter；
First control terminal of the transmission gate is connected with the first node, the second control terminal of the transmission gate with it is described
Section point is connected, and the input of the transmission gate is connected with the clock signal terminal, the output end of the transmission gate with it is described
Driving signal output end is connected；
The input of second phase inverter is connected with the first node, the output end of second phase inverter with it is described
Section point is connected.
Alternatively, in shift register provided in an embodiment of the present invention, second output module includes：8th switch
The switching transistor of transistor AND gate the 9th；
The control pole of 8th switching transistor is connected with the section point, and the first of the 8th switching transistor
Pole is connected with the second reference signal end, and the of the second pole of the 8th switching transistor and the 9th switching transistor
One is extremely connected；
The control pole of 9th switching transistor is connected with the output control signal end, the 9th switching transistor
The second pole be connected with the driving signal output end.
Alternatively, in shift register provided in an embodiment of the present invention, the shift register also includes：3rd is anti-phase
Device and the 4th phase inverter；First output module and second output module pass through the 3rd phase inverter and the respectively
Four phase inverters are connected with the driving signal output end；
The input of 3rd phase inverter is connected with first output module and second output module respectively,
The output end of 3rd phase inverter is connected with the input of the 4th phase inverter；
The output end of 4th phase inverter is connected with the driving signal output end.
Alternatively, in shift register provided in an embodiment of the present invention, the shift register also includes：Tenth switch
The switching transistor of transistor AND gate the 11st；
The control pole of tenth switching transistor is connected with touch-control control signal end, and the of the tenth switching transistor
One pole is connected with the second reference signal end, and the second pole of the tenth switching transistor is connected with the first node；
The control pole of 11st switching transistor is connected with the output control signal end, and the 11st switch is brilliant
First pole of body pipe is connected with the first reference signal end, and the second pole of the 11st switching transistor is believed with the driving
Number output end is connected.
Correspondingly, the embodiment of the present invention additionally provides a kind of gate driving circuit, including：Multiple present invention of cascade are implemented
Any of the above-described kind of shift register that example provides；
The input signal end of first order shift register is connected with frame trigger signal end；
In addition to the first order shift register, remaining input signal end per one-level shift register respectively with its phase
The driving signal output end of adjacent upper level shift register is connected；
In addition to afterbody shift register, the reset signal end difference of remaining every one-level shift register is adjacent thereto
The driving signal output end of next stage shift register be connected.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including above-mentioned grid provided in an embodiment of the present invention
Pole drive circuit.
The present invention has the beneficial effect that：
Shift register, gate driving circuit and display device provided in an embodiment of the present invention, including：First control mould
Block, the second control module, the first output module and the second output module；First control module is used in the input letter
Number end, the reset signal end and the first node signal co- controlling under by the letter at the first reference signal end
The first node number is supplied to, and by institute under the co- controlling of the input signal end and the signal of the first node
The signal for stating the second reference signal end is supplied to the first node；Second control module is used at the reset signal end
Control under the signal at the input signal end is supplied to the first node；First output module is described for controlling
The current potential of the current potential of the signal of section point and the signal of the first node is anti-phase, and the first node signal with
The signal of the clock signal terminal is supplied to the driving signal output end under the co- controlling of the signal of the section point；
Second output module is used for institute under the co- controlling of the output control signal end and the signal of the section point
The signal for stating the second reference signal end is supplied to the driving signal output end.Therefore, the phase interworking of aforementioned four module is passed through
Close, the output of driving signal output end can be realized by simple structure and less signal wire, prepared so as to simplify
Technique, reduce production cost.
Brief description of the drawings
Fig. 1 is the structural representation of shift register provided in an embodiment of the present invention；
Fig. 2 a are one of concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 2 b are the two of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 a are the three of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 3 b are the four of the concrete structure schematic diagram of shift register provided in an embodiment of the present invention；
Fig. 4 is a kind of input and output sequential chart provided in an embodiment of the present invention；
Fig. 5 is the structural representation of gate driving circuit provided in an embodiment of the present invention.
Embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention
The embodiment of the shift register of offer, gate driving circuit and display device is described in detail.It should be appreciated that
Preferred embodiment disclosed below is merely to illustrate and explain the present invention, and is not intended to limit the present invention.And do not conflicting
In the case of, the feature in embodiment and embodiment in the application can be mutually combined.
The embodiments of the invention provide a kind of array base palte, as shown in figure 1, including：First control module 1, the second control
Module 2, the first output module 3 and the second output module 4；
First control module 1 respectively with input signal end Input, reset signal end Reset, the first reference signal end V1,
Second reference signal end V2 and first node N1 are connected, in input signal end Input, reset signal end Reset and
The first reference signal end V1 signal is supplied to first node N1 under the co- controlling of first node N1 signal, and defeated
Enter and the second reference signal end V2 signal is supplied to first under the co- controlling of signal end Input and first node N1 signal
Node N1；
Second control module 2 is connected with input signal end Input, reset signal end Reset and first node N1 respectively,
For input signal end Input signal to be supplied into first node N1 under reset signal end Reset control；
First output module 3 respectively with clock signal terminal CK, first node N1, section point N2 and shift register
Driving signal output end Output is connected, the electricity of the current potential and first node N1 signal of the signal for controlling section point N2
Bit Inverting, and by clock signal terminal CK letter under the co- controlling of first node N1 signal and section point N2 signal
Number it is supplied to signal output part Output；
Second output module 4 respectively with output control signal end EN1, the second reference signal end V2, section point N2 and
Driving signal output end Output is connected, for the co- controlling in output control signal end EN1 and section point N2 signal
The lower signal by the second reference signal end V2 is supplied to driving signal output end Output.
Above-mentioned shift register provided in an embodiment of the present invention, including：First control module, the second control module, first
Output module and the second output module；First control module is used in input signal end, reset signal end and first node
Signal co- controlling under the signal at the first reference signal end is supplied to first node, and at input signal end and first
The signal at the second reference signal end is supplied to first node under the co- controlling of the signal of node；Second control module is used for
The signal at input signal end is supplied to first node under the control at reset signal end；First output module is used to control the second section
The current potential of the current potential of the signal of point and the signal of first node is anti-phase, and in the signal of first node and the signal of section point
Co- controlling under the signal of clock signal terminal is supplied to driving signal output end；Second output module is used in output control
The signal at the second reference signal end is supplied to driving signal output end under the co- controlling of the signal of signal end and section point.
Therefore, by the mutual cooperation of aforementioned four module, driving can be realized by simple structure and less signal wire
The output of signal output part, so as to simplify preparation technology, reduce production cost.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, effective arteries and veins at input signal end
It is high potential signal to rush signal, and the signal at the first reference signal end is high potential signal, and the signal at the second reference signal end is low
Electric potential signal.
With reference to specific embodiment, the present invention is described in detail.It should be noted that be in the present embodiment in order to
The present invention is preferably explained, but does not limit the present invention.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a and Fig. 2 b
Shown, the first control module 1 can include：First nor gate NY1, first switch transistor M1, second switch transistor M2 with
And the 3rd switching transistor M3；
First nor gate NY1 first input end is connected with input signal end Input, and the second of the first nor gate NY1 is defeated
Enter end with first node N1 to be connected, the first nor gate NY1 output end respectively with second switch transistor M2 control pole and
3rd switching transistor M3 control pole is connected；
First switch transistor M1 control pole is connected with reset signal end Reset, and the first of first switch transistor M1
Pole is connected with the first reference signal end V1, first switch transistor M1 the second pole and second switch transistor M2 the first pole phase
Even；
Second switch transistor M2 the second pole is connected with first node N1；
3rd switching transistor M3 the first pole is connected with the second reference signal end V2, and the second of the 3rd switching transistor M3
Pole is connected with first node N1.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 2 a and Fig. 2 b, the
One switching transistor M1 and second switch transistor M2 can be P-type transistor, and the 3rd switching transistor M3 can be N-type crystal
Pipe.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the first nor gate inputs at it
When the signal at end is low-potential signal, its output end can just export high potential signal.An as long as input of the first nor gate
The signal at end is high potential signal, and its output end can export low-potential signal.First switch transistor is at reset signal end
When in the conduction state under the control of signal, the signal at the first reference signal end can be supplied to the of second switch transistor
One pole.When second switch transistor is in the conduction state under the control of the signal of its control pole, its first pole can will be inputted
Signal be supplied to first node., can when 3rd switching transistor is in the conduction state under the control of the signal of its control pole
So that the signal at the second reference signal end is supplied into first node.Wherein, the concrete structure of the first nor gate can be with existing skill
Structure in art is identical, it will be appreciated by those skilled in the art that having, therefore not to repeat here.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 3 a and Fig. 3 b
Shown, the first control module 1 can also include：Second nor gate NY2, the first phase inverter D1, the 4th switching transistor M4, the 5th
Switching transistor M5 and the 6th switching transistor M6；
Second nor gate NY2 first input end is connected with input signal end Input, and the second of the second nor gate NY2 is defeated
Enter end with first node N1 to be connected, the second nor gate NY2 output end is connected with the first phase inverter D1 input；
The first phase inverter N1 output end control pole and the 6th switching transistor with the 5th switching transistor M5 respectively
M6 control pole is connected；
4th switching transistor M4 control pole is connected with reset signal end Reset, and the first of the 4th switching transistor M4
Pole is connected with the first reference signal end V1, the 4th switching transistor M4 the second pole and the 5th switching transistor M5 the first pole phase
Even；
5th switching transistor M5 the second pole is connected with first node N1；
6th switching transistor M6 the first pole is connected with the second reference signal end V2, and the second of the 6th switching transistor M6
Pole is connected with first node N1.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as best seen in figs. 3a and 3b, the
Four switching transistor M4 and the 6th switching transistor M6 can be P-type transistor, and the 5th switching transistor M5 can be N-type crystal
Pipe.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the second nor gate inputs at it
When the signal at end is low-potential signal, its output end can just export high potential signal.An as long as input of the second nor gate
The signal at end is high potential signal, and its output end can export low-potential signal.4th switching transistor is at reset signal end
When in the conduction state under the control of signal, the signal at the first reference signal end can be supplied to the of the 5th switching transistor
One pole.When 5th switching transistor is in the conduction state under the control of the signal of its control pole, its first pole can will be inputted
Signal be supplied to first node., can when 6th switching transistor is in the conduction state under the control of the signal of its control pole
So that the signal at the second reference signal end is supplied into first node.First phase inverter can be such that the signal of its input is exported with it
The current potential of the signal at end is opposite.Wherein, the concrete structure of the second nor gate and the first phase inverter can respectively with the prior art
Structure it is identical, it will be appreciated by those skilled in the art that having, therefore not to repeat here.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a to Fig. 3 b
Shown, the second control module 2 can include：7th switching transistor M7；
7th switching transistor M7 control pole is connected with reset signal end Reset, and the first of the 7th switching transistor M7
Pole is connected with input signal end Input, and the 7th switching transistor M7 the second pole is connected with first node N1.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 2 a to Fig. 3 b, the
Seven switching transistor M7 can be N-type transistor.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 7th switching transistor is multiple
When in the conduction state under the control of the signal of position signal end, the signal at input signal end can be supplied to first node.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a to Fig. 3 b
Shown, the first output module 3 can include：Transmission gate TG and the second phase inverter D2；
Transmission gate TG the first control terminal is connected with first node N1, transmission gate TG the second control terminal and section point N2
It is connected, transmission gate TG input is connected with clock signal terminal CK, transmission gate TG output end and driving signal output end
Output is connected；
Second phase inverter D2 input is connected with first node N1, the second phase inverter D2 output end and section point N2
It is connected.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, transmission gate is in its first control
The signal at end is high potential signal, and the signal of the second control terminal turns on when being low-potential signal, by the signal of clock signal terminal
It is supplied to driving signal output end.Second phase inverter can make the current potential phase of the signal of its output end and the signal of its input
Instead.Wherein, transmission gate can be identical with structure of the prior art respectively with the concrete structure of the second phase inverter, is this area skill
Art personnel are appreciated that what is had, and therefore not to repeat here.
Specifically, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 a to Fig. 3 b
Shown, the second output module 4 can include：8th switching transistor M8 and the 9th switching transistor M9；
8th switching transistor M8 control pole is connected with section point N2, the 8th switching transistor M8 the first pole and the
Two reference signal end V2 are connected, and the 8th switching transistor M8 the second pole is extremely connected with the first of the 9th switching transistor M9；
9th switching transistor M9 control pole is connected with output control signal end EN1, and the of the 9th switching transistor M9
Two poles are connected with driving signal output end Output.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 2 a to Fig. 3 b, the
Eight switching transistor M8 and the 9th switching transistor M9 can be N-type transistor.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 8th switching transistor is
When in the conduction state under the control of the signal of two nodes, the signal at the second reference signal end can be supplied to the 9th switch brilliant
First pole of body pipe., can be with when 9th switching transistor is in the conduction state under the control of the signal at output control signal end
The signal for inputting its first pole is supplied to signal output part.
Further, in order to improve the driving force of the signal of output, posted in above-mentioned displacement provided in an embodiment of the present invention
In storage, as shown in Fig. 2 b and Fig. 3 b, shift register can also include：3rd phase inverter D3 and the 4th phase inverter D4；First
The output module 4 of output module 3 and second passes through the 3rd phase inverter D3 and the 4th phase inverter D4 and driving signal output end respectively
Output is connected；
3rd phase inverter D3 input is connected with the first output module 3 and the second output module 4 respectively, and the 3rd is anti-phase
Device D3 output end is connected with the 4th phase inverter D4 input；
4th phase inverter D4 output end is connected with driving signal output end Output.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the input of the 3rd phase inverter
Respectively with second of the 9th switching transistor in the output end of the transmission gate in the first output module and the second output module
End is connected.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the 3rd phase inverter can make it
The signal of output end is opposite with the current potential of the signal of its input.4th phase inverter can also make the signal of its output end defeated with it
The current potential for entering the signal at end is opposite.Wherein, the structure of the 3rd phase inverter and the 4th phase inverter can be with structure of the prior art
Identical, it will be appreciated by those skilled in the art that having, therefore not to repeat here.
Further, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, such as Fig. 2 b and figure
Shown in 3b, shift register can also include：Tenth switching transistor M10 and the 11st switching transistor M11；
Tenth switching transistor M10 control pole is connected with touch-control control signal end EN2, the tenth switching transistor M10's
First pole is connected with the second reference signal end V2, and the tenth switching transistor M10 the second pole is connected with first node N1；
11st switching transistor M11 control pole is connected with output control signal end EN1, the 11st switching transistor
M11 the first pole is connected with the first reference signal end V1, the 11st switching transistor M11 the second pole and driving signal output end
Output is connected.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Fig. 2 b and Fig. 3 b, the
Ten switching transistor M10 can be N-type transistor, and the 11st switching transistor M11 can be P-type transistor.
In the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the tenth switching transistor is being touched
When controlling in the conduction state under the control of the signal of control signal end, the signal at the second reference signal end can be supplied to first
Node., can be by first when 11st switching transistor is in the conduction state under the control of the signal at output control signal end
The signal at reference signal end is supplied to signal output part.
In the specific implementation, typically shift register is applied in display panel, it is defeated with the grid line into display panel
Enter scanning signal, display panel is realized display function.Display panel typically also has touch controllable function at present, in order to avoid touch-control
Interfered with display, it is general to use touch-control with showing the mode of timesharing driving to realize the display of display panel and touch-control work(
Energy.In above-mentioned shift register provided in an embodiment of the present invention, the signal of touch-control control signal end is general in the display stage
Control the tenth switching transistor to end, so as to not influence to export normal scanning signal, realize display scanning.In the touch-control stage
The switching transistor of signal general control the tenth conducting of touch-control control signal end, so that the signal of section point is believed for high potential
Number ended with controlling transmission door, and control the conducting of the 5th switching transistor, and now output control signal end also controls the
Four switching transistors turn on, and then can make the signal of driving signal output end output low potential, to stop display scanning, and enter
Row touch-control.
In the specific implementation, the signal at output control signal end is generally high potential signal.Only under special circumstances, outside
Portion control IC (Integrated Circuit, integrated circuit) can control the signal at output control signal end to be changed into low potential letter
Number, to control the 11st switching transistor to turn on and the signal at the first reference signal end be supplied into driving signal output end.Its
In, special circumstances can be that display panel out of power will be extinguished, or display panel power-off, and this is that display may can be also remained in pixel
Electric charge during picture, therefore in order to avoid the electric charge remained in pixel adversely affects to display panel, by believing driving
The signal of number output end is changed into high potential signal, to control the electric charge remained in pixel to be discharged.
Further, in the specific implementation, in above-mentioned shift register provided in an embodiment of the present invention, the switch of N-type
Transistor turns under high potential signal effect, ends under low-potential signal effect；The switching transistor of p-type is believed in high potential
Number effect is lower ends, and is turned under low-potential signal effect.
It should be noted that the switching transistor mentioned in the above embodiment of the present invention can be thin film transistor (TFT) (TFT,
Thin Film Transistor) or metal oxide semiconductor field effect tube (MOS, Metal Oxide
Scmiconductor), do not limit herein.In specific implementation, the control pole of above-mentioned each switching transistor as its grid,
And, can be using the first pole as source electrode according to transistor types and the difference of input signal, the second pole is as drain electrode；Or
Using the first pole as drain electrode, the second pole does not do specific differentiation herein as source electrode.
Below by taking the structure of the shift register shown in Fig. 2 b as an example, combined circuit timing diagram is provided the embodiment of the present invention
Above-mentioned shift register the course of work make with detailed description.High potential signal is represented with 1 in described below, 0 represents low
Electric potential signal, wherein, 1 and 0 represents its logic level, merely to preferably explaining above-mentioned displacement provided in an embodiment of the present invention
The course of work of register, rather than the current potential being applied in the specific implementation on the grid of each switching transistor.Wherein, Fig. 2 b
Input and output sequential chart corresponding to shown shift register during normal display, as shown in figure 4, the main T1 chosen in Fig. 4,
Six stages of T2, T3, T4, T5 and T6.Also, output control signal end EN1 signal is high potential signal, touch-control control is believed
Number end signal be low-potential signal.First reference signal end V1 signal is high potential signal, the second reference signal end V2's
Signal is low-potential signal.
In the T1 stages, Input=1, CK=0, Reset=0.Due to Input=1, therefore the first nor gate NY1 outputs are low
Electric potential signal, to control second switch transistor M2 to turn on, and control the 3rd switching transistor M3 cut-offs.Due to Reset=
0, therefore the 7th switching transistor M7 ends, first switch transistor M1 conductings.The first switch transistor M1 of conducting and second
First reference signal end V1 high potential signal is supplied to first node N1 by switching transistor M2, makes first node N1 for high electricity
Position signal, due to the second phase inverter D2 effect, section point N2 signal is low-potential signal, so as to which controlling transmission door TG is led
It is logical, and control the 8th switching transistor M8 cut-offs.The transmission gate TG of conducting provides clock signal terminal CK low-potential signal
Driving signal output end Output is given, makes the scanning signal of driving signal output end Output output low potentials.
In the T2 stages, Input=0, CK=0, Reset=0.Due to Reset=0, therefore the 7th switching transistor M7 is cut
Only, first switch transistor M1 is turned on.Therefore first node N1 remains high potential signal, and makes the section point N2 signal be
Low-potential signal, so as to which controlling transmission door TG is turned on, and control the 8th switching transistor M8 cut-offs.The transmission gate TG of conducting will
Clock signal terminal CK low-potential signal is supplied to driving signal output end Output, exports driving signal output end Output
The scanning signal of low potential.
In the T3 stages, Input=0, CK=1, Reset=0.Due to Reset=0, therefore the 7th switching transistor M7 is cut
Only.Therefore first node N1 remains high potential signal, and makes section point N2 signal be low-potential signal, so as to control biography
Defeated door TG conductings, and control the 8th switching transistor M8 cut-offs.The transmission gate TG of conducting is by clock signal terminal CK high potential
Signal is supplied to driving signal output end Output, makes the scanning signal of driving signal output end Output output high potentials.
In the T4 stages, Input=0, CK=0, Reset=0.Due to Reset=0, therefore the 7th switching transistor M7 is cut
Only.Therefore first node N1 remains high potential signal, and makes section point N2 signal be low-potential signal, so as to control biography
Defeated door TG conductings, and control the 8th switching transistor M8 cut-offs.The transmission gate TG of conducting is by clock signal terminal CK low potential
Signal is supplied to driving signal output end Output, makes the scanning signal of driving signal output end Output output low potentials.
In the T5 stages, Input=0, CK=0, Reset=1.Due to Reset=1, therefore the 7th switching transistor M7 is led
It is logical, and first switch transistor M1 ends.7th switching transistor M7 of conducting is by input signal end Input low-potential signal
First node N1 is supplied to, the signal for making first node N1 is electric potential signal, so that the first nor gate NY1 output high potential letters
Number, to control second switch transistor M2 to end, the 3rd switching transistor M3 conductings.3rd switching transistor M3 of conducting is by the
Two reference signal end V2 low-potential signal is supplied to first node N1, first node N1 signal is believed for low potential
Number.Because first node N1 signal is low-potential signal, due to the second phase inverter D2 effect, make section point N2 signal
For high potential signal, so as to which controlling transmission door TG ends, and the 8th switching transistor M8 of control is turned on.Because output control is believed
Number end EN1 signal be high potential signal, therefore the 9th switching transistor M9 conductings.8th switching transistor M8 of conducting and the
Second reference signal end V2 low-potential signal is supplied to driving signal output end Output by nine switching transistor M9, makes driving
Signal output part Output exports the scanning signal of low potential.
In the T6 stages, Input=0, CK=0, Reset=0.Due to Reset=0, therefore the 7th switching transistor M7 is cut
Only.Therefore first node N1 remains low-potential signal, because the second phase inverter N2 effect is so that section point N2 signal
For high potential signal, controlling transmission door TG cut-offs, and control the 8th switching transistor M8 conductings.Due to output control signal end
EN1 signal is high potential signal, therefore the 9th switching transistor M9 is turned on.8th switching transistor M8 of conducting opens with the 9th
Close transistor M9 and the second reference signal end V2 low-potential signal is supplied to driving signal output end Output, make drive signal
Output end Output exports the scanning signal of low potential.
After the T6 stages, the course of work in T6 stages is repeated always, until input signal end Input signal is again
It is secondary to be changed into high potential signal.
Shift register provided in an embodiment of the present invention, can be with by above-mentioned simple structure and less signal wire
Stable output scanning signal, so as to simplify preparation technology, reduce production cost.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of gate driving circuit, as shown in figure 5, including
Multiple any of the above-described kind of shift register SR (1) provided in an embodiment of the present invention of cascade, SR (2) ... SR (n-1), SR (n) ...
SR (N-1), SR (N) (N number of shift register altogether, 1≤n≤N)；Wherein,
First order shift register SR (1) input signal end Input is connected with frame trigger signal end STV；
In addition to first order shift register SR (1), the input signal end Input of remaining shift register SR (n) at different levels
Upper level shift register SR (n-1) adjacent thereto driving signal output end Output is connected respectively；
In addition to afterbody shift register SR (N), the reset signal end of remaining shift register SR (n) at different levels
The driving signal output end that Reset distinguishes next stage shift register adjacent thereto is connected.
Specifically, above-mentioned gate driving circuit can apply in liquid crystal display panel, can also be applied to organic electroluminescence
In light emitting display panel, it is not limited thereto.Also, above-mentioned gate driving circuit solves the principle of problem and aforementioned shift is deposited
Device is similar, therefore the implementation of the gate driving circuit may refer to the implementation of aforementioned shift register, repeats part herein no longer
Repeat.
In the specific implementation, in above-mentioned gate driving circuit provided by the invention, 2k-1 level shift registers when
Clock signal end is that the first clock end ck1 is connected with same clock end；The clock signal terminal of 2k level shift registers with together
One clock end is that second clock end ck2 is connected；Wherein, k is positive integer, the signal of the first clock end and the signal at second clock end
Cycle phase with and dutycycle it is identical.Also, the output control signal end of shift registers at different levels with same output control terminal
It is connected, the first reference signal end of shift registers at different levels is connected with same first reference edge, and the of shift registers at different levels
Two reference signal ends are connected with same second reference edge.
In the specific implementation, when shift register also includes ten switching transistors, the touch-control of shift registers at different levels
Control signal end is connected with same touch-control control terminal.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention carries
The above-mentioned gate driving circuit supplied.The display device can be：Mobile phone, tablet personal computer, television set, display, notebook computer,
Any product or part with display function such as DPF, navigator.For the other essential of the display device
Part is it will be apparent to an ordinarily skilled person in the art that have, and will not be described here, also should not be used as to this hair
Bright limitation.The implementation of the display device may refer to the embodiment of above-mentioned gate driving circuit, repeats part and repeats no more.
Shift register, gate driving circuit and display device provided in an embodiment of the present invention, including：First control mould
Block, the second control module, the first output module and the second output module；First control module is used at input signal end, again
The signal at the first reference signal end is supplied to first node under the co- controlling of the signal of position signal end and first node, with
And the signal at the second reference signal end is supplied to first segment under the co- controlling of input signal end and the signal of first node
Point；Second control module is used to the signal at input signal end is supplied into first node under the control at reset signal end；First
The current potential that output module is used for the signal for the current potential and first node for controlling the signal of section point is anti-phase, and in first node
Signal and section point signal co- controlling under the signal of clock signal terminal is supplied to driving signal output end；Second
Output module is used for the letter at the second reference signal end under the co- controlling of output control signal end and the signal of section point
Number it is supplied to driving signal output end.Therefore, by the mutual cooperation of aforementioned four module, can by simple structure and
Less signal wire realizes the output of driving signal output end, so as to simplify preparation technology, reduces production cost.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
- A kind of 1. shift register, it is characterised in that including：First control module, the second control module, the first output module with And second output module；First control module respectively with input signal end, reset signal end, the first reference signal end, the second reference signal end And first node is connected, for the signal at the input signal end, the reset signal end and the first node The signal at the first reference signal end is supplied to the first node under co- controlling, and the input signal end with The signal at the second reference signal end is supplied to the first node under the co- controlling of the signal of the first node；Second control module is connected with the input signal end, the reset signal end and the first node respectively, For the signal at the input signal end to be supplied into the first node under the control at the reset signal end；First output module is posted with clock signal terminal, the first node, the section point and the displacement respectively The driving signal output end of storage is connected, the signal of the current potential and the first node of the signal for controlling the section point Current potential it is anti-phase, and by the clock under the co- controlling of the signal of signal and the section point of the first node The signal of signal end is supplied to the signal output part；Second output module respectively with output control signal end, the second reference signal end, the section point and The driving signal output end is connected, for the co- controlling at the output control signal end and the signal of the section point The lower signal by the second reference signal end is supplied to the driving signal output end.
- 2. shift register as claimed in claim 1, it is characterised in that first control module includes：First nor gate, First switch transistor, second switch transistor and the 3rd switching transistor；The first input end of first nor gate is connected with the input signal end, the second input of first nor gate Be connected with the first node, the output end of first nor gate respectively with the control pole of the second switch transistor and The control pole of 3rd switching transistor is connected；The control pole of the first switch transistor is connected with the reset signal end, the first pole of the first switch transistor It is connected with the first reference signal end, the second pole of the first switch transistor and the first of the second switch transistor Extremely it is connected；Second pole of the second switch transistor is connected with the first node；First pole of the 3rd switching transistor is connected with the second reference signal end, and the of the 3rd switching transistor Two poles are connected with the first node.
- 3. shift register as claimed in claim 1, it is characterised in that first control module includes：Second nor gate, First phase inverter, the 4th switching transistor, the 5th switching transistor and the 6th switching transistor；The first input end of second nor gate is connected with the input signal end, the second input of second nor gate It is connected with the first node, the output end of second nor gate is connected with the input of first phase inverter；The output end of first phase inverter is brilliant with the control pole of the 5th switching transistor and the 6th switch respectively The control pole of body pipe is connected；The control pole of 4th switching transistor is connected with the reset signal end, the first pole of the 4th switching transistor It is connected with the first reference signal end, the second pole of the 4th switching transistor and the first of the 5th switching transistor Extremely it is connected；Second pole of the 5th switching transistor is connected with the first node；First pole of the 6th switching transistor is connected with the second reference signal end, and the of the 6th switching transistor Two poles are connected with the first node.
- 4. shift register as claimed in claim 1, it is characterised in that second control module includes：7th switch is brilliant Body pipe；The control pole of 7th switching transistor is connected with the reset signal end, the first pole of the 7th switching transistor It is connected with the input signal end, the second pole of the 7th switching transistor is connected with the first node.
- 5. shift register as claimed in claim 1, it is characterised in that first output module includes：Transmission gate and Two phase inverters；First control terminal of the transmission gate is connected with the first node, the second control terminal of the transmission gate and described second Node is connected, and the input of the transmission gate is connected with the clock signal terminal, the output end of the transmission gate and the driving Signal output part is connected；The input of second phase inverter is connected with the first node, the output end of second phase inverter and described second Node is connected.
- 6. shift register as claimed in claim 1, it is characterised in that second output module includes：8th switch is brilliant The switching transistors of body Guan Yu nine；The control pole of 8th switching transistor is connected with the section point, the first pole of the 8th switching transistor with The second reference signal end is connected, the second pole of the 8th switching transistor and the first pole of the 9th switching transistor It is connected；The control pole of 9th switching transistor is connected with the output control signal end, and the of the 9th switching transistor Two poles are connected with the driving signal output end.
- 7. the shift register as described in claim any one of 1-6, it is characterised in that the shift register also includes：The Three phase inverters and the 4th phase inverter；First output module passes through the 3rd phase inverter respectively with second output module And the 4th phase inverter be connected with the driving signal output end；The input of 3rd phase inverter is connected with first output module and second output module respectively, described The output end of 3rd phase inverter is connected with the input of the 4th phase inverter；The output end of 4th phase inverter is connected with the driving signal output end.
- 8. the shift register as described in claim any one of 1-5, it is characterised in that the shift register also includes：The Ten switching transistors and the 11st switching transistor；The control pole of tenth switching transistor is connected with touch-control control signal end, the first pole of the tenth switching transistor It is connected with the second reference signal end, the second pole of the tenth switching transistor is connected with the first node；The control pole of 11st switching transistor is connected with the output control signal end, the 11st switching transistor The first pole be connected with the first reference signal end, the second pole of the 11st switching transistor and the drive signal are defeated Go out end to be connected.
- A kind of 9. gate driving circuit, it is characterised in that including：Multiple shiftings as described in claim any one of 1-8 of cascade Bit register；The input signal end of first order shift register is connected with frame trigger signal end；In addition to the first order shift register, the input signal end difference of remaining every one-level shift register is adjacent thereto The driving signal output end of upper level shift register is connected；In addition to afterbody shift register, under remaining reset signal end difference per one-level shift register is adjacent thereto The driving signal output end of one-level shift register is connected.
- 10. a kind of display device, it is characterised in that including gate driving circuit as claimed in claim 9.
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