CN110930942B - Shift register, control method thereof and display panel - Google Patents
Shift register, control method thereof and display panel Download PDFInfo
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- CN110930942B CN110930942B CN201911191450.2A CN201911191450A CN110930942B CN 110930942 B CN110930942 B CN 110930942B CN 201911191450 A CN201911191450 A CN 201911191450A CN 110930942 B CN110930942 B CN 110930942B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The invention discloses a shift register, a control method thereof and a display panel, and relates to the technical field of display, wherein the shift register comprises a first node control unit and a second node control unit which are used for respectively providing low level to a first node and a second node; a first inverting unit for supplying a potential opposite to a potential of the first node to the third node; a second inverting unit for supplying a potential opposite to a potential of the second node to the fourth node; and the first output unit and the second output unit are used for simultaneously providing opposite signals to the first output signal terminal and the second output signal terminal. The control method is used for controlling the work of the shift register. The display panel comprises a plurality of pixel circuits, and the scanning driving circuit comprises a plurality of shift registers. The shift register can simultaneously meet the output of positive and negative pulses, and is favorable for reducing the manufacturing size while meeting the driving capability.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a control method thereof and a display panel.
Background
In the field of display technology, a Thin Film Transistor (TFT) refers to a TFT integrated behind each liquid crystal pixel on a liquid crystal display to drive, so as to display screen information with high speed, high brightness and high contrast. Especially, large-sized, high-resolution, and high-quality flat panel display devices such as liquid crystal televisions have been dominant in the current flat panel display market. With the development of the application technology of Organic Light-Emitting diodes (OLEDs) in display screens, people have higher and higher requirements on Low power consumption performance of display devices, and Low Temperature Poly-silicon (LTPS) display technologies that can drive TFTs and switch TFTs and realize lower power consumption gradually become mainstream. The display device is usually provided with a Gate Driver on Array (GOA) circuit, where the GOA circuit includes a plurality of shift register units, and an output end of each shift register unit is connected to a row of Gate lines for outputting a Gate scanning signal to the Gate lines, so as to scan the Gate lines row by row. Besides, the output ends of the other shift register units except the last shift register unit need to be connected with the input end of the next shift register unit.
Currently, most OLED devices employ the panel technology of LTPSTFT. After the improvement of the past years, the LTPS display panel has the advantages of high resolution, high response speed, high brightness, high aperture ratio, etc., so that it becomes the most mature and mainstream TFT panel technology in the market today. Although the LTPS display panel is popular in the market, it has disadvantages of high production cost and large required power consumption. Therefore, in recent years, a Low Temperature Polycrystalline Oxide (LTPO) display panel technology, that is, an LTPO display panel obtained by combining the LTPS display panel technology and the Oxide display panel technology, has been developed by technicians, and the LTPO display panel not only has the advantages of high resolution, high reaction speed, high brightness, high aperture ratio and the like of the LTPS display panel, but also has the advantages of Low production cost and Low power consumption.
In the prior art, the LTPO display panel technology combines the LTPS display panel technology and the Oxide display panel technology, so that a shift register unit of a pixel circuit in the LTPO display panel needs to simultaneously satisfy positive and negative pulse output.
Therefore, it is an urgent need to solve the technical problem of the art to provide a shift register, a control method thereof, and a display panel, which can satisfy both positive and negative pulse output, simplify the process, and have strong driving capability.
Disclosure of Invention
In view of the above, the present invention provides a shift register, a control method thereof, and a display panel, so as to solve the problems that a shift register unit in the prior art cannot simultaneously satisfy positive and negative pulse outputs, and cannot simultaneously reduce the manufacturing size and improve the driving capability.
The present invention provides a shift register, comprising: a first node control unit electrically connected to the input control signal terminal and the first clock signal terminal, for providing a low level to the first node according to signals of the input control signal terminal and the first clock signal terminal; a second node control unit electrically connected to the input control signal terminal, the first clock signal terminal, the second clock signal terminal, and the first node, for providing a low level to the second node according to signals of the input control signal terminal, the first clock signal terminal, and the second clock signal terminal, and for providing a high level to the second node in response to the low level of the first node; a first output unit electrically connected to the first node and the second node, for providing a low level to the first output signal terminal in response to a low level of the first node, and for providing a high level to the first output signal terminal in response to a low level of the second node; a first inverting unit electrically connected to the first node, for supplying a potential opposite to a potential of the first node to the third node; a second inverting unit electrically connected to the second node, for supplying a potential opposite to a potential of the second node to the fourth node; and a second output unit electrically connected to the third node and the fourth node, for providing a low level to the second output signal terminal in response to a low level of the third node, and for providing a high level to the second output signal terminal in response to a low level of the fourth node.
Based on the same inventive concept, the invention also provides a control method of the shift register, which comprises the following steps: a first node control unit electrically connected to the input control signal terminal and the first clock signal terminal, for providing a low level to the first node according to signals of the input control signal terminal and the first clock signal terminal; a second node control unit electrically connected to the input control signal terminal, the first clock signal terminal, the second clock signal terminal, and the first node, for providing a low level to the second node according to signals of the input control signal terminal, the first clock signal terminal, and the second clock signal terminal, and for providing a high level to the second node in response to the low level of the first node; a first output unit electrically connected to the first node and the second node, for providing a low level to the first output signal terminal in response to a low level of the first node, and for providing a high level to the first output signal terminal in response to a low level of the second node; a first inverting unit electrically connected to the first node, for supplying a potential opposite to a potential of the first node to the third node; a second inverting unit electrically connected to the second node, for supplying a potential opposite to a potential of the second node to the fourth node; a second output unit electrically connected to the third node and the fourth node, for providing a low level to the second output signal terminal in response to a low level of the third node, and for providing a high level to the second output signal terminal in response to a low level of the fourth node;
the control method of the shift register comprises the following steps: the first stage, provide the high level to input control signal end and first clock signal end, provide the low level to the second clock signal end, the first output unit responds to the low level of the second node, provide the high level to the first output signal end, the second output unit responds to the low level of the third node, provide the low level to the second output signal end; and providing a high level to the input control signal terminal and the second clock signal terminal, and providing a low level to the first clock signal terminal, the first output unit providing a high level to the first output signal terminal in response to a low level of the second node, and the second output unit providing a low level to the second output signal terminal in response to a low level of the third node; in the second stage, a low level is provided for the input control signal end and the first clock signal end, a high level is provided for the second clock signal end, the first output unit responds to the low level of the first node and provides the low level to the first output signal end, and the second output unit responds to the low level of the fourth node and provides the high level to the second output signal end; a third stage of providing a high level to the input control signal terminal and the first clock signal terminal and a low level to the second clock signal terminal, the first output unit providing a low level to the first output signal terminal in response to the low level of the first node, the second output unit providing a high level to the second output signal terminal in response to the low level of the fourth node; and a fourth stage of providing a high level to the input control signal terminal and the second clock signal terminal and a low level to the first clock signal terminal, wherein the first output unit provides a high level to the first output signal terminal in response to the low level of the second node, and the second output unit provides a low level to the second output signal terminal in response to the low level of the third node.
Based on the same inventive concept, the present invention also provides a display panel, comprising: a plurality of pixel circuits; at least one scanning driving circuit, wherein the scanning driving circuit comprises a plurality of shift registers, and the shift registers are the shift registers; the first output signal end and the second output signal end of the shift register are electrically connected with the pixel circuit.
Compared with the prior art, the shift register, the control method thereof and the display panel provided by the invention at least realize the following beneficial effects:
the shift register can simultaneously meet the output of positive and negative pulses, namely when the output of a first output signal end is at a high level, the output of a second output signal end is at a low level; when the output of the first output signal terminal is at low level, the output of the second output signal terminal is at high level. Because the first phase reversal unit is positioned between the first node control unit and the third node, the second phase reversal unit is positioned between the first node control unit and the fourth node, and potential signals of the third node and the fourth node only need to be used for driving the second output unit, the first phase reversal unit and the second phase reversal unit connected with the third node and the fourth node do not need strong driving capability and further do not need to occupy larger space layout.
Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic diagram of a frame structure of a shift register according to an embodiment of the present invention;
FIG. 2 is a timing diagram of signals at each end of the shift register of FIG. 1;
fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of the shift register of FIG. 3 in a first stage;
FIG. 5 is another circuit schematic of the shift register of FIG. 3 during a first stage;
FIG. 6 is a schematic diagram showing an electrical analysis of the shift register of FIG. 3 at a second stage;
FIG. 7 is a schematic diagram showing a circuit analysis of the shift register of FIG. 3 at a third stage;
FIG. 8 is a schematic circuit diagram of the shift register of FIG. 3 in a fourth stage;
fig. 9 is a schematic plan view illustrating a display panel according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of the pixel circuit of FIG. 9;
fig. 11 is a schematic structural diagram of a pixel circuit in the prior art.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Referring to fig. 1, fig. 1 is a schematic diagram of a frame structure of a shift register according to an embodiment of the present invention, where the shift register according to the embodiment includes:
a first node control unit 101 electrically connected to the input control signal terminal IN and the first clock signal terminal CK1, for providing a low level to the first node Q according to the signals of the input control signal terminal IN and the first clock signal terminal CK 1;
a second node control unit 102 electrically connected to the input control signal terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, and the first node Q, for providing a low level to the second node QB according to signals of the input control signal terminal IN, the first clock signal terminal CK1, and the second clock signal terminal CK2, and for providing a high level to the second node QB IN response to the low level of the first node Q;
a first output unit 301 electrically connected to the first and second nodes Q and QB, for providing a low level to the first output signal terminal SCAN-P in response to a low level of the first node Q, and for providing a high level to the first output signal terminal SCAN-P in response to a low level of the second node QB;
a first inverting unit 201 electrically connected to the first node Q for supplying a potential opposite to that of the first node Q to a third node Q1;
a second inverting unit 202 electrically connected to the second node QB for supplying a potential opposite to that of the second node QB to the fourth node QB 1;
the second output unit 302, electrically connected to the third node Q1 and the fourth node QB1, provides a low level to the second output signal terminal SCAN-N in response to a low level of the third node Q1, and provides a high level to the second output signal terminal SCAN-N in response to a low level of the fourth node QB 1.
Referring to fig. 1 and fig. 2 in combination, fig. 2 is a signal timing diagram of each end of the shift register in fig. 1, and a control method of the shift register provided in the present embodiment is applied to the shift register shown in fig. 1, and the control method includes:
a first stage t1 for supplying a high level to the input control signal terminal IN and the first clock signal terminal CK1 and a low level to the second clock signal terminal CK2, the first output unit 301 supplying a high level to the first output signal terminal SCAN-P IN response to a low level of the second node QB, and the second output unit 302 supplying a low level to the second output signal terminal SCAN-N IN response to a low level of the third node Q1; and the number of the first and second groups,
the first output unit 301 supplies a high level to the first output signal terminal SCAN-P IN response to a low level of the second node Q1, and the second output unit 302 supplies a low level to the second output signal terminal SCAN-N IN response to a low level of the third node Q1;
a second stage t2 for supplying a low level to the input control signal terminal IN and the first clock signal terminal CK1 and a high level to the second clock signal terminal CK2, the first output unit 301 supplying a low level to the first output signal terminal SCAN-P IN response to the low level of the first node Q, and the second output unit 302 supplying a high level to the second output signal terminal SCAN-N IN response to the low level of the fourth node QB 1;
a third stage t3 for supplying a high level to the input control signal terminal IN and the first clock signal terminal CK1 and a low level to the second clock signal terminal CK2, the first output unit 301 supplying a low level to the first output signal terminal SCAN-P IN response to a low level of the first node Q, and the second output unit 302 supplying a high level to the second output signal terminal SCAN-N IN response to a low level of the fourth node QB 1;
the fourth stage t4 provides a high level to the input control signal terminal IN and the second clock signal terminal CK2, provides a low level to the first clock signal terminal CK1, the first output unit 301 provides a high level to the first output signal terminal SCAN-P IN response to the low level of the second node QB, and the second output unit 302 provides a low level to the second output signal terminal SCAN-N IN response to the low level of the third node Q1.
Specifically, as can be seen from the description of the control method of the shift register, the shift register of the present embodiment can simultaneously satisfy the positive and negative pulse outputs, that is, when the first output signal terminal SCAN-P outputs a high level, the second output signal terminal SCAN-N outputs a low level; when the first output signal terminal SCAN-P output is at low level, the second output signal terminal SCAN-N output is at high level. Since the first inverting unit 201 of the present embodiment is located between the first node control unit 101 and the third node Q1, the second inverting unit 202 is located between the first node control unit 102 and the fourth node QB1, and the potential signals of the third node Q1 and the fourth node QB1 only need to be used for driving the second output unit 302, the first inverting unit 201 and the second inverting unit 202 connected to the third node Q1 and the fourth node QB1 do not need strong driving capability, and further do not need to occupy a large space layout.
In some optional embodiments, please refer to fig. 3, where fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, in this embodiment, the first node control unit 101 includes: the first transistor T1 has a first terminal electrically connected to the input control signal terminal IN, a second terminal electrically connected to the first node Q, and a control terminal electrically connected to the first clock signal terminal CK 1.
The second node control unit 102 includes: a second transistor T2, a first end of which is electrically connected to the power high voltage terminal VGH, a second end of which is electrically connected to the fifth node N, and a control end of which is electrically connected to the input control signal terminal IN; a third transistor T3, a first terminal of which is electrically connected to the power high voltage terminal VGH, a second terminal of which is electrically connected to the fifth node N, and a control terminal of which is electrically connected to the second clock signal terminal CK 2; a fourth transistor T4, a first terminal of which is electrically connected to the first clock signal terminal CK1, a second terminal of which is electrically connected to the second node QB, and a control terminal of which is electrically connected to the fifth node N; the first capacitor C1 has a first end electrically connected to the fifth node N and a second end electrically connected to the first clock signal terminal CK 1.
Optionally, the second node control unit 102 may further include a fourth capacitor C4, a first terminal of which is electrically connected to the power high terminal VGH, and a second terminal of which is electrically connected to the second node QB. The second node control unit 102 further includes: a first terminal of the fifth transistor T5 is electrically connected to the power high terminal VGH, a second terminal thereof is electrically connected to the second node QB, and a control terminal thereof is electrically connected to the first node Q.
The first output unit 301 includes: a seventh transistor T7, a first end of which is electrically connected to the power low-level terminal VGL, a second end of which is electrically connected to the first output signal terminal SCAN-P, and a control end of which is electrically connected to the first node Q; a second capacitor C2 having a first terminal electrically connected to the first node Q and a second terminal electrically connected to the first output signal terminal SCAN-P; an eighth transistor T8, a first terminal of which is electrically connected to the power high voltage terminal VGH, a second terminal of which is electrically connected to the first output signal terminal SCAN-P, and a control terminal of which is electrically connected to the second node QB; and/or the presence of a gas in the gas,
the second output unit 302 includes: a ninth transistor T9, a first terminal of which is electrically connected to the power low level terminal VGL, a second terminal of which is electrically connected to the second output signal terminal SCAN-N, and a control terminal of which is electrically connected to the third node Q1; a third capacitor C3 having a first terminal electrically connected to the third node Q1 and a second terminal electrically connected to the second output signal terminal SCAN-N; a tenth transistor T10 has a first terminal electrically connected to the power high voltage terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB 1. Optionally, the second output unit 302 further includes a fifth capacitor C5, a first terminal of which is electrically connected to the power high terminal VGH, and a second terminal of which is electrically connected to the fourth node QB 1;
the first output unit 301 further includes: the sixth transistor T6 has a first terminal electrically connected to the first inverter unit 201 (i.e., the second terminal of the first transistor T1), a second terminal electrically connected to the first node Q, and a control terminal electrically connected to the power low terminal VGL. Optionally, the second output unit 302 may further include: a fifteenth transistor T15 has a first end electrically connected to the first inverter unit 201, a second end electrically connected to the third node Q1, and a control end electrically connected to the power low-level terminal VGL.
The first inverting unit 201 includes an eleventh transistor T11 and a twelfth transistor T12, the eleventh transistor T11 for supplying a high level to the third node Q1 in response to a low level of the first node Q, the twelfth transistor T12 for supplying a low level to the third node Q1 in response to a high level of the first node Q; and/or the presence of a gas in the gas,
the second inverting unit 202 includes a thirteenth transistor T13 and a fourteenth transistor T14, the thirteenth transistor T13 for supplying a high level to the fourth node QB1 in response to a low level of the second node QB, and the fourteenth transistor T14 for supplying a low level to the fourth node QB1 in response to a high level of the second node QB.
Optionally, a first terminal of the eleventh transistor T11 is electrically connected to the power high-level terminal VGH, a second terminal thereof is electrically connected to the third node Q1, a control terminal thereof is electrically connected to the first node Q, a first terminal of the twelfth transistor T11 is electrically connected to the power low-level terminal VGL, a second terminal thereof is electrically connected to the third node Q1, and a control terminal thereof is electrically connected to the first node Q. A first end of the thirteenth transistor T13 is electrically connected to the high power terminal VGH, a second end thereof is electrically connected to the fourth node QB1, a control end thereof is electrically connected to the second node QB, a first end of the fourteenth transistor T14 is electrically connected to the low power terminal VGL, a second end thereof is electrically connected to the fourth node QB1, and a control end thereof is electrically connected to the second node QB.
Specifically, referring to fig. 2 and fig. 3, in fig. 2 and fig. 3 of the present embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, and the fifteenth transistor T15 are P-type transistors, and the twelfth transistor T12 and the fourteenth transistor T14 are N-type transistors, respectively, to illustrate the operation principle of the shift register of the present embodiment.
Referring to fig. 2, fig. 3 and fig. 4 IN combination, fig. 4 is a circuit analysis diagram of the shift register of fig. 3 at a first stage, where at the first stage T1, a high level is provided to the input control signal terminal IN and the first clock signal terminal CK1, a low level is provided to the second clock signal terminal CK2, the third transistor T3 is turned on, the first transistor T1 is turned off, and the second transistor T2 is turned off, because the first terminal of the third transistor T3 is electrically connected to the power high-level terminal VGH, the second terminal thereof is electrically connected to the fifth node N, and the control terminal thereof is electrically connected to the second clock signal terminal CK2, the fifth node N is a high-level signal of the power high-level terminal VGH, and the fourth transistor T4 is turned off; at this time, the first terminal of the fourth capacitor C4 is electrically connected to the power high-level terminal VGH, and keeps a high-level signal connected to the power high-level terminal VGH, and the second terminal thereof is electrically connected to the second node QB, so that the second node QB is kept as a low-level signal in a state where the first transistor T1, the second transistor T2, and the fourth transistor T4 are all turned off;
the eighth transistor T8 of the first output unit 301 is turned on in response to the low level of the second node QB, and provides the high level of the power supply high level terminal VGH to the first output signal terminal SCAN-P, i.e., the first output signal terminal SCAN-P outputs the high level.
The thirteenth transistor T13 of the second inverting unit 202 is responsive to the low level of the second node QB, the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and provides the high level of the power source high level terminal VGH to the fourth node QB1, i.e., the potential of the fourth node QB1 is opposite to the low level signal of the second node QB. The tenth transistor T10 of the second output unit 302 has a first terminal electrically connected to the power high terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB1, and thus the tenth transistor T10 is turned off when the fourth node QB1 is at a high level.
Since the first end of the second capacitor C2 is electrically connected to the first node Q, the second end is electrically connected to the first output signal terminal SCAN-P, when the first output signal terminal SCAN-P outputs a high level and the first transistor T1 is turned off, the potential of the first node Q is continuously pulled high due to the bootstrap action of the second capacitor C2, the first node Q is a high level signal, the first end of the seventh transistor T7 of the first output unit 301 is electrically connected to the power low level terminal VGL, the second end thereof is electrically connected to the first output signal terminal SCAN-P, the control end thereof is electrically connected to the first node Q, and the seventh transistor T7 is turned off. The fifth transistor T5 of the second node control unit 102 has a first terminal electrically connected to the power high terminal VGH, a second terminal electrically connected to the second node QB, a control terminal electrically connected to the first node Q, and a turn-off state of the fifth transistor T5.
The twelfth transistor T12 of the first inverting unit 201 responds to the high level of the first node Q, the twelfth transistor T12 is turned on, the eleventh transistor T11 is turned off, and the low level of the power source low level terminal VGL is provided to the third node Q1, that is, the potential of the third node Q1 is opposite to the high level signal of the first node Q.
The ninth transistor T9 of the second output unit 302 has a first terminal electrically connected to the power low level terminal VGL, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the third node Q1, so that the third node Q1 is at a low level, the ninth transistor T9 is turned on, and the low level of the power low level terminal VGL is provided to the second output signal terminal SCAN-N, i.e. the second output signal terminal SCAN-N outputs a low level.
It should be noted that, in the first output unit 301 of the present embodiment, the sixth transistor T6 has a first end electrically connected to the first inverting unit 201 (i.e., the second end of the first transistor T1), a second end electrically connected to the first node Q, and a control end electrically connected to the power low-level end VGL; a fifteenth transistor T15 of the second output unit 302, having a first terminal electrically connected to the first inverting unit 201, a second terminal electrically connected to the third node Q1, and a control terminal electrically connected to the power low level terminal VGL; that is, the sixth transistor T6 and the fifteenth transistor T15 are always IN a conducting state, so that a certain voltage difference can be maintained between the first terminal and the second terminal of the sixth transistor T6 (i.e., the first node Q and the sixth node QQ), and the first terminal and the second terminal of the fifteenth transistor T15 (i.e., the third node Q1 and the sixth node QQ), when the potentials of the first node Q and the third node Q1 are low (e.g., equal to-14V or lower), if the sixth transistor T6 and the fifteenth transistor T15 are not provided, the first node Q is directly connected to the second terminal of the first transistor T1 to which the input control signal terminal IN is input, and the input control signal terminal IN has a time (e.g., 8V) of outputting a high level, when the voltage difference between the first terminal and the second terminal of the first transistor T1 reaches 22V, the first transistor T1 is easily broken down. Similarly, if the third node Q1 is directly connected to the second terminal of the eleventh transistor T11 at the input of the power high terminal VGH, which has a timing (e.g., 8V) of outputting a high level, the voltage difference between the first terminal and the second terminal of the eleventh transistor T11 reaches 22V at this time, and the eleventh transistor T11 is easily broken down. As can be seen from the above, the sixth transistor T6 and the fifteenth transistor T15 are provided, so that when the potentials of the first node Q and the third node Q1 are low, the potentials of the first node Q and the third node Q1 can be prevented from being transited through the sixth node QQ by the two transistors which are always turned on, the voltage difference between two ends of the transistor connected to the first node Q and the third node Q1 is not too large, the transistor is prevented from being broken down, and the whole circuit is protected.
Referring to fig. 2, 3 and 5, fig. 5 is another circuit analysis diagram of the shift register of fig. 3 at the first stage, and at the first stage T1, the method further includes providing a high level to the input control signal terminal IN and the second clock signal terminal CK2, providing a low level to the first clock signal terminal CK1, turning on the first transistor T1, turning off the second transistor T2, turning off the third transistor T3, charging the high level signal of the input control signal terminal IN to the first node Q through the first transistor T1, and keeping the potential of the first node Q at the high level. When the first node Q maintains the high-level signal, the seventh transistor T7 of the first output unit 301 has a first terminal electrically connected to the power low-level terminal VGL, a second terminal electrically connected to the first output signal terminal SCAN-P, and a control terminal electrically connected to the first node Q, such that the seventh transistor T7 is turned off. The fifth transistor T5 of the second node control unit 102 has a first terminal electrically connected to the power high voltage terminal VGH, a second terminal electrically connected to the second node QB, and a control terminal electrically connected to the first node Q, such that the fifth transistor T5 is turned off.
The first end of the first capacitor C1 is electrically connected to the fifth node N, the second end thereof is electrically connected to the first clock signal terminal CK1, due to the bootstrap action of the first capacitor C1, the voltage level of the second end of the first capacitor C1 is pulled low by the low level provided by the first clock signal terminal CK1, the voltage level of the first end of the first capacitor C1 is also pulled low, that is, the voltage level of the fifth node N is pulled low to be a low voltage signal, at this time, because the first end of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the second end thereof is electrically connected to the second node QB, the control end thereof is electrically connected to the fifth node N, the fourth transistor T4 is turned on, the low voltage signal of the first clock signal terminal CK1 is charged to the second node QB through the fourth transistor T4, and the voltage level of the second node QB is kept at a low voltage level;
the eighth transistor T8 of the first output unit 301 turns on in response to the low level of the second node QB, and continues to supply the high level of the power supply high level terminal VGH to the first output signal terminal SCAN-P, i.e., the first output signal terminal SCAN-P keeps outputting the high level.
The thirteenth transistor T13 of the second inverting unit 202 responds to the low level of the second node QB, the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and continues to supply the high level of the power source high level terminal VGH to the fourth node QB1, i.e., the potential of the fourth node QB1 is opposite to the low level signal of the second node QB. The tenth transistor T10 of the second output unit 302 has a first terminal electrically connected to the power high terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB1, and thus the tenth transistor T10 is turned off when the fourth node QB1 is at a high level.
The twelfth transistor T12 of the first inverting unit 201 continues to respond to the high level of the first node Q, the twelfth transistor T12 is turned on, the eleventh transistor T11 is turned off, and the low level of the power low level terminal VGL continues to be supplied to the third node Q1, i.e., the potential of the third node Q1 is opposite to the high level signal of the first node Q.
The ninth transistor T9 of the second output unit 302 has a first terminal electrically connected to the power low level terminal VGL, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the third node Q1, so that the third node Q1 is at a low level, the ninth transistor T9 is turned on, and the low level of the power low level terminal VGL is continuously provided to the second output signal terminal SCAN-N, i.e., the second output signal terminal SCAN-N keeps outputting a low level.
Referring to fig. 2, 3 and 6 IN combination, fig. 6 is a circuit analysis diagram of the shift register of fig. 3 at the second stage, at the second stage T2, a low level is provided to the input control signal terminal IN and the first clock signal terminal CK1, a high level is provided to the second clock signal terminal CK2, the first transistor T1 is turned on, the second transistor T2 is turned on, the third transistor T3 is turned off, a low level signal of the input control signal terminal IN is charged into the first node Q through the first transistor T1, and a potential of the first node Q becomes a low level. When the first node Q is the low potential signal, the fifth transistor T5 of the second node control unit 102 has a first terminal electrically connected to the power high-level terminal VGH, a second terminal electrically connected to the second node QB, and a control terminal electrically connected to the first node Q, so that the fifth transistor T5 is turned on, the high potential signal of the power high-level terminal VGH is charged into the second node QB through the fifth transistor T5, and the second node QB becomes the high potential; the eighth transistor T8 of the first output unit 301 has a first terminal electrically connected to the power high voltage terminal VGH, a second terminal electrically connected to the first output signal terminal SCAN-P, and a control terminal electrically connected to the second node QB, wherein the eighth transistor T8 is turned off when the second node QB is at a high voltage level. The seventh transistor T7 of the first output unit 301 has a first end electrically connected to the power low level terminal VGL, a second end electrically connected to the first output signal terminal SCAN-P, and a control end electrically connected to the first node Q, wherein the first node Q is a low level signal, the seventh transistor T7 is turned on, the low level signal of the power low level terminal VGL is charged into the first output signal terminal SCAN-P through the seventh transistor T7, and the first output signal terminal SCAN-P becomes a low level.
The eleventh transistor T11 of the first inverting unit 201 responds to the low level of the first node Q, the twelfth transistor T12 is turned off, the eleventh transistor T11 is turned on, and the high level of the power high level terminal VGH is supplied to the third node Q1, i.e., the potential of the third node Q1 is opposite to the low level signal of the first node Q. The ninth transistor T9 of the second output unit 302 has a first terminal electrically connected to the power low level terminal VGL, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the third node Q1, wherein the third node Q1 is at a high potential, and the ninth transistor T9 is turned off.
The fourteenth transistor T14 of the second inverting unit 202 is responsive to the high level of the second node QB, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned on, and supplies the low level of the power source low level terminal VGL to the fourth node QB1, i.e., the potential of the fourth node QB1 is opposite to the high level signal of the second node QB. The tenth transistor T10 of the second output unit 302 has a first terminal electrically connected to the power high-level terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB1, and since the fourth node QB1 is low, the tenth transistor T10 is turned on, a high-level signal of the power high-level terminal VGH is charged into the second output signal terminal SCAN-N through the tenth transistor T10, and the second output signal terminal SCAN-N becomes a high level.
Referring to fig. 2, 3 and 7 IN combination, fig. 7 is a circuit analysis diagram of the shift register of fig. 3 at a third stage, where IN the third stage T3, a high level is provided to the input control signal terminal IN and the first clock signal terminal CK1, a low level is provided to the second clock signal terminal CK2, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned on, since the third transistor T3 has a first end electrically connected to the power high-level terminal VGH, a second end electrically connected to the fifth node N, and a control end electrically connected to the second clock signal terminal CK2, the fifth node N is a high-level signal of the power high-level terminal VGH, and the fourth transistor T4 is turned off. Although the sixth transistor T6 is in the on state all the time, since the first transistor T1 is turned off, the potential of the first node Q maintains the low potential signal of the second stage T2. The seventh transistor T7 of the first output unit 301 has a first end electrically connected to the power low level end VGL, a second end electrically connected to the first output signal end SCAN-P, and a control end electrically connected to the first node Q, at this time, the potential of the first node Q keeps the low potential signal of the second stage T2 unchanged, the seventh transistor T7 keeps the conducting state, the low potential signal of the power low level end VGL continues to charge the first output signal end SCAN-P through the seventh transistor T7, and the first output signal end SCAN-P continues to keep the low potential.
When the first node Q continues to maintain the low level signal, the fifth transistor T5 of the second node control unit 102 has a first terminal electrically connected to the power high-level terminal VGH, a second terminal electrically connected to the second node QB, and a control terminal electrically connected to the first node Q, so that the fifth transistor T5 maintains the on state, the high level signal of the power high-level terminal VGH continues to be charged into the second node QB through the fifth transistor T5, and the second node QB maintains the high level.
The eleventh transistor T11 of the first inverting unit 201 continues to respond to the low level of the first node Q, the twelfth transistor T12 is turned off, the eleventh transistor T11 is turned on, and the high level of the power high level terminal VGH continues to be supplied to the third node Q1, i.e., the potential of the third node Q1 continues to be maintained opposite to the low level signal of the first node Q. The ninth transistor T9 of the second output unit 302 has a first terminal electrically connected to the power low-level terminal VGL, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the third node Q1, wherein the third node Q1 is kept at a high potential, and the ninth transistor T9 is kept at an off state.
The fourteenth transistor T14 of the second inverting unit 202 continues to respond to the high level of the second node QB, the thirteenth transistor T13 is turned off, the fourteenth transistor T14 is turned on, and continues to supply the low level of the power source low level terminal VGL to the fourth node QB1, i.e., the potential of the fourth node QB1 is maintained opposite to the high level signal of the second node QB. The tenth transistor T10 of the second output unit 302 has a first terminal electrically connected to the power high-level terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB1, because the fourth node QB1 is kept at a low level, the tenth transistor T10 is kept in a conductive state, the high-level signal of the power high-level terminal VGH is continuously charged into the second output signal terminal SCAN-N through the tenth transistor T10, and the second output signal terminal SCAN-N keeps a high level unchanged.
Referring to fig. 2, fig. 3 and fig. 8 IN combination, fig. 8 is a circuit analysis diagram of the shift register IN fig. 3 at a fourth stage, IN which at a fourth stage T4, a high level is provided to the input control signal terminal IN and the second clock signal terminal CK2, a low level is provided to the first clock signal terminal CK1, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, a high potential signal of the input control signal terminal IN is charged into the first node Q through the first transistor T1, and a potential of the first node Q is changed from a low potential to a high potential at the third stage T3.
When the first node Q is a high signal, the first end of the seventh transistor T7 of the first output unit 301 is electrically connected to the power low level terminal VGL, the second end thereof is electrically connected to the first output signal terminal SCAN-P, the control end thereof is electrically connected to the first node Q, and the seventh transistor T7 is turned off. The fifth transistor T5 of the second node control unit 102 has a first terminal electrically connected to the power high voltage terminal VGH, a second terminal electrically connected to the second node QB, and a control terminal electrically connected to the first node Q, such that the fifth transistor T5 is turned off.
The first end of the first capacitor C1 is electrically connected to the fifth node N, the second end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and due to the bootstrap effect of the first capacitor C1, the potential of the second end of the first capacitor C1 is pulled down as the first clock signal terminal CK1 changes from the high potential to the low potential of the third stage t3, and the potential of the first end of the first capacitor C1 is also pulled down, that is, the potential of the fifth node N is pulled down to a low potential signal; at this time, since the first terminal of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the second terminal thereof is electrically connected to the second node QB, and the control terminal thereof is electrically connected to the fifth node N, the fourth transistor T4 is turned on, the low potential signal of the first clock signal terminal CK1 is charged to the second node QB through the fourth transistor T4, and the potential of the second node QB is changed from the high potential of the third stage T3 to the low potential.
The eighth transistor T8 of the first output unit 301 is turned on in response to the low level of the second node QB, and provides the high level of the power supply high level terminal VGH to the first output signal terminal SCAN-P, i.e., when the first output signal terminal SCAN-P becomes an output high level.
The thirteenth transistor T13 of the second inverting unit 202 is responsive to the low level of the second node QB, the thirteenth transistor T13 is turned on, the fourteenth transistor T14 is turned off, and provides the high level of the power source high level terminal VGH to the fourth node QB1, i.e., the potential of the fourth node QB1 is opposite to the low level signal of the second node QB. The tenth transistor T10 of the second output unit 302 has a first terminal electrically connected to the power high terminal VGH, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the fourth node QB1, and thus the tenth transistor T10 is turned off when the fourth node QB1 is at a high level.
The twelfth transistor T12 of the first inverting unit 201 responds to the high level of the first node Q, the twelfth transistor T12 is turned on, the eleventh transistor T11 is turned off, and the low level of the power source low level terminal VGL is provided to the third node Q1, that is, the potential of the third node Q1 is opposite to the high level signal of the first node Q.
The ninth transistor T9 of the second output unit 302 has a first terminal electrically connected to the power low level terminal VGL, a second terminal electrically connected to the second output signal terminal SCAN-N, and a control terminal electrically connected to the third node Q1, so that the third node Q1 is at a low level, the ninth transistor T9 is turned on, and the low level of the power low level terminal VGL is provided to the second output signal terminal SCAN-N, i.e., the second output signal terminal SCAN-N becomes an output low level.
After the fourth phase t4, the shift register of the embodiment further continues to loop to the first phase t1 to start to continue operating.
In some alternative embodiments, with reference to fig. 3, in the present embodiment, the eleventh transistor T11 is a polysilicon transistor, and the twelfth transistor T12 is an oxide transistor; and/or, the thirteenth transistor T13 is a polysilicon transistor, and the fourteenth transistor T14 is an oxide transistor.
In the shift register circuit of the present embodiment, as shown in fig. 3, a shift register circuit in a scan driving circuit of a display panel is manufactured by using a low temperature poly-oxide technology, an eleventh transistor T11 is a polysilicon transistor, and a twelfth transistor T12 is an oxide transistor; and/or, the thirteenth transistor T13 is a polysilicon transistor, the fourteenth transistor T14 is an oxide transistor, optionally, the polysilicon transistor is a low temperature polysilicon thin film transistor, and the oxide transistor is a metal oxide thin film transistor, that is, the low temperature polysilicon thin film transistor and the metal oxide thin film transistor are simultaneously used as functional transistors in the scan driving circuit, since the gate time is reduced with the improvement of the resolution, the transistor is required to provide a larger driving current to complete the charging of the capacitor, and as the frame frequency is improved, the current driving capability of the transistor is required to be higher and higher, and the mobility is a key parameter for measuring the current driving capability of the transistor, while the polysilicon transistor of the embodiment has a high mobility, which can accelerate the charging speed of the pixel capacitor, and the oxide transistor has a lower leakage current, by combining the advantages of these two transistors, development of a display product with high resolution, low power consumption, and high image quality is facilitated.
The shift register of the embodiment can simultaneously meet the output of positive and negative pulses, namely when the SCAN-P output of the first output signal terminal is at a high level, the SCAN-N output of the second output signal terminal is at a low level; when the first output signal terminal SCAN-P output is at low level, the second output signal terminal SCAN-N output is at high level. Since the first inverting unit 201 of the present embodiment is located between the first node control unit 101 and the third node Q1, the second inverting unit 202 is located between the first node control unit 102 and the fourth node QB1, and the potential signals of the third node Q1 and the fourth node QB1 only need to be used for driving several transistors in the second output unit 302, the first inverting unit 201 and the second inverting unit 202 connected to the third node Q1 and the fourth node QB1 do not need strong driving capability, and further the low temperature polysilicon thin film transistor and the metal oxide thin film transistor as the functional transistors in the scan driving circuit do not need to occupy large space layout, which is beneficial to satisfying the driving capability and reducing the manufacturing size.
It should be noted that, in the shift register circuit in the prior art, a CMOS circuit is generally used as an inverting unit circuit (a basic unit circuit inverter of the CMOS circuit is composed of N-channel and P-channel low-temperature polysilicon transistors, and works in a push-pull manner, and an integrated circuit capable of implementing a certain logic function, referred to as a CMOS for short), because other control units and transistors of an output unit of the shift register circuit in this embodiment are P-channel low-temperature polysilicon transistors (or N-channel low-temperature polysilicon transistors, which are different in channel doping), if the inverting unit is also used as the CMOS circuit in the prior art, the manufacturing process of the N-channel low-temperature polysilicon transistors is inevitably increased, and the manufacturing process efficiency is further affected.
In some optional embodiments, please refer to fig. 3, 9 and 10 in combination, fig. 9 is a schematic plane structure diagram of a display panel 000 according to an embodiment of the present invention, fig. 10 is a schematic structure diagram of a pixel circuit in fig. 9, and a display panel 000 according to an embodiment of the present invention includes: a plurality of pixel circuits 10; at least one scan driving circuit 20, the scan driving circuit 20 including a plurality of shift registers 30, the shift registers 30 being any one of the shift registers of the above embodiments; the first and second output signal terminals SCAN-P and SCAN-N of the shift register 30 are electrically connected to the pixel circuit 10.
Alternatively, a plurality of shift registers 30 in the scan driving circuit 20 are arranged in cascade; the input control signal terminal of the mth stage shift register is electrically connected to the first output signal terminal SCAN-P of the (M-1) th stage shift register, where M is an integer, M is greater than or equal to 2 and less than or equal to M, and M is the number of shift registers 30 in the SCAN driving circuit 20. That is, the input control signal terminal of the first stage shift register provides the start control signal through the external circuit, and the input control signal terminal of the second stage shift register is electrically connected to the first output signal terminal SCAN-P of the first stage shift register, that is, the output signal of the first output signal terminal SCAN-P of the first stage shift register provides the control signal of the input control signal terminal of the second stage shift register, and so on.
Specifically, a pixel circuit in the prior art is generally shown in fig. 11, fig. 11 is a schematic structural diagram of a pixel circuit in the prior art, a pixel circuit in the prior art OLED panel generally adopts a 7T1C circuit shown in fig. 11, wherein 7T (7 transistors) are all composed of PMOS, and a scan signal connected to a scan line only needs to be input by S-p. In the pixel circuit 10 of the display panel 000 of the present embodiment, oxide TFTs (M4 and M5 in fig. 10, which are both N-type TFTs) are introduced, so S2-N input signal terminals (equivalent to connect the second output signal terminals SCAN-N of the shift register provided by the present embodiment) in fig. 10 and S2-P input signal terminals (equivalent to connect the first output signal terminals SCAN-P of the shift register provided by the present embodiment) in fig. 10 need to be added, that is, the first output signal terminals SCAN-P and the second output signal terminals SCAN-N of the shift register provided by the present embodiment need to be electrically connected to the pixel circuit in fig. 10.
In the pixel circuit 10 of the present embodiment, since oxide TFTs (M4 and M5 in fig. 10, which are mostly N-type TFTs) are introduced during the manufacturing process, the shift register 30 circuit designed in the present embodiment is designed by designing the eleventh transistor T11 as a polysilicon transistor and the twelfth transistor T12 as an oxide transistor; and/or, the thirteenth transistor T13 is a polysilicon transistor, and the fourteenth transistor T14 is an oxide transistor, which can avoid the additional fabrication of N-channel low temperature polysilicon transistors on the peripheral shift register 30 circuit, thereby improving the fabrication efficiency. Moreover, the inverting unit of the embodiment acts on the third node Q1 and the fourth node QB1 of the shift register 30 circuit, and the potential signals of the third node Q1 and the fourth node QB1 only need to be used for driving a few transistors in the second output unit 302, so that a strong driving capability is not needed, even if the mobility of the oxide transistor is low, a large-sized oxide transistor does not need to be manufactured, a large-space layout is avoided, and the manufacturing size is reduced while the driving capability is satisfied.
It should be noted that fig. 9 of this embodiment only schematically illustrates a structure of the display panel 000 related to the technical solution of the embodiment of the present invention, and it is understood that the display panel 000 of this embodiment further includes other structures for implementing a display function, for example, optionally, the display panel 000 may further include a plurality of scan lines and a plurality of data lines (not shown in the figure), the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixels, and each pixel includes the pixel circuit 10 provided in this embodiment, and may further include a data line driving circuit, a voltage supply unit, and the like.
As can be seen from the above embodiments, the shift register, the control method thereof, and the display panel provided by the present invention at least achieve the following beneficial effects:
the shift register can simultaneously meet the output of positive and negative pulses, namely when the output of a first output signal end is at a high level, the output of a second output signal end is at a low level; when the output of the first output signal terminal is at low level, the output of the second output signal terminal is at high level. Because the first phase reversal unit is positioned between the first node control unit and the third node, the second phase reversal unit is positioned between the first node control unit and the fourth node, and potential signals of the third node and the fourth node only need to be used for driving the second output unit, the first phase reversal unit and the second phase reversal unit connected with the third node and the fourth node do not need strong driving capability and further do not need to occupy larger space layout.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (11)
1. A shift register, comprising:
a first node control unit electrically connected to an input control signal terminal and a first clock signal terminal, for providing a low level to a first node according to signals of the input control signal terminal and the first clock signal terminal;
a second node control unit electrically connected to the input control signal terminal, the first clock signal terminal, the second clock signal terminal, and the first node, for providing a low level to the second node according to signals of the input control signal terminal, the first clock signal terminal, and the second clock signal terminal, and for providing a high level to the second node in response to the low level of the first node;
a first output unit electrically connected to the first node and the second node, for providing a low level to a first output signal terminal in response to a low level of the first node, and for providing a high level to the first output signal terminal in response to a low level of the second node;
a first inverting unit electrically connected to the first node, for supplying a potential opposite to a potential of the first node to a third node;
a second inverting unit electrically connected to the second node, for supplying a potential opposite to a potential of the second node to a fourth node;
and a second output unit electrically connected to the third node and the fourth node, for providing a low level to a second output signal terminal in response to a low level of the third node, and for providing a high level to the second output signal terminal in response to a low level of the fourth node.
2. The shift register of claim 1,
the first node control unit includes:
a first end of the first transistor is electrically connected to the input control signal end, a second end of the first transistor is electrically connected to the first node, and a control end of the first transistor is electrically connected to the first clock signal end.
3. The shift register of claim 1,
the second node control unit includes:
a first end of the second transistor is electrically connected to a power supply high-level end, a second end of the second transistor is electrically connected to the fifth node, and a control end of the second transistor is electrically connected to the input control signal end;
a third transistor having a first end electrically connected to the high-level end of the power supply, a second end electrically connected to the fifth node, and a control end electrically connected to the second clock signal end;
a fourth transistor having a first terminal electrically connected to the first clock signal terminal, a second terminal electrically connected to the second node, and a control terminal electrically connected to the fifth node;
a first end of the first capacitor is electrically connected to the fifth node, and a second end of the first capacitor is electrically connected to the first clock signal terminal.
4. The shift register of claim 3,
the second node control unit further includes:
a fifth transistor, a first end of which is electrically connected to the high-level end of the power supply, a second end of which is electrically connected to the second node, and a control end of which is electrically connected to the first node.
5. The shift register of claim 1,
the first output unit includes:
a seventh transistor, a first end of which is electrically connected to a low level end of a power supply, a second end of which is electrically connected to the first output signal end, and a control end of which is electrically connected to the first node;
a second capacitor having a first end electrically connected to the first node and a second end electrically connected to the first output signal end;
a first end of the eighth transistor is electrically connected to a power supply high-level end, a second end of the eighth transistor is electrically connected to the first output signal end, and a control end of the eighth transistor is electrically connected to the second node; and/or the presence of a gas in the gas,
the second output unit includes:
a ninth transistor, a first end of which is electrically connected to the low level end of the power supply, a second end of which is electrically connected to the second output signal end, and a control end of which is electrically connected to the third node;
a third capacitor having a first end electrically connected to the third node and a second end electrically connected to the second output signal terminal;
a tenth transistor, a first end of which is electrically connected to the high-level end of the power supply, a second end of which is electrically connected to the second output signal end, and a control end of which is electrically connected to the fourth node.
6. The shift register of claim 5,
the first output unit further includes:
a sixth transistor, a first end of which is electrically connected to the first inverting unit, a second end of which is electrically connected to the first node, and a control end of which is electrically connected to the power low level end.
7. The shift register of claim 1,
the first inverting unit includes an eleventh transistor for providing a high level to the third node in response to a low level of the first node, and a twelfth transistor for providing a low level to the third node in response to a high level of the first node; and/or the presence of a gas in the gas,
the second inverting unit includes a thirteenth transistor for providing a high level to the fourth node in response to a low level of the second node, and a fourteenth transistor for providing a low level to the fourth node in response to a high level of the second node.
8. The shift register of claim 7,
the eleventh transistor is a polysilicon transistor, and the twelfth transistor is an oxide transistor; and/or the presence of a gas in the gas,
the thirteenth transistor is a polysilicon transistor, and the fourteenth transistor is an oxide transistor.
9. A control method of a shift register is characterized in that,
the shift register includes:
a first node control unit electrically connected to an input control signal terminal and a first clock signal terminal, for providing a low level to a first node according to signals of the input control signal terminal and the first clock signal terminal;
a second node control unit electrically connected to the input control signal terminal, the first clock signal terminal, the second clock signal terminal, and the first node, for providing a low level to the second node according to signals of the input control signal terminal, the first clock signal terminal, and the second clock signal terminal, and for providing a high level to the second node in response to the low level of the first node;
a first output unit electrically connected to the first node and the second node, for providing a low level to a first output signal terminal in response to a low level of the first node, and for providing a high level to the first output signal terminal in response to a low level of the second node;
a first inverting unit electrically connected to the first node, for supplying a potential opposite to a potential of the first node to a third node;
a second inverting unit electrically connected to the second node, for supplying a potential opposite to a potential of the second node to a fourth node;
a second output unit electrically connected to the third node and the fourth node, for providing a low level to a second output signal terminal in response to a low level of the third node, and for providing a high level to the second output signal terminal in response to a low level of the fourth node;
the control method comprises the following steps:
a first stage of providing a high level to the input control signal terminal and the first clock signal terminal and a low level to the second clock signal terminal, the first output unit providing a high level to the first output signal terminal in response to a low level of the second node, the second output unit providing a low level to the second output signal terminal in response to a low level of the third node; and the number of the first and second groups,
providing a high level to the input control signal terminal and the second clock signal terminal, providing a low level to the first clock signal terminal, providing a high level to the first output signal terminal in response to a low level of the second node, and providing a low level to the second output signal terminal in response to a low level of the third node;
a second stage of providing a low level to the input control signal terminal and the first clock signal terminal and a high level to the second clock signal terminal, the first output unit providing a low level to the first output signal terminal in response to the low level of the first node, the second output unit providing a high level to the second output signal terminal in response to the low level of the fourth node;
a third stage of providing a high level to the input control signal terminal and the first clock signal terminal and a low level to the second clock signal terminal, the first output unit providing a low level to the first output signal terminal in response to the low level of the first node, and the second output unit providing a high level to the second output signal terminal in response to the low level of the fourth node;
and a fourth stage of providing a high level to the input control signal terminal and the second clock signal terminal and a low level to the first clock signal terminal, wherein the first output unit provides a high level to the first output signal terminal in response to a low level of the second node, and the second output unit provides a low level to the second output signal terminal in response to a low level of the third node.
10. A display panel, comprising:
a plurality of pixel circuits;
at least one scan driving circuit, the scan driving circuit comprising a plurality of shift registers, the shift registers being as claimed in any one of claims 1 to 8;
and the first output signal end and the second output signal end of the shift register are electrically connected with the pixel circuit.
11. The display panel according to claim 10,
a plurality of shift registers in the scanning driving circuit are arranged in a cascade mode;
and the input control signal end of the mth stage of the shift register is electrically connected to the first output signal end of the (M-1) th stage of the shift register, wherein M is an integer, M is more than or equal to 2 and less than or equal to M, and M is the number of the shift registers in the scanning drive circuit.
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| CN111627372B (en) * | 2020-06-30 | 2022-07-26 | 武汉天马微电子有限公司 | Shift register and circuit thereof, display panel and electronic equipment |
| CN112509513A (en) * | 2020-12-15 | 2021-03-16 | 云谷（固安）科技有限公司 | Shift register, display panel and display device |
| CN112785959B (en) * | 2021-02-05 | 2024-05-10 | 厦门天马微电子有限公司 | Inverter, driving method thereof, driving circuit and display panel |
| CN113380199B (en) * | 2021-06-07 | 2022-11-25 | 中国科学院微电子研究所 | Gate drive circuit, drive method and GOA circuit |
| CN113763886B (en) * | 2021-10-29 | 2023-01-10 | 京东方科技集团股份有限公司 | Shift register, driving circuit, display panel and display device |
| CN115938324A (en) * | 2022-11-22 | 2023-04-07 | 武汉华星光电半导体显示技术有限公司 | GOA circuit and display panel |
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| CN102651239B (en) * | 2012-03-29 | 2014-06-18 | 京东方科技集团股份有限公司 | Shift register, driver circuit and display device |
| CN104809979B (en) * | 2015-05-26 | 2017-07-18 | 京东方科技集团股份有限公司 | A kind of phase inverter and driving method, GOA unit, GOA circuits and display device |
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| CN109841194B (en) * | 2017-11-27 | 2020-04-10 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
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