CN108389559A - Shift register module and driving method, gate driving circuit and display device - Google Patents
Shift register module and driving method, gate driving circuit and display device Download PDFInfo
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- CN108389559A CN108389559A CN201810416513.9A CN201810416513A CN108389559A CN 108389559 A CN108389559 A CN 108389559A CN 201810416513 A CN201810416513 A CN 201810416513A CN 108389559 A CN108389559 A CN 108389559A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention belongs to display technology fields, are related to shift register module and driving method, gate driving circuit and display device.The shift register module includes input sub-circuit, shift LD sub-circuit, output sub-circuit and exports caching sub-circuit, wherein：Sub-circuit is inputted according to signal opposite first control signal and second control signal, second input signal of the first input signal and lag a cycle to the advanced a cycle of shift signal to be output with shift LD sub-circuit respectively is screened, and will screen signal transmission to shift LD sub-circuit；Shift LD sub-circuit shifts screening signal according to the first clock signal；Sub-circuit is exported according to second clock signal, is drive signal by the screening signal modulation after displacement；Output caching sub-circuit enhances the driving capability of output drive signal or blocks the output of drive signal according to enable signal.Which obviate stabilizing influence is shown caused by ghost effect when display switches with touch-control.
Description
Technical field
The invention belongs to display technology fields, and in particular to a kind of drive of shift register module, shift register module
Dynamic method, gate driving circuit and display device.
Background technology
In field of liquid crystal, array substrate row actuation techniques (Gate Driver on Array, abbreviation GOA) be by
Gate driving circuit is integrated in the circuit of liquid crystal display panel, has been widely used at present, and GOA circuits are by by gate driving
Circuit succession replaces traditional Gate IC on array substrate, therefore can reduce IC usage amounts, and there is reduction to be produced into
Originally, the advantages that reducing production process.
As the competition of liquid crystal display panel industry tends to be fierce, reduces panel cost and improving performance becomes panel vendor's competition spot,
Each pixel for being adopted as viewing area of GOA circuits provides stable driving, improves the performance of display panel well.And
And with the diversification of display product function, touch-control (Touch) also becomes than matching one of function.In touch-control working condition or picture
When plain repid discharge state and other special states, gate scanning circuit output still has electrically with gate lines and All other routes
Connection, causes to have an impact because of ghost effect in above-mentioned particular state.
How to ensure to show stabilizing influence caused by ghost effect when display switches with touch-control, becomes urgently to be resolved hurrily at present
The technical issues of.
Invention content
The technical problem to be solved by the present invention is to be directed to above-mentioned deficiency in the prior art, a kind of shift register mould is provided
Block, the driving method of shift register module, gate driving circuit and display device can effectively avoid display from switching with touch-control
When stabilizing influence is shown caused by ghost effect.
Technical solution is the shift register module used by solving present invention problem, including cascades setting successively
Input sub-circuit, shift LD sub-circuit, output sub-circuit and output caching sub-circuit, wherein：
The input sub-circuit, with the first input signal end, the second input signal end, first control signal end and the second control
Signal end connection processed is used for according to signal opposite first control signal and second control signal, to being posted respectively with the displacement
Deposit the first input signal of the advanced a cycle of sub-circuit shift signal to be output and the second input letter of lag a cycle
Number screened, and will screening signal transmission to the shift LD sub-circuit；
The shift LD sub-circuit, connect with the first clock signal terminal and low level voltage end, when for according to first
Clock signal shifts the screening signal；
The output sub-circuit, connect with second clock signal end and low level voltage end, for being believed according to second clock
Number, it is drive signal by the screening signal modulation after displacement；
The output caches sub-circuit, is connect with enable signal end, high level voltage end and low level voltage end, is used for root
According to enable signal, enhancing exports the driving capability of the drive signal or blocks the output of the drive signal.
Preferably, the input sub-circuit includes the first transmission gate and the second transmission gate, wherein：
First transmission gate, input terminal connect the first input signal end, and the first control terminal connects first control signal
End, the second control terminal connect second control signal end, and output end connects the input terminal of the shift LD sub-circuit；
Second transmission gate, input terminal connect the second input signal end, and the first control terminal connects second control signal
End, the second control terminal connect first control signal end, and output end connects the input terminal of shift LD sub-circuit.
Preferably, the shift LD sub-circuit includes third nor gate, the 4th phase inverter, the 5th transmission gate and the 6th
Transistor, wherein：
The third nor gate, first input end connect the output end of the input sub-circuit, the connection of the second input terminal
The output end of 5th transmission gate, output end connect the input terminal of the 4th phase inverter；
4th phase inverter, output end connect the first control terminal of the 5th transmission gate；
5th transmission gate, input terminal connect the first clock signal terminal, and the second control terminal connects third nor gate
Output end, output end are also connected with the input terminal of the output sub-circuit；
6th transistor, control terminal connect the output end of the third nor gate, and the first pole connects low level end,
Second pole connects the output end of the 5th transmission gate.
Preferably, the output sub-circuit includes the 7th phase inverter, the 8th transmission gate, the 9th phase inverter and the tenth crystal
Pipe, wherein：
7th phase inverter, input terminal connect the output end of the shift LD sub-circuit, described in output end connection
The input terminal of second control terminal of the 8th transmission gate and the 9th phase inverter；
8th transmission gate, input terminal connect second clock signal end, and the first control terminal connects the 9th reverse phase
The output end of device, output end connect the input terminal of the second pole and the output caching sub-circuit of the tenth transistor；
Tenth transistor, control terminal connect the output end of the 9th phase inverter, and the first pole connects low level electricity
Pressure side.
Preferably, the output caching sub-circuit includes the 11st phase inverter, the 12nd field-effect tube, the 13rd effect
Ying Guan, the 14th field-effect tube and the 15th field-effect tube, wherein：
11st phase inverter, input terminal connect the output end of the output sub-circuit, output end connection described the
The control terminal of the control terminal of 12 field-effect tube and the 15th field-effect tube；
12nd field-effect tube, the first pole connect high level voltage end, the second pole connection the 13rd effect
Should pipe the first pole；
13rd field-effect tube, control terminal connect the first enable signal end, described 14th of the second pole connection
First pole of effect pipe；
14th field-effect tube, control terminal connect the second enable signal end, described 15th of the second pole connection
First pole of effect pipe；
15th field-effect tube, the second pole connect low level voltage signal end.
A kind of driving method of above-mentioned shift register module, including input phase, shift LD stage, output stage
With output the caching stage, wherein：
Input phase, according to signal opposite first control signal and second control signal, to being posted respectively with the displacement
Deposit the first input signal of the advanced a cycle of sub-circuit shift signal to be output and the second input letter of lag a cycle
Number screened, and will screening signal transmission to the shift LD sub-circuit；
The shift LD stage shifts the screening signal according to the first clock signal；
The screening signal modulation after displacement is drive signal according to second clock signal by the output stage；
The caching stage is exported, the driving capability of the drive signal is exported according to enable signal enhancing or blocks the drive
The output of dynamic signal.
Preferably, the pulse width of the second clock signal is the one of the pulse width of first clock signal
Partly, the pulse width of first input signal and second input signal is respectively that the pulse of first clock signal is wide
Twice of degree, the pulse width of the drive signal are the half of the pulse width of first clock signal.
Preferably, when display function：Export caching stage, the level phase of the first enable signal and the second enable signal
Instead, enable signal enhancing exports the driving capability of the drive signal, which exports high level or low level；
When touch function：Enable signal blocks the output of the drive signal, which is presented high-impedance state
State.
A kind of gate driving circuit, including above-mentioned shift register module, multiple shift register module cascades
Connection, wherein：
Output signal from shift LD sub-circuit described in shift register module described in upper level and from next
The output signal of shift LD sub-circuit, respectively this grade of shift register mould described in the grade shift register module
First input signal and second input signal of block.
A kind of display device, including above-mentioned gate driving circuit.
The beneficial effects of the invention are as follows：
Include the output of p-type field-effect tube and N-type field-effect tube by increase in the shift register module of the present embodiment
Sub-circuit is cached, in conjunction with the switch of enable signal control field-effect tube (M13, M14), can not only export height when normal display
Low level (EN is low level,For high level), and when can export touch-control high-impedance state (EN is high level,It is low
Level) so that output signal generates three kinds of states, in touch-control working condition or pixel repid discharge state and other are special
State can be such that the output of shift register module is disconnected with gate lines and All other routes completely, have low noise, work is more
Stablize, the stronger advantage of driving capability；
The gate driving circuit is as a result of above-mentioned shift register module, in touch-control working condition or pixel
Repid discharge state and other special states can be such that the output of GOA circuits is disconnected with gate lines and All other routes completely, avoid
In above-mentioned particular state because ghost effect has an impact display circuit part, there is low noise, work more to stablize, driving
The stronger advantage of ability promotes yield with this more preferable raising panel performance.
Description of the drawings
Fig. 1 is the functional block diagram of shift register module in the embodiment of the present invention 1；
Fig. 2 is the circuit diagram of shift register module in the embodiment of the present invention 1；
Fig. 3 is the working timing figure of shift register module in the embodiment of the present invention 1；
Fig. 4 is the cascade schematic diagram of multiple shift register modules in gate driving circuit in the embodiment of the present invention 2；
In attached drawing mark：
1- inputs sub-circuit；2- shift LD sub-circuits；3- exports sub-circuit；4- output caching sub-circuits.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, below in conjunction with the accompanying drawings and specific embodiment party
Formula to the driving method, gate driving circuit and display device of shift register module of the present invention, shift register module make into
One step is described in detail.
Embodiment 1：
The present embodiment provides a kind of shift register module new construction, by output end addition type field-effect tube, and lead to
The switch for crossing enable signal control field-effect tube, can not only export normal low and high level, but also can export high-impedance state, make
It obtains output signal and generates three kinds of states, can effectively avoid gate driving circuit in particular state because ghost effect is to display circuit
Part has an impact.
It is as shown in Figure 1 the structure diagram of shift register module in the present embodiment.The shift register module include according to
Input sub-circuit 1, shift LD sub-circuit 2, output sub-circuit 3 and the output caching sub-circuit 4 of secondary cascade setting, wherein：
Sub-circuit 1 is inputted, with the first input signal end, the second input signal end, first control signal end and the second control
Signal end connects, for according to signal opposite first control signal and second control signal, to respectively with the shift LD
Second input signal of the first input signal and lag a cycle of the advanced a cycle of the shift signal to be output of sub-circuit 2
It is screened, and signal transmission will be screened to the shift LD sub-circuit 2；
Shift LD sub-circuit 2, for according to the first clock signal, being shifted to the screening signal；
Sub-circuit 3 is exported, for being that driving is believed by the screening signal modulation after displacement according to second clock signal
Number；
Output caching sub-circuit 4, driving capability or resistance for exporting the drive signal according to enable signal enhancing
The output of the disconnected drive signal.
Wherein, the pulse width of second clock signal is the half of the pulse width of the first clock signal, the first input letter
Number and the pulse width of the second input signal be respectively twice of pulse width of the first clock signal, the pulse of drive signal is wide
Degree is the half of the pulse width of the first clock signal.
As shown in Fig. 2, input sub-circuit 1 includes the first transmission gate M1 and the second transmission gate M2, the first transmission gate M1 and the
Two transmission gate M2 are connected with identical a pair of control signal and the control port of connection is opposite.Wherein：First transmission gate M1's is defeated
Enter end the first input signal end of connection (for receiving the first input signal STV_N-1), the first control terminal connection the first control letter
Number end (for receiving first control signal CN), the second control terminal connect second control signal end (for receiving the second control letter
Number CNB), output end connects the input terminal of shift LD sub-circuit 2；The input terminal of second transmission gate M2 connects the second input signal
End (for receiving the second input signal STV_N+1), the first control terminal connect second control signal end (for receiving the second control
Signal CNB), the second control terminal connects first control signal end (for receiving first control signal CN), output end connection displacement
Deposit the input terminal of sub-circuit 2.The level of first control signal and second control signal is opposite.Transmission gate in Fig. 2, left side are
Input terminal, right side are output end, and two opposite control terminals of signal, first control signal CN are high electricity in order to control for the upper side and lower side
Transmission gate is opened when flat, second control signal CNB is low level, and right output signal is left input signal at this time.
Shift LD sub-circuit 2 includes third nor gate M3, the 4th phase inverter M4, the 5th transmission gate M5 and the 6th transistor
M6, wherein：The first input end of third nor gate M3 connects the output of the output end and the second transmission gate M2 of the first transmission gate M1
End (output end for inputting sub-circuit 1), the second input terminal connect the output end of the 5th transmission gate M5, and output end connection the 4th is anti-
The input terminal of phase device M4；The output end of 4th phase inverter M4 connects the first control terminal of the 5th transmission gate M5；5th transmission gate M5
Input terminal connect the first clock signal terminal, the second control terminal connects the output end of third nor gate M3, and output end is also connected with defeated
Go out the input terminal of sub-circuit 3；The output end of the control terminal connection third nor gate M3 of 6th transistor M6, the first pole connects low electricity
Flush end, the second pole connect the output end of the 5th transmission gate M5.After 2 end of output of shift LD sub-circuit, by the 6th transistor M6
It persistently drags down, shift LD sub-circuit 2 is forbidden to export.The pulse for the shift signal (STV_N) that shift LD sub-circuit 2 exports is wide
Degree is identical as the pulse width of the first input signal (STV_N-1) and the second input signal (STV_N+1), and is located in sequential
Between first input signal (STV_N-1) and the second input signal (STV_N+1).
It exports sub-circuit 3 and includes the 7th phase inverter M7, the 8th transmission gate M8, the 9th phase inverter M9 and the tenth transistor M10,
Wherein：The input terminal of 7th phase inverter M7 connects the input terminal (i.e. the output end of shift LD sub-circuit 2) of the 5th transmission gate M5,
Output end connects the input terminal of the second control terminal and the 9th phase inverter M9 of the 8th transmission gate M8；The input terminal of 8th transmission gate M8
Second clock signal end is connected, the first control terminal connects the output end of the 9th phase inverter M9, and output end connects the tenth transistor M10
The second pole and output caching sub-circuit 4 input terminal；The control terminal of tenth transistor M10 connects the output of the 9th phase inverter M9
End, the first pole connect low level voltage end.After exporting 3 end of output of sub-circuit, is persistently dragged down, forbidden by the tenth transistor M10
Sub-circuit 3 is exported to export.The pulse width of second clock signal CKB is the half of the pulse width of the first clock signal CK.
Output caching sub-circuit 4 includes the 11st phase inverter M11, the 12nd field-effect tube M12, the 13rd field-effect tube
M13, the 14th field-effect tube M14 and the 15th field-effect tube M15, wherein：The input terminal connection the 8th of 11st phase inverter M11
The output end output end of sub-circuit 3 (export) of transmission gate M8, output end connect the 12nd field-effect tube M12 control terminal and
The control terminal of 15th field-effect tube M15；The first pole connection high level voltage end of 12nd field-effect tube M12, the second pole connects
Connect the first pole of the 13rd field-effect tube M13；The first enable signal end of control terminal connection of 13rd field-effect tube M13, second
Pole connects the first pole of the 14th field-effect tube M14；The control terminal of 14th field-effect tube M14 connects the second enable signal end,
Second pole connects the first pole of the 15th field-effect tube M15；The second pole connection low level voltage letter of 15th field-effect tube M15
Number end.The level of first enable signal and the second enable signal is on the contrary, the 13rd field-effect tube M13 and the 14th field-effect tube
The connecting pin of M14 is the output end of the shift register module.In Fig. 2, M12 and M13 are p-type field-effect tube, and M14 and M15 are N
Type field-effect tube.
In shift register module provided in this embodiment, all transistors are illustrated by taking N-type transistor as an example,
It is conceivable that replacing N-type transistor using P-type transistor, then needing to invert signal polarity, connection type still remains unchanged,
I will not elaborate.
In the shift register module, high level voltage signal VGH is direct current high level signal, low level voltage signal
VGL is direct current low level signal；First control signal CN and second control signal CNB is a pair of of opposite signal, if CN is high electricity
Flat, then CNB is low level；First enable signal EN and the second enable signal(it is anti-to be illustrated as EN in each figure) is a pair of opposite
Signal, EN is low level during display,For high level；During touch-control, original display scans effective signal and is
Low level, and acted as touch scanning signals, EN is high level,For low level, which is in
Existing high-impedance state state.
Correspondingly, the present embodiment also provides the driving method of shift register module in one.Sequence diagram as shown in Figure 3 with
Forward scan is as an example, otherwise be reverse scan.When forward scan, the original state of CK, CKB are low level；CN is high electricity
Flat, CNB is low level；EN is low level,For high level.
T1 stages, i.e. input phase, according to signal opposite first control signal and second control signal, to respectively with institute
State the advanced a cycle of shift LD sub-circuit shift signal to be output the first input signal and lag a cycle the
Two input signals are screened, and will screen signal transmission to the shift LD sub-circuit.At this time：STV_N-1 is high level,
STV_N+1 is low level, and CK is low level, and CKB is low level, and STV_N-1 is effective at this time, and the first transmission gate M1 is opened, output
STV_N-1, that is, high level；Third nor gate M3 exports low level, and the 4th phase inverter M4 exports high level；5th transmission gate M5 is beaten
It opens, the first clock signal CK exports low level by the 5th transmission gate M5；7th phase inverter M7 exports high level, the 9th phase inverter
M9 exports low level；8th transmission gate M8 is closed, and EN is low level,For high level, output signal OUT is original state
Low level.
T2 stages, i.e. shift LD stage shift the screening signal according to the first clock signal.At this time：
STV_N-1 is high level, and STV_N+1 is low level, and CK is high level, and CKB is high level, at this time：With T1 stages, the first transmission
Door M1 is still opened, and exports STV_N-1, that is, high level, since the output of the 5th transmission gate M5 is still the low level of laststate,
Therefore third nor gate M3 exports low level, and the 4th phase inverter M4 exports high level；5th transmission gate M5 is opened, the first clock letter
Number CK passes through the 5th transmission gate M5 and exports high level；7th phase inverter M7 exports low level, and the 9th phase inverter M9 exports high level；
8th transmission gate M8 is opened, and second clock signal CKB exports high level by the 8th transmission gate M8, and output signal OUT is high electricity
It is flat.
The T3 stages export the stage, are that driving is believed by the screening signal modulation after displacement according to second clock signal.
At this time：STV_N-1 is high level, and STV_N+1 is low level, and CK is high level, and CKB is low level, at this time：With the T1 stages,
One transmission gate M1 is still opened, and exports STV_N-1, that is, high level；Since the output of the 5th transmission gate M5 is still the height of laststate
Level, therefore third nor gate M3 exports low level, the 4th phase inverter M4 exports high level；5th transmission gate M5 is opened, and first
Clock signal CK exports high level by the 5th transmission gate M5；7th phase inverter M7 exports low level, the 9th phase inverter M9 outputs
High level；8th transmission gate M8 is opened, and second clock signal CKB exports low level, output signal OUT by the 8th transmission gate M8
For low level.
The T4 stages export the caching stage, according to enable signal enhancing export the drive signal driving capability or
Block the output of the drive signal.At this time：STV_N-1 is low level, and STV_N+1 is high level, and CK is low level, and CKB is
High level, at this time：With the T1 stages, the first transmission gate M1 is still opened, and STV_N-1, that is, low level is exported, due to the 5th transmission gate
The output of M5 is still the high level of laststate, therefore third nor gate M3 exports low level, the 4th high electricity of phase inverter M4 outputs
It is flat；5th transmission gate M5 is opened, and the first clock signal CK exports low level by the 5th transmission gate M5；7th phase inverter M7 outputs
High level, the 9th phase inverter M9 export low level；8th transmission gate M8 is closed, and output signal OUT is low level.
During display, in the succeeding state in T4 stages, the output signal OUT of this grade of shift register module is always
Low level.
In showing product, touch function and display function are time-sharing works, i.e., are touched within the display scanning work time
Control scanning does not work, and shows that scanning stops within the touch-control scanning work time.Therefore, switching to touch function from display function
When, i.e., in TX scanning work times or fast discharge time, adjusting enable signal so that EN is high level,For low level,
Then output signal output is invalid, which is presented high-impedance state state.
Include the output of p-type field-effect tube and N-type field-effect tube by increase in the shift register module of the present embodiment
Sub-circuit is cached, in conjunction with the switch of enable signal control field-effect tube (M13, M14), can not only export height when normal display
Low level (EN is low level,For high level), and when can export touch-control high-impedance state (EN is high level,It is low
Level) so that output signal generates three kinds of states, in touch-control working condition or pixel repid discharge state and other are special
State can be such that the output of shift register module is disconnected with gate lines and All other routes completely, have low noise, work is more
Stablize, the stronger advantage of driving capability.
Embodiment 2：
The present embodiment provides the shift register modules in a kind of gate driving circuit, including embodiment 1.
In the gate driving circuit, multiple shift register module cascade Connections, as shown in figure 4, per level-one shift LD
The input signal of device module includes the first input signal STV_N-1 and the second input signal STV_N+1, STV_N-1 is from upper
The output signal STV_N, STV_N+1 of shift LD sub-circuit 2 are to be posted from next stage displacement in level-one shift register module
The output signal STV_N of shift LD sub-circuit 2 in buffer module, respectively as two inputs of this grade of shift register module
Signal, in this grade of shift register module the output signal of shift LD sub-circuit 2 be located in sequential the first input signal and
Between second input signal.
The gate driving circuit is as a result of above-mentioned shift register module, in touch-control working condition or pixel
Repid discharge state and other special states can be such that the output of GOA circuits is disconnected with gate lines and All other routes completely, avoid
In above-mentioned particular state because ghost effect has an impact display circuit part, there is low noise, work more to stablize, driving
The stronger advantage of ability promotes yield with this more preferable raising panel performance.
Embodiment 3：
The present embodiment provides a kind of display device, which includes the gate driving circuit in embodiment 2.
The display device can be：Desktop computer, tablet computer, laptop, mobile phone, PDA, GPS, car-mounted display,
Projection Display, video camera, digital camera, electronic watch, calculator, electronic instrument and meter, liquid crystal display panel, Electronic Paper, TV
Any product or component with display function such as machine, display, Digital Frame, navigator, can be applied to public display and void
The multiple fields such as unreal display.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, in the essence for not departing from the present invention
In the case of refreshing and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of shift register module, which is characterized in that input sub-circuit, shift LD electricity including cascading setting successively
Road, output sub-circuit and output caching sub-circuit, wherein：
The input sub-circuit is believed with the first input signal end, the second input signal end, first control signal end and the second control
Number end connection, for according to signal opposite first control signal and second control signal, to respectively with shift LD
Second input signal of the first input signal of the advanced a cycle of circuit shift signal to be output and lag a cycle into
Row screening, and signal transmission will be screened to the shift LD sub-circuit；
The shift LD sub-circuit, connect with the first clock signal terminal and low level voltage end, for being believed according to the first clock
Number, the screening signal is shifted；
The output sub-circuit, connect with second clock signal end and low level voltage end, is used for according to second clock signal, will
The screening signal modulation after displacement is drive signal；
The output caches sub-circuit, is connect with enable signal end, high level voltage end and low level voltage end, makes for basis
It can signal, the driving capability of the enhancing output drive signal or the output for blocking the drive signal.
2. shift register module according to claim 1, which is characterized in that the input sub-circuit includes the first transmission
Door and the second transmission gate, wherein：
First transmission gate, input terminal connect the first input signal end, and the first control terminal connects first control signal end, the
Two control terminals connect second control signal end, and output end connects the input terminal of the shift LD sub-circuit；
Second transmission gate, input terminal connect the second input signal end, and the first control terminal connects second control signal end, the
Two control terminals connect first control signal end, and output end connects the input terminal of shift LD sub-circuit.
3. shift register module according to claim 1, which is characterized in that the shift LD sub-circuit includes third
Nor gate, the 4th phase inverter, the 5th transmission gate and the 6th transistor, wherein：
The third nor gate, first input end connect it is described input sub-circuit output end, the second input terminal connection described in
The output end of 5th transmission gate, output end connect the input terminal of the 4th phase inverter；
4th phase inverter, output end connect the first control terminal of the 5th transmission gate；
5th transmission gate, input terminal connect the first clock signal terminal, and the second control terminal connects the output of third nor gate
End, output end are also connected with the input terminal of the output sub-circuit；
6th transistor, control terminal connect the output end of the third nor gate, and the first pole connects low level end, and second
Pole connects the output end of the 5th transmission gate.
4. shift register module according to claim 1, which is characterized in that the output sub-circuit includes the 7th reverse phase
Device, the 8th transmission gate, the 9th phase inverter and the tenth transistor, wherein：
7th phase inverter, input terminal connect the output end of the shift LD sub-circuit, output end connection the described 8th
The input terminal of second control terminal of transmission gate and the 9th phase inverter；
8th transmission gate, input terminal connect second clock signal end, and the first control terminal connects the 9th phase inverter
Output end, output end connect the input terminal of the second pole and the output caching sub-circuit of the tenth transistor；
Tenth transistor, control terminal connect the output end of the 9th phase inverter, and the first pole connects low level voltage end.
5. shift register module according to claim 1, which is characterized in that the output caching sub-circuit includes the tenth
One phase inverter, the 12nd field-effect tube, the 13rd field-effect tube, the 14th field-effect tube and the 15th field-effect tube, wherein：
11st phase inverter, input terminal connect the output end of the output sub-circuit, output end connection the described 12nd
The control terminal of the control terminal of field-effect tube and the 15th field-effect tube；
12nd field-effect tube, the first pole connect high level voltage end, and the second pole connects the 13rd field-effect tube
The first pole；
13rd field-effect tube, control terminal connect the first enable signal end, and the second pole connects the 14th field-effect
First pole of pipe；
14th field-effect tube, control terminal connect the second enable signal end, and the second pole connects the 15th field-effect
First pole of pipe；
15th field-effect tube, the second pole connect low level voltage signal end.
6. a kind of driving method of claim 1-5 any one of them shift register modules, which is characterized in that including input
Stage, shift LD stage, output stage and output caching stage, wherein：
Input phase, according to signal opposite first control signal and second control signal, to sub with the shift LD respectively
Second input signal of the first input signal of the advanced a cycle of circuit shift signal to be output and lag a cycle into
Row screening, and signal transmission will be screened to the shift LD sub-circuit；
The shift LD stage shifts the screening signal according to the first clock signal；
The screening signal modulation after displacement is drive signal according to second clock signal by the output stage；
The caching stage is exported, the driving capability of the drive signal is exported according to enable signal enhancing or the driving is blocked to believe
Number output.
7. driving method according to claim 6, which is characterized in that the pulse width of the second clock signal is described
The pulse width of the half of the pulse width of first clock signal, first input signal and second input signal is distinguished
It it is twice of the pulse width of first clock signal, the pulse width of the drive signal is first clock signal
The half of pulse width.
8. driving method according to claim 6, which is characterized in that when display function：The caching stage is exported, first is enabled
On the contrary, enable signal enhancing exports the driving capability of the drive signal, which posts for signal and the level of the second enable signal
Buffer module exports high level or low level；
When touch function：Enable signal blocks the output of the drive signal, which is presented high-impedance state state.
9. a kind of gate driving circuit, which is characterized in that including claim 1-5 any one of them shift register modules,
Multiple shift register module cascade Connections, wherein：
Output signal from shift LD sub-circuit described in shift register module described in upper level and come from next stage institute
State the output signal of shift LD sub-circuit described in shift register module, respectively this grade of shift register module
First input signal and second input signal.
10. a kind of display device, which is characterized in that including the gate driving circuit described in claim 9.
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| CN112289252A (en) * | 2019-07-12 | 2021-01-29 | 成都辰显光电有限公司 | Drive circuit, display panel and display device |
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