CN110930951A - Gate drive circuit, display panel and display device - Google Patents
Gate drive circuit, display panel and display device Download PDFInfo
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- CN110930951A CN110930951A CN201911345890.9A CN201911345890A CN110930951A CN 110930951 A CN110930951 A CN 110930951A CN 201911345890 A CN201911345890 A CN 201911345890A CN 110930951 A CN110930951 A CN 110930951A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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Abstract
The invention relates to a gate driving circuit, a display panel and a display device. The gate driving circuit includes: the device comprises an output holding module, an output module and an output buffer module; the output end of the output holding module is connected with the input end of the output module, the output end of the output module is connected with the input end of the output buffer module, and the output end of the output buffer module is the output end of the grid drive circuit; the output holding module is used for controlling a third scanning signal output by the output module to be a first level in a first period and a second level outside the first period according to the first scanning signal and the second scanning signal; the first level is different from the second level; the first scanning signal, the second scanning signal and the third scanning signal are different; and the output buffer module is used for outputting the third scanning signal after shaping and buffering. According to the embodiment of the invention, the output stability of the gate driving circuit can be better and the power consumption is smaller.
Description
Technical Field
The invention relates to the technical field of OLED display equipment, in particular to a gate driving circuit, a display panel and a display device.
Background
The grid driving circuit of the display panel keeps stable and effective work and is always a key point for improving the performance of the grid driving circuit. However, if the gate driver circuit is formed of a single transistor, it requires a large external capacitor and a large leakage current, and thus, there are problems of poor stability and large power consumption.
Disclosure of Invention
The invention provides a gate driving circuit, a display panel and a display device, which are used for solving the defects in the related art.
According to a first aspect of embodiments of the present invention, there is provided a gate driving circuit, including: the device comprises an output holding module, an output module and an output buffer module; the output end of the output holding module is connected with the input end of the output module, the output end of the output module is connected with the input end of the output buffer module, and the output end of the output buffer module is the output end of the grid drive circuit; the output holding module is used for controlling a third scanning signal output by the output module to be at a first level in a first period and at a second level outside the first period according to a first scanning signal and a second scanning signal; the first level is different from the second level; the first scanning signal, the second scanning signal and the third scanning signal are different; the output buffer module is used for outputting the third scanning signal after shaping and buffering;
the output holding module comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a NAND gate; the first transistor, the second transistor and the third transistor are first type transistors, and the fourth transistor is a second type transistor; the source of the first transistor is used for inputting the first scanning signal, the gate of the first transistor is used for inputting a second scanning signal, the drain of the first transistor is connected with the first input end of the nand gate, and the second input end of the nand gate is used for inputting the first scanning signal; the grid of the first transistor is further connected with the grid of the second transistor, the source of the second transistor is connected with a first power supply, the drain of the second transistor is connected with the source of the third transistor, the grid of the third transistor is connected with the grid of the fourth transistor in parallel and then connected with the output end of the NAND gate, the node where the drain of the third transistor is connected with the drain of the fourth transistor in parallel is connected with the first input end of the NAND gate, the source of the fourth transistor is connected with a second power supply, and the node is the output end of the output holding module.
In one embodiment, the output module comprises a fifth transistor, a transmission gate and a first inverter; the fifth transistor is the first type transistor; the source electrode of the fifth transistor is connected with the first power supply, the grid electrode of the fifth transistor is used for inputting a first enabling signal, the drain electrode of the fifth transistor is connected with the output end of the output holding module, the drain electrode of the fifth transistor is further connected with the first control end of the transmission gate, the drain electrode of the fifth transistor is further connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the second control end of the transmission gate, the input end of the transmission gate is used for inputting a clock signal, and the output end of the transmission gate is the output end of the output module.
In one embodiment, the output buffer module comprises a second inverter and a third inverter;
the input end of the second phase inverter is connected with the output end of the output module, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is the output end of the output buffer module.
Because the output buffer module comprises the second inverter and the third inverter which are connected in series, the signal output by the output module can be shaped and buffered, and the stability of circuit output can be further improved.
In one embodiment, the output buffer module further comprises a sixth transistor; the sixth transistor is a first type transistor; the source of the sixth transistor is connected with the first power supply, the gate of the sixth transistor is connected with the output end of the third inverter, and the drain of the sixth transistor is connected with the input end of the third inverter.
Because the grid of the sixth transistor is connected with the output end of the third phase inverter, and the drain of the sixth transistor is connected with the input end of the third phase inverter, the sixth transistor can perform feedback regulation on the output of the circuit, so that the output is more stable and effective, the performance of the display panel can be further improved, and the yield is improved.
In one embodiment, the output buffer module further comprises a seventh transistor; the seventh transistor is a second type transistor; and the drain of the seventh transistor is connected with the input end of the third inverter, the source of the seventh transistor is connected with the second power supply, and the gate of the seventh transistor is connected with the output end of the third inverter.
Because the drain of the seventh transistor is connected with the input end of the third inverter and the grid of the seventh transistor is connected with the output end of the third inverter, the seventh transistor can perform feedback regulation on the output of the circuit, so that the output is more stable and effective, the performance of the display panel is further improved, and the yield is improved.
In one embodiment, the gate driving circuit further includes a reset unit; the reset unit is used for resetting the third scanning signal output by the output module; the control end of the reset unit is connected with the output end of the first phase inverter, the enable end of the reset unit is used for inputting a second enable signal, and the output end of the reset unit is connected with the output end of the output module.
The reset unit can reset the third scanning signal output by the output module, so that special functions of full-screen brightness or full-screen darkness and the like of the display panel can be realized.
In one embodiment, the reset unit includes an eighth transistor, a ninth transistor, and a tenth transistor; the eighth transistor and the ninth transistor are the first type transistor, and the tenth transistor is the second type transistor; the source of the eighth transistor is connected with the first power supply, the gate of the eighth transistor is the control end of the reset unit, the drain of the eighth transistor is connected with the source of the ninth transistor, the gate of the ninth transistor is connected with the gate of the tenth transistor in parallel and then connected with the enable end of the reset unit, the drain of the ninth transistor is connected with the drain of the tenth transistor in parallel and then connected with the output end of the reset unit, and the source of the tenth transistor is connected with the second power supply.
In one embodiment, the first type transistor is a P-type transistor and the second type transistor is an N-type transistor; and/or the power supply voltage of the first power supply is greater than the power supply voltage of the second power supply.
According to a second aspect of the embodiments of the present invention, a display panel is provided, which includes the gate driving circuit.
According to a third aspect of embodiments of the present invention, there is provided a display device including the display panel described above.
According to the above embodiments, since the output holding module includes the first transistor, the second transistor, the third transistor, the fourth transistor and the nand gate, the first transistor, the second transistor and the third transistor are the first type transistor, and the fourth transistor is the second type transistor, and the complementary functions of the first type transistor and the second type transistor can make the output stability of the circuit better and the power consumption smaller. And because the number of the electronic components used by the output holding module is small, the number of the electronic components used by the grid drive circuit is reduced, the power consumption can be reduced, the occupied area of the grid drive circuit can be reduced, and the narrow frame of the display panel is favorably realized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a block diagram illustrating a gate driving circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating an embodiment of the present invention;
FIG. 4 is a block diagram illustrating another gate driver circuit according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
An embodiment of the present invention provides a gate driving circuit, as shown in fig. 1 to 2, the gate driving circuit includes: an output holding module 11, an output module 12 and an output buffer module 13.
As shown in fig. 1, the output end of the output holding module 11 is connected to the input end of the output module 12, the output end of the output module 12 is connected to the input end of the output buffer module 13, and the output end of the output buffer module 13 is the output end of the gate driving circuit. The output hold module 11 is configured to control the third scan signal OUT output by the output module 12 to be at the first level in the first period and to be at the second level outside the first period according to the first scan signal STV _ N-1 and the second scan signal STV _ N + 1. Wherein the first level is different from the second level. The first scan signal STV _ N-1, the second scan signal STV _ N +1, and the third scan signal OUT are different. The output buffer module 13 is configured to perform shaping buffering on the third scan signal OUT and then output the third scan signal OUT.
For example, the first scan signal STV _ N-1 may be a scan signal of the N-1 th row of pixels, the second scan signal STV _ N +1 may be a scan signal of the N +1 th row of pixels, and the third scan signal OUT may be a scan signal of the N-th row of pixels. N is a positive integer greater than 1. The first level may be less than the second level, e.g., the first level may be a low level and the second level may be a high level. That is, as shown in fig. 3, the third scan signal OUT is at a low level in the first period T2, so that the switching tubes in the pixel circuits of the pixels in the nth row are turned on, and the third scan signal OUT is at a high level in the periods T1, T3, and T4 other than the first period T2, so that the switching tubes in the pixel circuits of the pixels in the nth row are turned off. The switching tubes in the pixel circuits of the pixels in the nth row are PMOS transistors.
As shown in fig. 2, the output holding module 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a nand gate F. The first transistor M1, the second transistor M2, and the third transistor M3 are transistors of a first type, and the fourth transistor M4 is a transistor of a second type. In this embodiment, the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor. The P-type transistor may be a PMOS transistor and the N-type transistor may be an NMOS transistor.
The source of the first transistor M1 is used for inputting the first scan signal STV _ N-1, the gate of the first transistor M1 is used for inputting the second scan signal STV _ N +1, the drain of the first transistor M1 is connected to the first input of the nand gate F, and the second input of the nand gate F is used for inputting the first scan signal STV _ N-1; the gate of the first transistor M1 is further connected to the gate of the second transistor M2, the source of the second transistor M2 is connected to the first power VGH, the drain of the second transistor M2 is connected to the source of the third transistor M3, the gate of the third transistor M3 is connected to the gate of the fourth transistor M4 in parallel and then connected to the output of the nand gate F, the drain of the third transistor M3 is connected to the node G of the drain of the fourth transistor M4 in parallel and the first input of the nand gate F, the source of the fourth transistor M4 is connected to the second power VGL, and the node is the output of the output holding module 11.
In this embodiment, the power supply voltage of the first power supply VGH is greater than the power supply voltage of the second power supply VGL. For example, the power supply voltage supplied from the first power supply VGH is a high voltage, and the power supply voltage supplied from the second power supply VGL is a low voltage.
In this embodiment, when the signals input to the first input terminal and the second input terminal of the nand gate F are both high levels, the output terminal of the nand gate F outputs low levels, and when at least one of the signals input to the first input terminal and the second input terminal of the nand gate F is low levels, the output terminal of the nand gate F outputs high levels.
As shown in fig. 2, the output module 12 includes a fifth transistor M5, a transmission gate T and a first inverter INV1, wherein the fifth transistor M5 is a first type transistor, i.e. a PMOS transistor. The source of the fifth transistor M5 is connected to the first power source VGH, the gate of the fifth transistor M5 is used for inputting the first enable signal EN1, the drain of the fifth transistor M5 is connected to the output terminal of the output holding module 11, that is, the drain of the fifth transistor M5 is connected to the node G, or the drain of the fifth transistor M5 is connected to the drain of the third transistor M3. The drain of the fifth transistor M5 is further connected to the first control terminal of the transmission gate T, the drain of the fifth transistor M5 is further connected to the input terminal of the first inverter INV1, the output terminal of the first inverter INV1 is connected to the second control terminal of the transmission gate T, the input terminal of the transmission gate T is used for inputting the clock signal CK, and the output terminal of the transmission gate T is the output terminal of the output module 12.
In this embodiment, when the first control terminal of the transmission gate T is at a low level and the second control terminal of the transmission gate T is at a high level, the transmission gate T is turned on, and when the first control terminal of the transmission gate T is at a high level and the second control terminal of the transmission gate T is at a low level, the transmission gate T is turned off. The transmission gate T may be a CMOS transmission gate, and the CMOS transmission gate may be formed by connecting a PMOS transistor and an NMOS transistor in parallel.
In the present embodiment, when the signal input to the input terminal of the first inverter INV1 is at a high level, the signal output to the output terminal of the first inverter INV1 is at a low level. When the signal input to the input terminal of the first inverter INV1 is at a low level, the signal output from the output terminal of the first inverter INV1 is at a high level. The second inverter INV2 and the third inverter INV3 have the same operation principle as the first inverter INV 1.
As shown in fig. 2, the output buffer module 13 includes a second inverter INV2, a third inverter INV3, a sixth transistor M6 and a seventh transistor M7. The sixth transistor M6 is a first type transistor, i.e., a PMOS transistor. The seventh transistor M7 is a second type transistor, i.e., an NMOS transistor. The input end of the second inverter INV2 is connected to the output end of the output module 12, that is, the input end of the second inverter INV2 is connected to the output end of the transmission gate T. An output end of the second inverter INV2 is connected to an input end of the third inverter INV3, and an output end of the third inverter INV3 is an output end of the output buffer module 13. A source of the sixth transistor M6 is connected to the first power source VGH, a gate of the sixth transistor M6 is connected to the output terminal of the third inverter INV3, and a drain of the sixth transistor M6 is connected to the input terminal of the third inverter INV 3. A drain of the seventh transistor M7 is connected to an input terminal of the third inverter INV3, a source of the seventh transistor M7 is connected to the second power source VGL, and a gate of the seventh transistor M7 is connected to an output terminal of the third inverter INV 3.
In this embodiment, when the gate driving circuit normally operates, the first enable signal EN1 is at a high level.
As shown in fig. 3, in the second period T1, the first scan signal STV _ N-1 is at a low level, the second scan signal STV _ N +1 is at a high level, the clock signal CK is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned off, the third transistor M3 is turned off, the nand gate F outputs a high level, the fourth transistor M4 is turned on, the first inverter INV1 outputs a high level, the transmission gate T is turned on, the second inverter INV2 outputs a low level, the third inverter INV3 outputs a high level, and the third scan signal OUT is at a high level.
As shown in fig. 3, in the first period T2, the first scan signal STV _ N-1 is at a low level, the second scan signal STV _ N +1 is at a high level, the clock signal CK is at a low level, the second transistor M2 is turned off, the fourth transistor M4 is turned on, the nand gate F outputs a high level, the first inverter INV1 outputs a high level, the transmission gate T is turned on, the second inverter INV2 outputs a high level, the third inverter INV3 outputs a low level, and the third scan signal OUT is at a low level.
As shown in fig. 3, in the third period T3, the first scan signal STV _ N-1 is at a high level, the second scan signal STV _ N +1 is at a low level, the clock signal CK is at a high level, the first transistor M1 is turned on, the second transistor M2 is turned on, the third transistor M3 is turned on, the nand gate F outputs a low level, the first inverter INV1 inputs a high level and outputs a low level, the transmission gate T is turned off, the second inverter INV2 inputs a high level and outputs a low level, the third inverter INV3 inputs a low level and outputs a high level, and the third scan signal OUT is at a high level.
As shown in fig. 3, in the fourth period T4, the first scan signal STV _ N-1 is at a high level, the second scan signal STV _ N +1 is at a low level, the clock signal CK is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, the third transistor M3 is turned on, the nand gate F outputs a low level, the first inverter INV1 inputs a high level and outputs a low level, the transmission gate T is turned off, the second inverter INV2 inputs a high level and outputs a low level, the third inverter INV3 inputs a low level and outputs a high level, and the third scan signal OUT is at a high level.
In this embodiment, the output holding module includes a first transistor, a second transistor, a third transistor, a fourth transistor and a nand gate, the first transistor, the second transistor and the third transistor are first type transistors, the fourth transistor is a second type transistor, and the characteristics of the first type transistor and the second type transistor complement each other, so that the output stability of the circuit is better and the power consumption is smaller. And because the number of the electronic components used by the output holding module is small, the number of the electronic components used by the grid drive circuit is reduced, the power consumption can be reduced, the occupied area of the grid drive circuit can be reduced, the narrow frame of the display panel can be realized, and the market competitiveness can be facilitated.
The embodiment of the invention provides the gate driving circuit with the CMOS structure, completely adopts digital signals, and can ensure that the output stability of the gate driving circuit is better and the power consumption is lower by utilizing the characteristic complementary action of the N-type transistor and the P-type transistor.
In this embodiment, since the output buffer module includes the second inverter and the third inverter, and the second inverter is connected in series with the third inverter, the signal output by the output module can be shaped and buffered, and the stability of the output of the gate driving circuit can be further improved.
In this embodiment, since the third inverter and the sixth transistor form a reverse loop, and the third inverter and the seventh transistor also form a reverse loop, a feedback effect can be achieved, it can be ensured that the third scan signal output by the gate driving circuit is more stable and effective, the performance of the display panel can be further improved, and the yield can be improved. The reverse loop may also be referred to as a feedback loop.
The embodiment of the invention also provides a gate driving circuit. As shown in fig. 4 to 5, in the present embodiment, on the basis of the above embodiments, the gate driving circuit further includes a reset unit 14. The reset unit 14 is configured to reset the third scan signal OUT output by the output module 12. A control terminal of the reset unit 14 is connected to an output terminal of the first inverter INV1, an enable terminal of the reset unit 14 is used for inputting the second enable signal EN2, and an output terminal of the reset unit 14 is connected to an output terminal of the output module 12.
In the present embodiment, as shown in fig. 5, the reset unit 14 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; the eighth transistor M8 and the ninth transistor M9 are of a first type, i.e., PMOS transistors, and the tenth transistor M10 is of a second type, i.e., NMOS transistors.
A source of the eighth transistor M8 is connected to the first power source VGH, a gate of the eighth transistor M8 is a control terminal of the reset unit 14, that is, a gate of the eighth transistor M8 is connected to an output terminal of the first inverter INV1, a drain of the eighth transistor M8 is connected to a source of the ninth transistor M9, a gate of the ninth transistor M9 is connected to a gate of the tenth transistor M10 in parallel and then connected to an enable terminal of the reset unit 14, a drain of the ninth transistor M9 is connected to a drain of the tenth transistor M10 in parallel and then connected to an output terminal of the reset unit 14, that is, a drain of the ninth transistor M9 is connected to a drain of the tenth transistor M10 in parallel and then connected to an output terminal of the transmission gate T, and a source of the tenth transistor M10 is connected to the second power source VGL.
In this embodiment, when the gate driving circuit normally operates, the first enable signal EN1 is at a high level, and the second enable signal EN2 is at a low level. In the second period T1, the eighth transistor M8 is turned off, the ninth transistor M9 is turned on, or in a critical state, and the tenth transistor M10 is turned off. In the first period T2, the eighth transistor M8 is turned off, the ninth transistor M9 is turned on, or in a critical state, and the tenth transistor M10 is turned off. In the third period T3, the eighth transistor M8 is turned on, the ninth transistor M9 is turned on, and the tenth transistor M10 is turned off. In the fourth period T4, the eighth transistor M8 is turned on, the ninth transistor M9 is turned on, and the tenth transistor M10 is turned off.
In this embodiment, when the first enable signal EN1 is at a low level and the second enable signal EN2 is at a low level, the transmission gate T is turned off, the gate driving circuit is forced to reset, and the output third scan signal OUT is at a high level. When the first enable signal EN1 is at a low level and the second enable signal EN2 is at a high level, the transmission gate T is turned off, the gate driving circuit is forcibly reset, and the output third scan signal OUT is at a low level. Thus, special functions of full-screen brightness or full-screen darkness of the display panel can be realized.
The embodiment of the invention also provides a display panel. The display panel comprises the gate driving circuit described in any of the above embodiments.
In this embodiment, the display panel may be an OLED (Organic Light-Emitting Diode) display panel or an LED (Light-Emitting Diode) display panel, but is not limited thereto.
In this embodiment, the display panel may be a flexible screen display panel, a bendable screen display panel, a foldable screen display panel, a hard screen display panel, a perforated screen display panel, or a full screen display panel.
In this embodiment, the output holding module includes a first transistor, a second transistor, a third transistor, a fourth transistor and a nand gate, the first transistor, the second transistor and the third transistor are of a first type, the fourth transistor is of a second type, and the characteristics of the first type transistor and the second type transistor complement each other, so that the output stability of the circuit is better and the power consumption is smaller. And because the number of the electronic components used by the output holding module is small, the number of the electronic components used by the grid drive circuit is reduced, the power consumption can be reduced, the occupied area of the grid drive circuit can be reduced, the narrow frame of the display panel can be realized, and the market competitiveness can be improved.
The embodiment of the invention also provides a display device. The display device comprises a display module and the display panel of any one of the embodiments. The display module may include a polarizer, a touch panel, a glass cover plate, and the like, but is not limited thereto.
In this embodiment, the output holding module includes a first transistor, a second transistor, a third transistor, a fourth transistor and a nand gate, the first transistor, the second transistor and the third transistor are of a first type, the fourth transistor is of a second type, and the characteristics of the first type transistor and the second type transistor complement each other, so that the output stability of the circuit is better and the power consumption is smaller. And because the number of the electronic components used by the output holding module is small, the number of the electronic components used by the grid drive circuit is reduced, the power consumption can be reduced, the occupied area of the grid drive circuit can be reduced, the narrow frame of the display panel can be realized, and the market competitiveness can be improved.
The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
In the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" means two or more unless expressly limited otherwise.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A gate drive circuit, comprising: the device comprises an output holding module, an output module and an output buffer module; the output end of the output holding module is connected with the input end of the output module, the output end of the output module is connected with the input end of the output buffer module, and the output end of the output buffer module is the output end of the grid drive circuit; the output holding module is used for controlling a third scanning signal output by the output module to be at a first level in a first period and at a second level outside the first period according to a first scanning signal and a second scanning signal; the first level is different from the second level; the first scanning signal, the second scanning signal and the third scanning signal are different; the output buffer module is used for outputting the third scanning signal after shaping and buffering;
the output holding module comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a NAND gate; the first transistor, the second transistor and the third transistor are first type transistors, and the fourth transistor is a second type transistor; the source of the first transistor is used for inputting the first scanning signal, the gate of the first transistor is used for inputting a second scanning signal, the drain of the first transistor is connected with the first input end of the nand gate, and the second input end of the nand gate is used for inputting the first scanning signal; the grid of the first transistor is further connected with the grid of the second transistor, the source of the second transistor is connected with a first power supply, the drain of the second transistor is connected with the source of the third transistor, the grid of the third transistor is connected with the grid of the fourth transistor in parallel and then connected with the output end of the NAND gate, the node where the drain of the third transistor is connected with the drain of the fourth transistor in parallel is connected with the first input end of the NAND gate, the source of the fourth transistor is connected with a second power supply, and the node is the output end of the output holding module.
2. The gate driving circuit of claim 1, wherein the output module comprises a fifth transistor, a transmission gate and a first inverter; the fifth transistor is the first type transistor;
the source electrode of the fifth transistor is connected with the first power supply, the grid electrode of the fifth transistor is used for inputting a first enabling signal, the drain electrode of the fifth transistor is connected with the output end of the output holding module, the drain electrode of the fifth transistor is further connected with the first control end of the transmission gate, the drain electrode of the fifth transistor is further connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the second control end of the transmission gate, the input end of the transmission gate is used for inputting a clock signal, and the output end of the transmission gate is the output end of the output module.
3. The gate driving circuit of claim 1, wherein the output buffer module comprises a second inverter and a third inverter;
the input end of the second phase inverter is connected with the output end of the output module, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is the output end of the output buffer module.
4. A gate drive circuit as claimed in claim 3, wherein the output buffer module further comprises a sixth transistor; the sixth transistor is a first type transistor;
the source of the sixth transistor is connected with the first power supply, the gate of the sixth transistor is connected with the output end of the third inverter, and the drain of the sixth transistor is connected with the input end of the third inverter.
5. A gate drive circuit as claimed in claim 3, wherein the output buffer module further comprises a seventh transistor; the seventh transistor is a second type transistor;
and the drain of the seventh transistor is connected with the input end of the third inverter, the source of the seventh transistor is connected with the second power supply, and the gate of the seventh transistor is connected with the output end of the third inverter.
6. The gate driving circuit according to claim 2, further comprising a reset unit; the reset unit is used for resetting the third scanning signal output by the output module;
the control end of the reset unit is connected with the output end of the first phase inverter, the enable end of the reset unit is used for inputting a second enable signal, and the output end of the reset unit is connected with the output end of the output module.
7. The gate driving circuit according to claim 6, wherein the reset unit comprises an eighth transistor, a ninth transistor and a tenth transistor; the eighth transistor and the ninth transistor are the first type transistor, and the tenth transistor is the second type transistor;
the source of the eighth transistor is connected with the first power supply, the gate of the eighth transistor is the control end of the reset unit, the drain of the eighth transistor is connected with the source of the ninth transistor, the gate of the ninth transistor is connected with the gate of the tenth transistor in parallel and then connected with the enable end of the reset unit, the drain of the ninth transistor is connected with the drain of the tenth transistor in parallel and then connected with the output end of the reset unit, and the source of the tenth transistor is connected with the second power supply.
8. The gate driving circuit according to any one of claims 1 to 7, wherein the first type transistor is a P-type transistor and the second type transistor is an N-type transistor; and/or the power supply voltage of the first power supply is greater than the power supply voltage of the second power supply.
9. A display panel comprising the gate driver circuit according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
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| CN201911345890.9A CN110930951A (en) | 2019-12-24 | 2019-12-24 | Gate drive circuit, display panel and display device |
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| CN201911345890.9A CN110930951A (en) | 2019-12-24 | 2019-12-24 | Gate drive circuit, display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870764A (en) * | 2020-06-11 | 2021-12-31 | 成都辰显光电有限公司 | Pixel circuit and display panel |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070080047A (en) * | 2006-02-06 | 2007-08-09 | 삼성전자주식회사 | A shift resister for display device |
| JP2012168227A (en) * | 2011-02-10 | 2012-09-06 | Seiko Epson Corp | Driving circuit for electro-optical device, electro-optical device and electronic device |
| CN105609071A (en) * | 2016-01-05 | 2016-05-25 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid drive circuit and display apparatus |
| CN106205518A (en) * | 2016-06-27 | 2016-12-07 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| CN107491208A (en) * | 2017-08-11 | 2017-12-19 | 京东方科技集团股份有限公司 | Touch-control driver element, touch drive circuit and display device |
| CN107516492A (en) * | 2017-09-21 | 2017-12-26 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display device |
| CN109215611A (en) * | 2018-11-16 | 2019-01-15 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, GOA unit circuit and display device |
-
2019
- 2019-12-24 CN CN201911345890.9A patent/CN110930951A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070080047A (en) * | 2006-02-06 | 2007-08-09 | 삼성전자주식회사 | A shift resister for display device |
| JP2012168227A (en) * | 2011-02-10 | 2012-09-06 | Seiko Epson Corp | Driving circuit for electro-optical device, electro-optical device and electronic device |
| CN105609071A (en) * | 2016-01-05 | 2016-05-25 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid drive circuit and display apparatus |
| CN106205518A (en) * | 2016-06-27 | 2016-12-07 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| CN107491208A (en) * | 2017-08-11 | 2017-12-19 | 京东方科技集团股份有限公司 | Touch-control driver element, touch drive circuit and display device |
| CN107516492A (en) * | 2017-09-21 | 2017-12-26 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display device |
| CN109215611A (en) * | 2018-11-16 | 2019-01-15 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method, GOA unit circuit and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870764A (en) * | 2020-06-11 | 2021-12-31 | 成都辰显光电有限公司 | Pixel circuit and display panel |
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