KR20070080047A - A shift resister for display device - Google Patents

Abstract

A shift resister for a display device is provided to facilitate generation of a shift register output signal by elongating a sampling period by delaying an adjustment signal by a predetermined time. A shift resister includes plural stages which are connected to each other. A signal selector(331) determines input directions of a data signal and a gate signal. The signal selector includes first and second transmission gates which are parallel-coupled with each other. A switching controller(332) controls a switch and includes a NOR gate having first and second input terminals and an NMOS transistor. The switch(333) includes PMOS transistors. A buffer unit(334) receives an output signal from the switch and outputs a shift register output signal. The buffer unit includes at least one inverter. A reset unit(335) includes NMOS transistors. A reset signal is applied to a control terminal of the NMOS transistor. An input terminal of a delay unit(336) is connected to an output terminal of the switch and outputs an adjustment signal.

Description

Shift register for display device {A SHIFT RESISTER FOR DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating an example of a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating an example of a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a circuit diagram showing a shift register according to an embodiment of the present invention.

6 is a signal waveform diagram of a shift register according to one embodiment of the present invention;

7 is a waveform diagram of a clock signal and an adjustment signal of a shift register according to an embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 110, 210: substrate

100: lower panel 191: pixel electrode

200: upper display panel 230: color filter

270: common electrode 300: liquid crystal panel assembly

331: Signal selector 332: Switching controller

333: switching unit 334: buffer unit

335: reset unit 336: delay unit

400: gate driver 500: data driver

600: signal controller 800: gray voltage generator

The present invention relates to a shift register for a display device.

The liquid crystal display is one of the most widely used flat panel display devices, and includes two display panels on which an electric field generating electrode such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. The liquid crystal display generates an electric field in the liquid crystal layer by applying a voltage to the field generating electrode, thereby determining an orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

SUMMARY OF THE INVENTION The present invention is to provide a shift register for a display device which can improve the operation speed and accuracy of the driver while making the gate driver and the data driver more economical.

The shift register for a display device of the present invention for achieving the above technical problem is a shift register including a plurality of stages connected in series, each of the plurality of stages, the first input signal or the second input signal in accordance with a control signal A signal selector configured to select and output one of the signals; a NOR GATE using the output signal of the signal selector as a first input signal, and a first switching transistor configured to output a first clock signal according to an output signal of the NOR gate. And a second switching transistor outputting a reference voltage according to the output signal of the NOR gate, a second switching transistor alternately operating with the first switching transistor, and a delay unit configured to receive and delay the output of the first switching transistor, and to output the first switching transistor. An output signal of the first switching transistor and an output of the second switching transistor A call is alternately enters the second input signal of the NOR gate.

The delay unit may include at least one inverter connected in series.

The output terminal may further include a third switching transistor connected to the output terminals of the first and second switching transistors and outputting a reference voltage according to a reset signal.

The third switching transistor may include an NMOS.

The first switching transistor may include a PMOS.

The second switching transistor may include an NMOS.

The signal selector may include first and second transmission gates connected in parallel.

The apparatus may further include a buffer unit configured to receive an output signal of the first switching transistor and output a shift register output signal.

At least one bias voltage of the NOR gate may receive a second clock signal having a phase opposite to that of the first clock signal.

The output signal of the delay unit may enter a first input signal of a neighboring stage.

The output signal of the delay unit may enter a second input signal of a neighboring stage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a pair of gate drivers 400, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the data driver 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _{n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to form a gate formed of a combination of a gate on voltage Von and a gate off voltage Voff. The signal is applied to the gate lines G ₁ -G _n . The gate driver 400 includes a plurality of stages arranged substantially in a row as a shift register.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The gate driver 400 and the data driver 500 are formed and integrated on the liquid crystal panel assembly 300 in the same process together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. It is. Therefore, the cost of forming the gate driver 400 and the data driver 500 can be reduced.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

The gray voltage generator 800 generates two sets of gray voltages (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

Each of the signal controller 600 and the gray voltage generator 800 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board (not shown). Alternatively, the driving devices 600 and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In addition, the driving devices 600 and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _2n according to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _2n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), so that all the gate lines G ₁ -G _2n are repeated. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, a gate driver according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a block diagram illustrating a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the gate driver 400 includes a wiring part LS and a circuit part CS. The circuit portion CS is composed of a plurality of stages ST1-k formed in succession. The wiring part LS includes a plurality of wirings and is connected to each stage ST1-k to transmit a signal required for driving the stage.

According to the start signal applied from the wiring unit LS, the first stage ST1 generates a carry signal and a gate signal Gout1. The carry signal is transferred to the second stage ST2, and the second stage ST2 generates the carry signal and the gate signal Gout2. Through this process, all stages ST1-k sequentially generate and output gate signals Gout1-k.

A data driver of the liquid crystal display according to the exemplary embodiment of the present invention will now be described in more detail with reference to FIG. 4.

4 is a block diagram illustrating a data driver of a liquid crystal display according to an exemplary embodiment of the present invention.

The data driver 500 includes at least one data driver IC 540 shown in FIG. 4, and the data driver IC 540 includes a shift register 541, a latch 543, and a digital-to-analog converter ( 545, and a buffer 547.

When the horizontal register start signal STH is applied, the shift register 541 sequentially shifts the input image data DAT according to the data clock signal HCLK, and transfers the image data DAT to the latch 543. When the data driver 500 includes a plurality of data driver ICs 540, the shift register 541 shifts all of the image data DAT in charge of the shift register 541, and then shifts the shift clock signal SC to a neighbor. To the shift register of the data driver IC.

Latch 543 includes first and second latches (not shown). The first latch receives and stores the image data DAT sequentially from the shift register 541. The second latch simultaneously receives and stores the image data DAT from the first latch according to the load signal LOAD. Export to analog converter 545.

The digital-to-analog converter 545 converts the digital image data DAT from the latch 543 into an analog data voltage and outputs it to the buffer 547. The data voltage has a positive value or a negative value with respect to the common voltage Vcom according to the polarity signal POL.

Buffer 547 outputs the data voltage from digital-to-analog converter 545 through output terminals Y ₁ -Y _r . The polarities of the data voltages output through the neighboring output terminals Y ₁ -Y _r are different from each other. The output terminals Y ₁ -Y _r are connected to the corresponding data lines D ₁ -D _m .

Next, an example of a shift register included in the gate driver 400 and the data driver 500 according to the present invention will be described in detail with reference to FIGS. 5 and 6.

FIG. 5 is a circuit diagram showing a shift register according to an embodiment of the present invention, and FIGS. 6 and 7 are signal waveform diagrams of the shift register shown in FIG.

Referring to FIG. 5, a shift register according to an embodiment of the present invention includes a plurality of stages ST1, ST2..., And each stage ST1, ST2... Is continuously arranged and connected to each other.

Each stage, for example, the first stage ST1, includes a signal selector 331, a switching controller 332, a switching unit 333, a buffer unit 334, a reset unit 335, and a delay unit 336. Include.

The signal selector 331 determines a signal input direction of a data signal or a gate signal. The signal selector 331 includes first and second transmission gates 331a and 331b connected in parallel to each other. First and second input signals IN1 and IN2 are input to input terminals of the first and second transmission gates 331a and 331b, respectively, and output terminals are connected to each other. The first direction signal DIR and the second direction signal DIRB are applied to both control terminals of the first transmission gate 331a. The first and second direction signals DIR and DIRB are opposite in phase. The first direction signal DIR and the second direction signal DIRB are also applied to both control terminals of the second transmission gate 331b. Of the control terminals of the first and second transmission gates 331a and 331b, control terminals to which the same direction signal is applied are connected to each other.

The switching control unit 332 controls the operation of the switching unit 333 and is controlled by an NMOS (nor gate 332a having first and second input terminals and an output terminal of the NOR gate 332a). 332b). The first input terminal of the NOR gate 332a is connected to the output terminal of the signal selector 331. The NOR gate 332a has a first and a second bias voltage, a driving voltage VDD is applied to the first bias voltage, and a clock signal CK2 is applied to the second bias voltage.

The NMOS 332b has a control terminal connected to an output terminal of the NOR gate 332a, an input terminal is connected to a reference voltage, and an output terminal is connected to a second input terminal of the NOR gate 332a.

The switching unit 333 is composed of a PMOS 333. If the switching unit 333 is configured as a PMOS instead of a transmission gate, the switching unit may serve as a simpler device. The control terminal of the PMOS 333 is connected to the output terminal of the NOR gate 332a, the input terminal of the PMOS 333 has a first clock signal CK1, and the output terminal of the PMOS 333 has a second input terminal of the NOR gate 332a. It is connected.

The buffer unit 334 receives the output signal of the switching unit 333 and outputs a shift register output signal DSR. The buffer unit 334 is composed of at least one semi-electric device connected in series.

The reset unit 335 is composed of an NMOS 335, a reset signal is applied to a control terminal of the NMOS 335, a reference voltage is applied to an input terminal, and an output terminal is an output terminal and a NOR of the switching unit 333. It is connected to the second input terminal of the gate 332a.

In the delay unit 336, an input terminal of the delay unit 336 is connected to an output terminal of the switching unit 333 to output a control signal LE1. The delay unit 336 includes at least one inverter connected in series.

The operation of the shift register according to the present invention will now be described.

First, when the reset signal is low level ("0"), the NMOS of the reset unit 333 is closed and resets the output of the shift register to "0". After that, the reset signal changes to the high level ("1") and waits until the start signal START comes out.

When the start signal START is output, the first and second input signals IN1 and IN2 are input to the signal selector 331. At this time, the first and second direction signals DIR and DIRB are applied to the control terminals of the first and second transfer transistors 331a and 331b. If the first direction signal DIR is at the high level (“1”) and the second direction signal DIRB is at the low level (“0”), the first transfer gate 331a is opened and the first input signal IN1 is Is output. When the first direction signal DIR is at a low level (“0”) and the second direction signal DIRB is at a high level (“1”), the second transfer gate 331b is opened and the second input signal IN2 is output. do.

The NOR gate 332a negatively multiplies the third and fourth input signals coming into the first and second input terminals. The third input signal is an output signal of the signal selector 331. If both the third and fourth input signals are low level ("0"), the output signal of the NOR gate 332a is high level ("1"), and both the third and fourth input signals are high level ("1"). Is a low level ("0"), one of the third and fourth input signals is a high level ("1"), and the other is a low level ("0"). The output signal of the back gate NOR gate 332a is at a low level ("0").

The NMOS 332b outputs a reference voltage VSS according to the output signal of the NOR gate 332a. That is, when the output signal of the NOR gate 332a is at the high level ("1"), the NMOS 332b is opened to output the reference voltage VSS, and when the low level is "0", the NMOS 332b is closed.

On the other hand, the output signal of the NOR gate 332a is input to the control terminal of the PMOS of the switching unit 334. If the output signal of the NOR gate 332a is at a high level ("1"), the PMOS is closed. At a low level ("0"), the PMOS is opened and the first clock signal CK is output.

The output signal of the switching unit 334 is input to the buffer unit 335 and output as the shift register output signal DSR1.

In addition, the output signal of the switching unit 334 is input to the delay unit 336 is delayed for a predetermined time and then output as an adjustment signal LE1. The adjustment signal LE1 is a signal that is input to the next stage ST2 to adjust the time for which the clock signals CK1 and CK2 are sampled. That is, referring to FIG. 7, there is a section in which the first clock signal CK1 and the adjustment signal LE1 are both at a high level (“1”). In this section, the shift register output signal DSR1 is at a high level (“”). Up to 1 "). Therefore, when the sampling interval is short, it is difficult to completely generate the shift register output signal DSR1. Since the shift register according to the present invention outputs the delayed control signal LE1 after being delayed, the sampling period can be extended, and the shift register output signal DSR1 can be generated smoothly.

On the other hand, the output terminal of the NMOS 332b of the switching control unit 332 and the output terminal of the PMOS of the switching unit 333 are both connected to the second input terminal of the NOR gate 332a. Therefore, the output signal of the NMOS 332b or the PMOS 333 is fed back to the NOR gate 332b. When the output of the NOR gate 332a is at the high level (“1”), the NMOS 332b of the switching controller 332 is opened, and at the low level (“0”), the PMOS of the switching unit 333 is opened. Therefore, the output signals of the NMOS 332b or the PMOS 333 are alternately input to the input terminal of the NOR gate 332a. In this way, the open and closed state of the switching unit 333 can be reliably controlled by the NMOS 332b.

At this time, a second clock signal CKB having a phase opposite to that of the first clock signal CK is applied to the second bias voltage of the NOR gate 332b. Therefore, when the second clock signal CKB is at the low level (“0”), it operates with the reference voltage VSS, and when it is at the high level (“1”), it operates with the driving voltage VDD. Therefore, the switching unit 333 may react more quickly according to the phase change of the clock signal.

The operation of the second stage ST2 is similar to that of the first stage ST1. The first input signal input to the direction selector 331 of the second stage ST2 is the adjustment signal LE1 output from the first stage ST1, and the second input signal is output from the third stage (not shown). Control signal LE3. In addition, the second clock signal CKB is applied to the input terminal of the PMOS of the switching unit 333, and the first clock signal CK is applied to the second bias voltage of the NOR gate 333a.

In this manner, the first clock signal CK1 and the second clock signal CKB are alternately sampled in the plurality of stages ST1, ST2..., And the shift register output signals DSR1, DSR2, DSR3... Are sequentially output.

When such a shift register is mounted in the gate driver 400, the shift register outputs DSR1, DSR2, DSR3 ... are gate outputs Gout1-k, and when the shift register output is mounted in the data driver 500, the shift register output ( DSR1, DSR2, DSR3 ... are the image data DAT transferred from the shift register 541 (see FIG. 4) to the latch 543. As shown in FIG.

According to the present invention, since the gate driver and the data driver are integrated on the display panel, the gate driver and the data driver may be more economically formed, and the operation speed and accuracy of the driver may be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

A shift register including a plurality of stages connected in series, Each of the plurality of stages, A signal selector which selects and outputs one of a first input signal and a second input signal according to a control signal; NOR GATE which uses the output signal of the said signal selection part as a 1st input signal, A first switching transistor configured to output a first clock signal according to the output signal of the NOR gate; A second switching transistor which outputs a reference voltage according to the output signal of the NOR gate and alternately operates with the first switching transistor; A delay unit configured to receive and delay the output of the first switching transistor; Including, The output signal of the first switching transistor and the output signal of the second switching transistor alternately enter the second input signal of the NOR gate. Shift register for display device. In claim 1, And the delay unit comprises at least one inverter connected in series. In claim 1, And an output terminal connected to the output terminals of the first and second switching transistors, the third switching transistor outputting a reference voltage according to a reset signal. In claim 3, And the third switching transistor comprises an NMOS. In claim 1, And the first switching transistor comprises a PMOS. In claim 1, And the second switching transistor comprises an NMOS. In claim 1, And the signal selector comprises first and second transfer gates connected in parallel. In claim 1, And a buffer unit configured to receive the output signal of the first switching transistor and output a shift register output signal. In claim 1, And at least one bias voltage of the NOR gate is subjected to a second clock signal that is out of phase with the first clock signal. In claim 1, And an output signal of the delay unit enters a first input signal of a neighboring stage. In claim 1, And an output signal of the delay unit enters a second input signal of a neighboring stage.

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