KR20050077573A - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of preventing distortion of a screen due to RC delay.

A plurality of pixels each including a switching element, a plurality of gate lines connected to the pixel to transfer a gate signal, a data driver to select a gray voltage corresponding to an image signal as a data voltage, and apply the data voltage to the pixel; A plurality of gate drivers configured to output the gate signal, and a signal controller configured to output a control signal to the gate driver and the data driver, wherein the plurality of gate drivers include first and second gate drivers. The gate driver includes a plurality of gate driver integrated circuits, the second gate driver is formed in the same process as the switching element of the pixel, and the first and second gate drivers are connected to the same gate line.

By compensating for the RC delay in this way, it is possible to prevent distortion of the screen and realize high screen quality while reducing costs.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. An electric field is applied to the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. Such liquid crystal displays are typical among flat panel displays (FPDs). Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

Meanwhile, the liquid crystal display includes a plurality of pixels, a liquid crystal panel assembly having a gate line and a data line connected to the pixels, a data driver and a pixel for applying a voltage corresponding to an image signal to the pixel through the data line as a gray scale voltage. And a gate driver configured to provide a gate signal through the gate line to open and close the switching element.

In the liquid crystal display, a switching element of a pixel to which a gate signal is applied is turned on, and a data voltage is transferred to the pixel through the turned on switching element to represent an image.

On the other hand, as the liquid crystal display device increases in size, the length of the gate line increases. As a result, an RC delay of the gate signal occurs due to an increase in resistance of the gate line, an increase in capacitance, and the screen may be distorted or its brightness may change.

For example, when the gate driver is positioned on the left side of the liquid crystal panel assembly, distortion occurs as the gate signal goes to the right due to the RC delay. As a result, only a part of the data voltage is transmitted or a distortion occurs, thereby degrading the image quality.

Accordingly, a technical problem to be solved by the present invention is to provide a driving device of a liquid crystal display device with no delay or distortion of a gate signal.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a plurality of pixels each including a switching element, a plurality of gate lines connected to the pixels to transfer a gate signal, and gray levels corresponding to image signals. A data driver for selecting a voltage as a data voltage and applying the same to the pixel, a plurality of gate drivers for outputting the gate signal to the gate line, and a signal controller for outputting control signals to the gate driver and the data driver; The plurality of gate drivers includes first and second gate drivers, the first gate driver includes a plurality of gate driver integrated circuits, and the second gate driver is formed in the same process as the switching element of the pixel.

Here, the first and second gate drivers are preferably connected to the same gate line. The second gate driver may receive the control signal through the data driver.

The first gate driver and the second gate driver may simultaneously apply the gate signal to the same gate line.

The second gate driver may include a plurality of shift registers arranged in a line, the shift register may include a plurality of switching elements, and the switching elements may be made of amorphous silicon.

Alternatively, the second gate driver may output an output based on the gate signal from the first gate driver, wherein the first and second gate drivers are connected to the same gate line.

The second gate driver may include a plurality of shift registers arranged in a line, the shift register may include a plurality of switching elements, and the switching elements may be made of amorphous silicon.

According to another exemplary embodiment of the present invention, the first gate driver is connected to an odd-numbered gate line, and the second gate driver is connected to an even-numbered gate line.

The second gate driver may include a plurality of shift registers arranged in a line, the shift register may include a plurality of switching elements, and the switching elements may be made of amorphous silicon.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, gate drivers 400L and 400R, a data driver 500, and data connected thereto. The gray voltage generator 800 connected to the driver 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

Hereinafter, reference numerals '400L' and '400R' are used for the left and right gate drivers, respectively, and reference numerals are referred to as '400' when referring to both gate drivers.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. It includes the line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate drivers 400L and 400R are connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to gate the gate signals formed by a combination of the gate on voltage V _on and the gate off voltage V _off . Applies to lines G ₁ -G _n .

Here, the gate drivers 400L and 400R according to the exemplary embodiment of the present invention are disposed on the left and right sides of the liquid crystal panel assembly 300 to simultaneously apply gate signals to the same gate lines G ₁ -G _n . This will be described later in detail. In addition, one of the two gate drivers 400L and 400R is formed of a chip, and the other is formed by the same process when forming the switching element Q of the pixel of the liquid crystal panel assembly 300. In the exemplary embodiment of the present invention, it is assumed that the left gate driver 400L includes a gate driver integrated circuit and the right gate driver 400R is integrated with the liquid crystal panel assembly 300.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After proper processing, the gate control signal CONT1 is sent to the left gate driver 400L, and the data control signal CONT2 and the processed image signals R ', G', and B 'are sent to the data driver 500. .

The gate control signal CONT1 includes a vertical synchronization start signal STV indicating the start of output of the gate on pulse (gate on voltage section), a gate clock signal CPV for controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives and shifts image data R ', G', and B 'corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage. The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the unit 800. Then, it is applied to the corresponding data line D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. When the switching element Q connected to the () is turned on, the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

Next, the structure and operation of the gate driver according to the exemplary embodiment of the present invention will be described in more detail.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

As illustrated, the gate driver 400 includes a plurality of shift registers 410 arranged in a line.

As described above, the left gate driver 400L includes a plurality of gate driver ICs, and the shift register 410 constituting the right gate driver 400R is formed and integrated in the same process as the switching element Q of the pixel. .

In addition, the shift register 410, as is known, includes a plurality of switching elements, and the switching elements are preferably made of amorphous silicon.

Referring back to FIG. 1, the left gate driver 400L receives the gate control signal CONT1 from the signal controller 600, while the right gate driver 400R receives the gate control signal CONT1 from the data driver 500. In addition to the vertical sync start signal STV, a gate on voltage V _on and a gate off voltage V _off may be applied. This can be implemented using a so-called LOG (line on glass) method. That is, although it may be substantially input from the signal controller 600 in the same manner as the left gate driver 400L, the input may be input through the data driver 500 to reduce the area occupied by the wiring. In addition, two clock signals CK1 and CK2 are also input from the data driver 500.

The gate drivers 400L and 400R start outputting the gate-on voltage V _on in response to the vertical synchronization start signal STVs from the signal controller 600 and the data driver 500, respectively. The gate-on voltage V _on is sequentially applied to G ₁ -G _n ).

The first shift register 410 starts outputting the gate-on voltage V _on in synchronization with the vertical synchronizing start signal STV and the clock signal CK1, and the output voltage and clock signal of the previous shift register from the second shift register. In synchronization with (CK1), the output of the gate-on voltage V _on is started.

As shown in FIG. 1, the gate-on voltage V _on is simultaneously output to the same gate line G ₁ -G _n . Then, when the gate-on voltage V _on is applied from _one side, it may be compensated if an RC delay or the like occurs on the opposite side of the gate line G ₁ -G _n .

Meanwhile, the vertical synchronization start signal STV and the two clock signals CK1 and CK2 input to the shift registers 410 of the right and left gate drivers 400L and 400R are the same.

In this way, a problem that the brightness of the screen changes due to the RC delay occurring at the edges of the gate lines G ₁ -G _n may be solved.

Meanwhile, the gate driver 400R according to the exemplary embodiment of the present invention described above operates independently by receiving the gate control signal CONT1 through the data driver 500.

Alternatively, the right gate driver 400R may operate based _on the gate-on voltage V _on from the left gate driver 400L.

In this case, when the left gate driver 400L outputs the gate-on voltage V _on , the right gate driver 400R may output the gate-on voltage V _on at the same time as the output of the gate-on voltage Von. ₁ -G _n ). When the gate-on voltage V _on is applied from the left gate driver 400L, the time when the signal is transmitted to the right gate driver 400R is substantially the same as 0 seconds as the electrons are transferred. At the same time, the right gate driver 400R may apply the gate-on voltage V _on to the gate lines G ₁ -G _n . Subsequently, each gate line G ₁ -G _n is charged as described above, and also prevents distortion of the gate-on voltage V _on caused by an RC delay occurring at both edges of the liquid crystal panel assembly 300. can do.

On the other hand, the embodiment described above can be applied when the RC delay is a problem in large area high resolution. On the contrary, a description will be given of an embodiment applicable to a small and medium-sized liquid crystal display in which RC delay is not a problem.

4 is an example of a driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 4, the descriptions of the signal controller 600, the data driver 500, and the gray voltage generator 800 are the same as those of the embodiment shown in FIG. The structure of is also the same as the embodiment shown in FIG.

In addition, since the operation of the shift register (see FIG. 3) constituting the gate driver 400 is the same, a description thereof will be omitted below.

1, the left gate driver 400L is formed of a plurality of gate driver ICs, and the right gate driver 400R is formed in the same process as the switching element of the pixel.

However, the left gate driver 400L is connected to the odd-numbered gate lines G ₁ , G ₃ , .. G _2n-1 , and the right gate driver 400R is the even-numbered gate lines G ₂ , G ₄ ,. ... G _2n ) is different from the embodiment shown in FIG. 1.

In this way, the number of gate driver ICs constituting the left gate driver 400L can be reduced by half to reduce costs.

As described above, one gate driver uses an integrated circuit, and the other gate driver is integrated in the same process as the switching element of the pixel, thereby reducing the cost and preventing distortion of the signal due to RC delay. A display device can be provided.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

4 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Claims (10)

A plurality of pixels each including a switching element, A plurality of gate lines connected to the pixels to transfer gate signals; A data driver which selects a gray voltage corresponding to an image signal as a data voltage and applies the same to the pixel; A plurality of gate drivers configured to output the gate signals to the gate lines, and A signal controller outputting a control signal to the gate driver and the data driver Including; The plurality of gate drivers include first and second gate drivers, The first gate driver includes a plurality of gate driver integrated circuits, and the second gate driver is formed in the same process as the switching element of the pixel. Liquid crystal display. In claim 1, The first and second gate drivers are connected to the same gate line. In claim 2, The second gate driver receives the control signal through the data driver. In claim 3, And the first gate driver and the second gate driver simultaneously apply the gate signal to the same gate line. In claim 4, The second gate driver includes a plurality of shift registers arranged in a line; The shift register includes a plurality of switching elements, And the switching element is made of amorphous silicon. In claim 1, And the second gate driver outputs an output based on the gate signal from the first gate driver. In claim 6, The first and second gate drivers are connected to the same gate line. In claim 7, The second gate driver includes a plurality of shift registers arranged in a line; The shift register includes a plurality of switching elements, And the switching element is made of amorphous silicon. In claim 1, And the first gate driver is connected to an odd-numbered gate line, and the second gate driver is connected to an even-numbered gate line. In claim 9, The second gate driver includes a plurality of shift registers arranged in a line; The shift register includes a plurality of switching elements, And the switching element is made of amorphous silicon.