KR20060013151A - Driving apparatus for display device - Google Patents

Abstract

The present invention relates to a driving device of a display device.

A gate driver for transmitting a gate signal, a gate driver including a plurality of stages respectively outputting the gate signal, and a signal controller configured to emit a plurality of control signals to the gate driver, wherein one of the plurality of control signals The gate signal and the high section coincide.

In this way, by reducing one of the gate control signals, the number of pins and associated wiring of the integrated circuit can be reduced, thereby securing design margins and reducing defects.

Display device, gate control signal, gate clock signal, output enable signal, vertical synchronization start signal, stage

Description

Drive device for display device {DRIVING APPARATUS FOR DISPLAY DEVICE}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a signal waveform diagram according to an embodiment of the present invention.

4 is a signal waveform diagram according to the prior art.

The present invention relates to a driving device of a display device.

Recently, organic electroluminescence display (OLED), plasma display panel (PDP), liquid crystal display (LCD), instead of heavy and large cathode ray tube (CRT) Flat panel display devices such as are being actively developed.

PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic EL display device displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display and an organic EL display include a pixel including a switching element, a display panel provided with a display signal line, and a gate-on voltage and a gate-off voltage applied to a gate line among the display signal lines, A gate driver for turning on / off the switching element, a data driver for outputting a data voltage to a data line among the display signal lines and applying the data voltage to the pixel through the turned on switching element, and a signal controller for controlling the switching elements.

The signal controller sends a gate control signal to the gate driver to control the operation of the gate driver. The gate control signal controls the vertical synchronization start signal (STV) indicating the start of the output of the gate-on voltage and the output timing of the gate-on voltage. And a gate enable signal CPV and an output enable signal OE for limiting the duration of the gate-on voltage.

At this time, the number of gate control signals is large, which increases the number of input / output pins of the signal control unit and the gate driver in the form of an integrated circuit, and requires wiring for transferring these signals.

Accordingly, an object of the present invention is to provide a driving device of a display device capable of reducing a control signal.

According to an aspect of the present invention, there is provided a driving apparatus of a display device, including: a gate line transferring a gate signal, a gate driver including a plurality of stages respectively outputting the gate signal, and the gate driver; And a signal controller configured to emit a plurality of control signals, wherein one of the plurality of control signals coincides with a high section of the gate signal.

In this case, one of the plurality of control signals may be a gate clock signal CPV.

In addition, the signal controller may make the width of the high section of the gate clock signal larger than the width of the low section, and the gate signal may be changed to high at the rising edge of the gate clock signal.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a driving device of a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.                     

1 is a block diagram of a display device according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display device according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. 4 is a waveform diagram of a gate control signal according to the present invention, and FIG. 4 is a waveform diagram of a gate control signal according to the related art.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal control unit 600 to control them.

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels Px connected to the plurality of display signal lines G ₁ -G _n and D ₁ -D _m in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a pixel circuit connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is connected to the pixel circuit. have. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display, which is a representative example of a flat panel display, the lower panel 100, the upper panel 200, and a liquid crystal layer 3 therebetween are included as shown in FIG. 2. The display signal lines G ₁ -G _n , D ₁ -D _m and the switching elements Q are provided on the lower display panel 100. The pixel circuit of the liquid crystal display device includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected to the switching element Q. The holding capacitor C _ST can be omitted as necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.

Referring back to FIG. 1, the gray voltage generator 800 generates one or two gray voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to gate a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. Applies to lines G ₁ -G _n . The gate driver 400 includes a plurality of stages arranged substantially in a row as a shift register.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.                     

The display operation of such a display device will now be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After appropriately processing the display panel 300 according to the operating conditions, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transferred to the data driver 500. Export.

The gate control signal (CONT1) includes a gate-on voltage vertical synchronization start signal (STV) for instructing the start of output of the (V _on), the gate-on voltage gated clock signal that controls the output timing of the (V _on) (CPV) and the gate-on And an output enable signal OE that defines the duration of the voltage V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display or the like shown in FIG. 2, the polarity of the data voltage with respect to the common voltage V _com (hereinafter referred to as "polarization of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage") is inverted. Inverted signal (RVS) may also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

3 illustrates a signal waveform diagram of a gate control signal according to an exemplary embodiment of the present invention, and FIG. 4 illustrates a signal waveform diagram of a gate control signal according to the related art.

Here, the gate driver 400 includes a plurality of stages arranged in a line as described above, and among the outputs of the plurality of stages, "Gout1" and "Gout2" indicate gate signals as outputs of the first and second stages. .

As illustrated in FIG. 3, the gate driver 400 emits the gate outputs Gout1 and Gout2 when the first gate clock signal CPV becomes high after the vertical synchronization start signal STV is input. The first gate output Gout1 goes high on the rising edge of the gate clock signal CPV and goes to the low level on the falling edge, and again from the time when the gate clock signal CPV goes high, the second gate clock signal ( Gout2) is generated. That is, the high period of the gate clock signal CPV and the high period of the gate outputs Gout1 and Gout2 coincide with each other.

At this time, as shown in Fig. 4, when the signal waveform of the gate control signal according to the prior art is seen, the gate outputs Gout1 and Gout2 become high at the rising edge of the gate clock signal CPV and then enable the output. It goes low on the rising edge of signal OE. In this case, the low period of the output enable signal OE and the high period of the gate outputs Gout1 and Gout2 coincide with each other.

Meanwhile, the signal controller 600 may adjust the width of the high section of the gate clock signal CPV. For example, if the duty ratio of the gate clock signal of the gate control signal according to the related art is 50%, the present invention may be implemented. It can be seen that the gate clock signal CPV according to the example is more than that, which can be adjusted by the signal controller 600.

In this way, the gate control signal can be reduced to reduce the number of pins in the integrated circuit, as well as the wiring for delivering this signal, thereby ensuring design margins.

In the case of the liquid crystal display of FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. In the case of the liquid crystal display shown in FIG. 2, in particular, when one frame ends, the next frame starts and an inversion signal applied to the data driver 500 such that the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame. The state of (RVS) is controlled ("frame inversion"). At this time, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS even in one frame (eg, "row inversion", "point inversion"), The polarities can also be different (eg "invert columns", "invert points")

As described above, one of the gate control signals CONT2 may be reduced to reduce the number of pins of the integrated circuit, and the signal wiring may be reduced to secure design margins and to reduce defects.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (4)

A gate line for transmitting a gate signal, A gate driver including a plurality of stages respectively outputting the gate signals, and Signal control unit for sending a plurality of control signals to the gate driver Including; One of the plurality of control signals corresponds to a high section of the gate signal Drive device for display device. In claim 1, One of the plurality of control signals is a gate clock signal (CPV). In claim 2, And the signal controller is configured to make the width of the high section of the gate clock signal larger than the width of the low section. In claim 3, And the gate signal is turned high at the rising edge of the gate clock signal.

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