KR20020064397A - THIN FLIM TRANSISTER LIQUID CRYSTAL DISPLAY DEVICE INCLUDING DUAL TFTs PER ONE PIXEL AND DRIVING METHOD OF THE SAME - Google Patents

Abstract

PURPOSE: A TFT-LCD(Thin Film Transistor-Liquid Crystal Display) having two TFT per pixel and a method for driving the same are provided to reduce the number of driving ICs by having a driving circuit for driving two TFTs in an LCD having two TFTs per pixel. CONSTITUTION: A TFT-LCD having two TFT per pixel includes a liquid crystal display(LCD) panel(108) having a plurality of pixels, a liquid capacitor(CLc) per pixel and first and second TFTs(T1,T2), a voltage generating circuit(106) for generating a plurality of panel power voltages required for the LCD panel, a timing controller(104) for outputting control signals for driving the second TFTs, gate driver integrated circuits(ICs;120-124) for outputting a plurality of gate driving signals for driving the first TFTs under the control of the timing controller, source driver ICs(110-114) having a plurality of data lines for applying liquid crystal voltages of the plurality of liquid crystal capacitors, and a driving circuit(130) for outputting at least two driving signals for driving the second TFTs according to the control signals and the panel voltage voltages, wherein the liquid crystal capacitors are charged when the first and second TFTs are turned on simultaneously by the gate driving signals and the at least two driving signals.

Description

A thin film liquid crystal display device having two thin film transistors per pixel and a driving method thereof {THIN FLIM TRANSISTER LIQUID CRYSTAL DISPLAY DEVICE INCLUDING DUAL TFTs PER ONE PIXEL AND DRIVING METHOD OF THE SAME}

The present invention relates to a thin film liquid crystal display device, and more particularly, to a liquid crystal display device having two thin film transistors per pixel and a driving method thereof.

Referring to FIG. 1, a general thin film liquid crystal display module 10 includes a timing controller 14, a gray voltage generator 12, a panel voltage generator 16, gate driver circuits 30 to 34, and a source driver circuit. And the liquid crystal panel 18.

The timing controller 14 includes basic timing signals necessary for displaying an image from a video signal source (not shown) such as a personal computer, a camcorder, for example, a data clock signal MCLK, a horizontal sync signal Hsync, a vertical sync signal. (Vsync), R, G, B data (RGB data) signals, data enable signal (DE) and the like. In addition, the timing controller 14 may control various control signals necessary for driving the gate driver circuits 30 to 34 and the source driver circuits 20 to 24, for example, the horizontal clock signal HCLK and the horizontal start signal STH. , A load signal TP, a gate clock signal, a vertical start signal STV, a scan enable signal OE, and the like are output.

The panel voltage generation circuit 16 accepts the output voltages VDD of a DC / DC converter (not shown) to allow a gate-on voltage Von of 20 V to 30 V and a gate of about -10 V to -2 V. The off voltage Voff and the common electrode voltage Vcom of 5 V to 7 V are generated. The gray voltage generator 12 generates gray voltages for adjusting the light transmittance of the liquid crystal to the source driver circuits 20 to 24.

The gate driver circuits 30 to 34 generate gate driving signals that sequentially select gate lines on the liquid crystal panel 18 so that image signal voltages can be transferred to each pixel of the liquid crystal panel 18. The source (data) driver circuits 20 to 24 convert the digital R, G, and B data signals (RGB data) provided from the timing controller 14 into analog signals to select pixels on the liquid crystal panel 18. to provide.

As shown in FIG. 2, the liquid crystal panel 18 includes a plurality of pixel arrays formed on a semiconductor substrate. In the pixel array, a plurality of gate lines Gj to Gj + 3, a plurality of data lines Di to Di + 3, and a plurality of pixel circuits are arranged in rows and columns. Each pixel circuit uses a thin film transistor T1 that functions as a switch and a liquid crystal as a dielectric, and locally adjusts the amount of light passing through the light transmission characteristic of the liquid crystal in response to an applied voltage. It consists of a liquid crystal capacitor (C _LC ) and a storage capacitor (C _ST ) for increasing the ability of collecting charges accumulated across the liquid crystal.

Accordingly, the liquid crystal panel is driven when the image signal voltage is applied to the corresponding liquid crystal capacitor through one thin film transistor per pixel. At this time, when the thin film transistor is turned off, the liquid crystal capacitor is in a floating state, and as a result, the applied signal voltage is maintained. According to such an operation principle, when all pulses are sequentially applied to the gate electrodes and image signal voltages are respectively applied to the corresponding source electrodes, all the pixels of the panel are driven.

Therefore, in the liquid crystal display device, the source drive ICs 20 to 24 simultaneously provide data corresponding to the gate lines activated by the gate drive ICs 30 to 34 to the data lines Di to Di + 3, thereby providing a color image. Is expressed.

As described above, a liquid crystal display module having a general thin film transistor configures a pixel using one thin film transistor. The liquid crystal display module having such a configuration has a disadvantage of increasing the number of driver ICs, which occupy a large proportion of the production cost.

For example, for a 3 color 800 * 600 resolution SVGA class liquid crystal display module. Eight 300-channel source (data) driver ICs are required, and 150-channel gate driver ICs are required. However, in general, since the drive IC occupies a large portion of the production cost required to produce the liquid crystal display module, if the number of drive ICs provided in the liquid crystal display module is reduced, the production cost of the liquid crystal display module may be significantly reduced.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to implement an apparatus and a method for reducing a driver IC of a liquid crystal display device having two thin film transistors per pixel.

1 is a block diagram showing the configuration of a general liquid crystal display module;

FIG. 2 is a block diagram showing some components for explaining the operation of the liquid crystal display module shown in FIG. 1;

3 is a block diagram showing a configuration of a liquid crystal display module according to the present invention;

4 is a diagram schematically showing a connection configuration to a signal line of the liquid crystal display module shown in FIG. 3;

5 is a detailed circuit diagram according to an embodiment of the driving circuit shown in FIG. 3;

6 is a circuit diagram showing a part of a configuration of a liquid crystal display module according to a first embodiment of the present invention;

FIG. 7 is a waveform diagram illustrating the operation of the liquid crystal display module shown in FIG. 6;

8 is a circuit diagram showing a part of a configuration of a liquid crystal display module according to a second embodiment of the present invention; And

9 is a waveform diagram illustrating an operation of the liquid crystal display module illustrated in FIG. 8.

Explanation of symbols on the main parts of the drawings

100: liquid crystal display module 102: gradation voltage generating circuit

104: timing controller 106: panel voltage generation circuit

108: dual TFT liquid crystal panel 110 to 114: source drive IC

120 to 124: gate drive IC 130: drive circuit

According to an aspect of the present invention for achieving the above object, a liquid crystal display device comprising: a liquid crystal panel having a plurality of pixels, one liquid crystal capacitor and first and second thin film transistors per pixel; ; A voltage generator circuit for generating a plurality of panel power supply voltages required for the liquid crystal panel; A timing controller outputting a control signal for driving the second thin film transistors; Gate driver integrated circuits configured to output a plurality of gate driving signals for driving the first thin film transistors under the control of the timing controller; Source driver integrated circuits having a plurality of data lines for applying liquid crystal voltages of the plurality of liquid crystal capacitors; A driving circuit receiving the control signal and the panel power supply voltages and outputting at least two driving signals for driving the second thin film transistor; The liquid crystal panel is charged with the liquid crystal capacitors when the first and second thin film transistors are simultaneously turned on by the gate driving signals and the at least two driving signals.

In a preferred embodiment of the present invention, the liquid crystal panel is configured such that the lines into which the at least two driving signals are input in the vertical direction are sequentially connected to the second thin film transistor, but the lines into which the gate driving signals are input. The odd and even numbers are connected to each other.

In this embodiment, the liquid crystal panel outputs the at least two drive signals and the data signals each with a pulse width of one gate line time, and simultaneously the gate drive signals are each N times (N is a positive integer). It is driven by being output at the pulse width of the gate line time.

In a preferred embodiment of the present invention, the liquid crystal panel may include a line through which a first driving signal is input among the at least two driving signals in a horizontal direction and connected to the second thin film transistor of a specific pixel among the pixels. And a line to which a second driving signal is input is sequentially connected to the second thin film transistor of a next pixel of the specific pixel; The plurality of data signal lines are connected such that odd and even numbers are shared with each other in a horizontal direction.

In this embodiment, the liquid crystal panel outputs the at least two drive signals and the data signals at a pulse width of 1 / N gate line time, respectively, and simultaneously the gate drive signals are each at a pulse width of 1 gate line time. It is driven by the output.

In a preferred embodiment of the present invention, the liquid crystal panel includes a dummy line of a tape carrier package (TCP) of source drive integrated circuits in which the at least two driving signals are respectively provided at both ends of the liquid crystal panel. ) Are provided in a 'c' shape wiring.

In a preferred embodiment of this aspect, the driving circuit outputs the odd-numbered driving signal and the even-numbered driving signal among the at least two driving signals so that they have a phase difference of 180 degrees.

In a preferred embodiment of this aspect, the driving circuit comprises a level shifter composed of a plurality of capacitors and resistors, a P channel transistor, and an N channel transistor, wherein the at least two drive signals comprise the control signal and the panel power supply. The voltages are received and output at a signal level between the panel power supply voltages.

(Action)

Therefore, according to the present invention, the driving circuit receives the control signal from the timing controller and outputs first and second driving signals for driving the second thin film transistor. The first thin film transistor is driven by the gate driving circuit. Therefore, the liquid crystal panel is charged with the liquid crystal capacitor when the first and second thin film transistors are driven simultaneously.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a liquid crystal display module according to the present invention.

Referring to the drawings, the liquid crystal display module 100 includes a novel timing controller 104, a driving circuit 130, and a liquid crystal panel 108. The liquid crystal display module 100 includes a plurality of gate drive circuits 120 to 124, a plurality of source driver circuits 110 to 114, a panel voltage generator circuit 106, and a gray voltage generator circuit 102. do.

As illustrated in FIGS. 6 to 8, the liquid crystal panel 108 includes two, that is, first and second thin film transistors T1 and T2 and one liquid crystal capacitor CLc per pixel.

The timing controller 104 outputs a timing signal CTRL for driving the second thin film transistors T2 to the driving circuit 130. Basic timing signals necessary for displaying an image from a video signal source (not shown), that is, a data clock signal MCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, R, G, and B data (RGB) various control signals required for driving the gate driver circuits 120 to 124 and the source driver circuits 110 to 114 by receiving the data, the data enable signal DE, and the like, for example, the horizontal clock signal HCLK. ), A horizontal start signal STH, a load signal TP, a gate clock signal (Gate Clock), a vertical start signal STV, a scan enable signal OE, and the like.

The gate clock signal (Gate Clock) output by the timing controller 104 is a clock signal supplied to the gate driver circuits 120 to 124, the period of which is the time of the horizontal clock signal HCLK corresponding to one horizontal line. Or the number of pulses. The vertical start signal STV is a signal for allowing the gate-on voltage Von supplied from the panel voltage generator circuit 106 to be transferred to the liquid crystal panel 108 through the gate driver circuits 120 to 124, and scan. The enable signal OE is a signal for bringing the gate driver circuits 120 to 124 into an output enable state.

In addition, the horizontal clock signal HCLK is a signal synchronized with the data clock signal MCLK so that the R, G, and B data signals RGB data may be properly synchronized with the specifications of the source drive circuits 50. The horizontal start signal STH is a reference signal for precisely latching the R, G, and B data signals RGB data input from the video signal source (not shown) to the source driver circuits 110 to 114. to be. The load signal TP is a signal for allowing the R, G, and B data signals RGB data latched in the source driver circuits 110 to 114 to be provided to the liquid crystal panel 108.

The panel voltage generation circuit 106 accepts output voltages VDD of a DC / DC converter (not shown), and has a gate on voltage Von of 20 V to 30 V, and a gate off voltage of about −10 V to −2 V. Voff) and a common electrode voltage Vcom of 5V to 7V. The gray voltage generator 102 generates gray voltages for controlling the light transmittance of the liquid crystal to the source driver circuits 110 to 114. The gate on voltage Von and the gate off voltage Voff are output to the driving circuit 130.

The gate driver circuits 120 to 124 generate gate driving signals that sequentially select gate lines on the liquid crystal panel 108 so that image signal voltages may be transferred to each pixel of the liquid crystal panel 108. . Here, the gate line will be described in detail with reference to FIGS. 6 to 8.

The source driver circuits 110 to 114 convert the digital R, G, and B data signals (RGB data) provided from the timing controller 104 into analog signals and convert them into selected pixels on the liquid crystal panel 108. to provide.

The driving circuit 130 receives the timing signal CTRL and outputs first and second driving signals CTRL1 and CTRL2. In detail, referring to FIG. 5, the driving circuit 130 receives the timing signal CTRL and outputs the first driving signal CTRL1, and the timing signal CTRL is an inverter INV. And a second block for outputting the second driving signal CTRL2 180 degrees out of phase. The first block includes one PNP transistor TP1, one NPN transistor TN1, two capacitors C1 and C2, and three resistors R1 to R3. The second block includes an inverter, one PNP transistor TP2, one NPN transistor TN2, two capacitors C3 and C4, and three resistors R4 to R6. Here, the capacitor and resistors operate as level shift circuits in each block. In addition, the driving circuit 130 receives the gator on voltage Von and the gate off voltage Voff from the panel voltage generation circuit 106 to switch between the first and second driving signals (S). Output CTRL1, CTRL2).

Therefore, the liquid crystal panel 108 includes two thin film transistors per pixel, the first thin film transistor T1 is driven by a gate driving signal, and the second thin film transistor T2 is connected to the first thin film transistor T2. And second drive signals CTRL1 and CTRL2. That is, when the first and second thin film transistors T1 and T2 are turned on at the same time, when the image signal voltage is applied to the corresponding liquid crystal capacitor through the data line, the liquid crystal is charged.

At this time, when the thin film transistor is turned off, the liquid crystal capacitor is in a floating state, and as a result, the applied signal voltage is maintained. According to such an operation principle, when all pulses are sequentially applied to the gate electrodes and image signal voltages are respectively applied to the corresponding source electrodes, all the pixels of the panel are driven. As a result, the number of gate drive circuits or source drive circuits can be reduced to one half.

Referring back to FIG. 4, the liquid crystal display module 100 receives the first and second driving signals CTRL1 and CTRL2 connected to the second thin film transistor T2 on both sides of the source drive circuits S1. And a Dummy line of a tape carrier package (TCP) of S4) to be connected to the liquid crystal panel 108. In addition, the entire wiring structure is formed in a 'c' shape in which both ends of the liquid crystal panel are connected, so that the driving signal is generated by using another path even if the first and second driving signals CTRL1 and CTRL2 are cut off at one place. By being connected to the liquid crystal panel 108, it is possible to prevent a decrease in yield due to process line open.

6 illustrates a pixel circuit corresponding to two adjacent pixels of the liquid crystal display panel according to the first exemplary embodiment of the present invention, and FIG. 7 illustrates waveforms for explaining a driving operation of the liquid crystal panel illustrated in FIG. 6. It is also. In this case, an embodiment for reducing the number of gate drive circuits is shown.

Referring to FIG. 6, the liquid crystal panel 108 includes two thin film transistors T1 and T2 and a liquid crystal capacitor CLc _2n-1 and CLc _2n per pixel. In addition, the odd-numbered line GL _2n-1 and the even _- numbered line GL _2n are connected to the output terminal GL _i of the gate drive circuit in common. Therefore, the number of output stages of the gate drive circuit is reduced to 1/2.

The first thin film transistor T1 is connected to the gate lines GL _2n-1 and GL _2n , and the second thin film transistor T2 is the first CTRL1 or the second driving signal CTRL2. Connected to the line.

First, the output GL _i of the gate drive circuit is output at a pulse width of 2 gate line times 2H, and is connected to and connected to the gate lines GL _2n-1 and GL _{2n of} the first thin film transistor T1. The first thin film transistor T1 is turned on. At this time, the first CTRL1 or the second driving signal CTRL2 line connected to the gate line of the second thin film transistor T2 has a pulse of one gate line time 1H, as shown in FIG. 7. It is applied to have a width and a phase difference of one gate line time.

Therefore, the voltage across the data line DL _j is transferred to the liquid crystal capacitors CLc _2n-1 and CLc _2n only when the first and second thin film transistors T1 and T2 are simultaneously turned on. As a result, the same result as that of the method of charging the liquid crystal capacitor during the conventional one gate line time can be obtained.

Therefore, the driving characteristics of the thin film liquid crystal display module can be maintained while reducing the number of gate drive circuits by 1/2. This result is not limited to only two drive signals, but when a plurality of drive signals are provided, that is, the number of gate drive circuits can be reduced to 1 / N correspondingly. At this time, the turn-on pulse width connected to the gate line of the first thin film transistor T1 becomes N * 1H, and the N driving signals are output with pulse widths of one gate line time, respectively, and they are each of A signal having a period of N * 1H having a phase difference is obtained. For example, in the case of the thin film liquid crystal display module having four driving signal lines, the liquid crystal display module using four conventional 150 channel gate drive circuits is applied to the case of the first embodiment. One circuit may be provided to drive the thin film liquid crystal display module.

Subsequently, a second embodiment according to the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 illustrates a partial configuration of the liquid crystal panel according to the second embodiment, and FIG. 9 is a waveform diagram for describing a driving operation of the liquid crystal panel shown in FIG. 8. The embodiment in this case aims at reducing the number of source drive circuits by half.

Referring to FIG. 8, the liquid crystal panel 108 includes two thin film transistors T1 and T2 and a liquid crystal capacitor CLc _2m-1 and CLc _2m per pixel. Gate lines GL _i and GL _{i + 1} are connected to the first thin film transistors T1 in the vertical direction, respectively. The first driving signal CTRL1 is connected to the odd-numbered second thin film transistor T2 in the horizontal direction, and the second driving signal CTRL2 is the even-numbered second thin film transistor T2 in the horizontal direction. )

Accordingly, each of the first thin film transistors T1 for odd-numbered and even-numbered pixels sharing the same data line DL _j is connected to the same gate line. The thin film transistor T2 is connected to different driving signals. That is, the second thin film transistor T2 of the odd-numbered pixel is connected to the first driving signal CTRL1 line, and the second thin film transistor T2 of the even-numbered pixel is the second driving signal CTRL2. ) Is connected to the line.

Referring to FIG. 9, an operation of the liquid crystal panel 108 is performed. In the data line DL _j , the liquid crystal voltages of the odd-numbered pixels and the liquid crystal voltages of the even-numbered pixels are respectively 1/2 gated from the source drive circuit. Applied for line time (1 / 2H). In addition, a turn-on voltage having a 1 H time pulse width is applied to the first thin film transistor T1 by the gate drive circuit, and the first and second driving signals CTRL1 and CTRL2 are 1. A 1 H period signal having a / 2 H pulse width is applied to the gate terminal of the second thin film transistor T2. Accordingly, the first and second thin film transistors T1 and T2 are simultaneously turned on to charge the liquid crystal voltages to the liquid crystal capacitors CLc _2m-1 and CLc _2m .

As described above, since the odd-numbered and even-numbered pixels share one data line, the number of data lines is reduced to 1/2. Therefore, the number of source drive circuits required for the entire liquid crystal panel is also reduced to 1/2. For example, if the source drive circuit driving the SVGA resolution uses eight existing 300 channels, the present embodiment can reduce the number to four.

As described above, the present invention can reduce the number of drive integrated circuits by including a driving circuit for driving two thin film transistors in a liquid crystal display device having two thin film transistors per pixel.

Therefore, by reducing the number of drive integrated circuits that occupy a large proportion of the manufacturing cost of the liquid crystal display device of the liquid crystal display device, it is possible to reduce the manufacturing cost of the liquid crystal display device.

Claims (8)

In the liquid crystal display device: A liquid crystal panel having a plurality of pixels, the liquid crystal panel including one liquid crystal capacitor and first and second thin film transistors per pixel; A voltage generator circuit for generating a plurality of panel power supply voltages required for the liquid crystal panel; A timing controller outputting a control signal for driving the second thin film transistors; Gate driver integrated circuits configured to output a plurality of gate driving signals for driving the first thin film transistors under the control of the timing controller; Source driver integrated circuits having a plurality of data lines for applying liquid crystal voltages of the plurality of liquid crystal capacitors; A driving circuit receiving the control signal and the panel power supply voltages and outputting at least two driving signals for driving the second thin film transistor; And the liquid crystal panel is charged with the liquid crystal capacitors when the first and second thin film transistors are simultaneously turned on by the gate driving signals and the at least two driving signals. The method of claim 1, The liquid crystal panel is configured such that lines into which the at least two driving signals are input in the vertical direction are sequentially connected to the second thin film transistor. And the lines into which the gate driving signals are input are connected such that odd and even numbers are shared with each other. The method of claim 2, The liquid crystal panel outputs the at least two driving signals and the data signals each at a pulse width of one gate line time, and simultaneously the gate driving signals are each N times pulses of a gate line time. A liquid crystal display device driven by being output in width. The method of claim 1, In the liquid crystal panel, a line in which a first driving signal is input among the at least two driving signals in a horizontal direction is connected to the second thin film transistor of a specific pixel among the pixels. A line to which a second driving signal is input is configured to be sequentially connected to the second thin film transistor of a next pixel of the specific pixel; And the plurality of data signal lines are connected such that an odd number including the specific pixel and an even number including a next pixel of the specific pixel are mutually shared in the horizontal direction. The method of claim 4, wherein The liquid crystal panel is driven by outputting the at least two driving signals and the data signals with a pulse width of 1 / N gate line time, respectively, and simultaneously outputting the gate driving signals with a pulse width of 1 gate line time. Liquid crystal display device characterized in that. The method of claim 1, The liquid crystal panel has a '-' shape using dummy lines of a tape carrier package (TCP) of source drive integrated circuits, each of which the at least two driving signals are provided at both ends of the liquid crystal panel. And wiring of the liquid crystal display device. The method of claim 1, And the driving circuit outputs an odd-numbered driving signal and an even-numbered driving signal among the at least two driving signals so that they have a phase difference of 180 degrees with each other. The method according to claim 1 or 7, The driving circuit includes a level shifter composed of a plurality of capacitors and resistors, a P channel transistor, and an N channel transistor, And the at least two driving signals receive the control signal and the panel power voltages and are output at a signal level between the panel power voltages.