CN113870762B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN113870762B CN113870762B CN202111156473.7A CN202111156473A CN113870762B CN 113870762 B CN113870762 B CN 113870762B CN 202111156473 A CN202111156473 A CN 202111156473A CN 113870762 B CN113870762 B CN 113870762B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Abstract
The application discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises: the pixel units are arranged in an array and further comprise a plurality of time sequence control lines and a plurality of gating control lines; the row timing control circuit is configured to sequentially start the connection of scanning lines in the scanning unit with odd pixel rows and even pixel rows; the column timing control circuit is configured to control the data writing sequence of the data lines to the sub-pixels to be a first sub-pixel, a second sub-pixel and a third sub-pixel when the scanning lines scan odd pixel rows; when the scanning line scans the even pixel rows, the data line is controlled to write the data of the sub-pixels into the third sub-pixel, the second sub-pixel and the first sub-pixel in sequence; the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
Description
Technical Field
The present disclosure relates generally to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
Background
Current display technology updates iterates and the market is more enthusiastic for high frame rate display products. A high frame rate product means that the number of frames displayed in the same time is greater than a low frame rate product, and thus the display time per frame becomes less.
In the related art, a display panel includes a plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction, the gate lines and the data lines crossing to define a plurality of sub-pixels. When driving the sub-pixels to emit light, the scan driving circuit sequentially drives the first to last gate lines to be opened according to a certain scan frequency, thereby sequentially outputting scan signals to the first to last rows of sub-pixels.
This is most serious for display products, namely insufficient pixel charge time and insufficient VCOM coupling voltage recovery time. These influencing factors can lead to a number of disadvantages, in particular crosstalk at high frame rate levels.
Disclosure of Invention
In view of the foregoing drawbacks or shortcomings in the prior art, it is desirable to provide a display panel, a driving method thereof, and a display device that can effectively solve crosstalk at a high frame frequency level.
In a first aspect, the present application provides a display panel, comprising:
the pixel units are arranged in an array manner, form a plurality of pixel rows which are arrayed along a first direction and a plurality of pixel columns which are arrayed along a second direction, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged along the row direction, and further comprises a plurality of time sequence control lines and a plurality of gating control lines;
a plurality of scanning lines configured to scan with one scanning unit in two adjacent pixel rows, one of the scanning units including an odd pixel row and a next even pixel row adjacent to the odd pixel row;
the data lines are configured to write data into the pixel columns, and the same sub-pixels correspond to the same pixel column;
a row timing control circuit configured to sequentially turn on connection of the scanning lines with the odd-numbered pixel rows and the even-numbered pixel rows in the scanning unit;
a column timing control circuit configured to control an order of data writing of the data lines to the sub-pixels to be a first sub-pixel, a second sub-pixel, and a third sub-pixel when the scanning line scans the odd-numbered pixel row; when the scanning line scans the even pixel rows, the data writing sequence of the data line to the sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
Further, the line sequence control circuit comprises a first control line for controlling the scanning line to scan the odd pixel row and a second control line for controlling the scanning line to scan the even pixel row.
Optionally, the line-timing control circuit includes first transistors in one-to-one correspondence with the odd pixel rows and second transistors in one-to-one correspondence with the even pixel rows, wherein,
the first end of the first transistor is connected with the corresponding odd pixel row, the second end of the first transistor is connected with the scanning line corresponding to the pixel row, and the control end of the first transistor is connected with the first control line;
the first end of the second transistor is connected with the corresponding even pixel row, the second end of the second transistor is connected with the scanning line corresponding to the pixel row, and the control end of the second transistor is connected with the second control line.
Optionally, the column timing control circuit includes a first gate line for controlling the data line to write data into the pixel column where the first subpixel is located, a second gate line for controlling the data line to write data into the pixel column where the second subpixel is located, and a third gate line for controlling the data line to write data into the pixel column where the third subpixel is located.
Optionally, the column timing control circuit includes a third transistor corresponding to the pixel column of the first sub-pixel, a fourth transistor corresponding to the pixel column of the second sub-pixel, and a fifth transistor corresponding to the pixel column of the third sub-pixel,
the first end of the third transistor is connected with the corresponding pixel column, the second end of the third transistor is connected with the data line corresponding to the pixel column, and the control end of the third transistor is connected with the first gating line;
the first end of the fourth transistor is connected with the corresponding pixel column, the second section of the fourth transistor is connected with the data line corresponding to the pixel column, and the control end of the fourth transistor is connected with the second gating line;
the first end of the fifth transistor is connected with the corresponding pixel column, the second section of the fifth transistor is connected with the data line corresponding to the pixel column, and the control end of the fifth transistor is connected with the third gating line.
Optionally, the turn-on sequence of the sub-pixels in two pixel rows in one of the scanning units is one of the following sequences:
the odd pixel rows are sequentially opened according to red/blue/green sub-pixels, and the even pixel rows are sequentially opened according to green/blue/red sub-pixels;
the odd pixel rows are sequentially opened according to the blue/red/green sub-pixels, and the even pixel rows are sequentially opened according to the green/red/blue sub-pixels;
the odd pixel rows are sequentially opened according to green\red\blue sub-pixels, and the even pixel rows are sequentially opened according to blue\red\green sub-pixels; a kind of electronic device with high-pressure air-conditioning system
The odd pixel rows are sequentially opened according to the green/blue/red sub-pixels, and the even pixel rows are sequentially opened according to the red/blue/green sub-pixels.
Optionally, in a scanning period in which the scanning line scans one of the scanning units, the line sequence control circuit includes a first control signal provided to the first control line and a second control signal provided to the second control line, where the first control signal includes a first active level controlling the first transistor to be turned on and a first inactive level controlling the first transistor to be turned off, and the second control signal includes a second active level controlling the second transistor to be turned on and a second inactive level controlling the second transistor to be turned off.
Optionally, the column timing control circuit continues an active level of a third gate signal supplied to a third gate line during a scan period in which the scan line scans one of the scan cells.
Optionally, the timing of the active level of the third strobe signal partially coincides with the timing of the first active level, and the timing of the active level of the third strobe signal partially coincides with the timing of the second active level.
Optionally, the column timing control circuit provides a first gate signal to the first gate line, a timing of an active level of the first gate signal partially coincides with a timing of the first inactive level, and a timing of an active level of the first gate signal partially coincides with a timing of the first active level.
Alternatively, two adjacent pixel rows in the same scanning unit are connected by the same scanning line.
In a second aspect, the present application provides a driving method of a display panel, applied to the display panel as described in any one of the above, the method comprising:
scanning is performed by the scanning line in one scanning unit in two adjacent pixel rows, wherein the scanning period corresponding to one scanning unit comprises an odd line scanning stage and an even line scanning stage,
in the odd-numbered line scanning stage, the connection between the scanning line and the odd-numbered pixel line is controlled and started by a line time control circuit; the sequence of controlling the data writing of the data line sub-pixels is controlled to be a first sub-pixel, a second sub-pixel and a third sub-pixel through a column time sequence control circuit;
in the even line scanning stage, the connection between the scanning line and the even pixel line is controlled to be started through a time sequence control circuit; the data writing sequence of the data line sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
In a third aspect, the present application provides a display device comprising a display panel as described in any one of the above.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
according to the display panel provided by the embodiment of the application, the two pixels are used as one scanning unit, so that the opening time of the sub-pixels in the scanning unit is controlled, the high-frequency crosstalk is solved, and the power consumption of the module can be reduced; the related defects caused by the coupling voltage of the common electrode during the charging of the green sub-pixel can be solved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the relationship between crosstalk and charging time according to an embodiment of the present disclosure;
FIG. 3 is a graph showing the voltages of the common electrode at high and low frequencies according to the embodiment of the present application;
FIG. 4 is a graph of the duty cycle of each color in white light provided by embodiments of the present application;
FIG. 5 is a schematic diagram of a gray scale display according to an embodiment of the present application;
fig. 6 is a schematic diagram of a driving timing sequence corresponding to a first display panel according to an embodiment of the present application;
fig. 7 is a schematic diagram of a driving timing sequence corresponding to a first display panel according to an embodiment of the present application;
fig. 8 is a schematic diagram of a driving sequence corresponding to a first display panel according to an embodiment of the present application;
fig. 9 is a schematic diagram of a driving sequence corresponding to a first display panel according to an embodiment of the present application;
fig. 10 is a flowchart of a driving method of a display panel according to an embodiment of the present application.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 1 in detail, in a first aspect, the present application provides a display panel, including:
the pixel units are arranged in an array mode, a plurality of pixel rows which are arranged along a first direction and a plurality of pixel columns which are arranged along a second direction are formed by the pixel units, and each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged along the row direction.
The first sub-pixel, the second sub-pixel and the third sub-pixel are sub-pixels with different colors and are used for realizing color display. In the embodiment of the present application, the first direction and the second direction are defined to be perpendicular to each other, the sub-pixels arranged along the first direction are defined as pixel rows, the sub-pixels arranged along the second direction are defined as pixel columns, and in some embodiments, the first direction and the second direction may be interchanged, and the pixel rows and the pixel columns may also be interchanged.
In the embodiment of the present application, the first subpixel is a red subpixel R, the second subpixel is a green subpixel G, and the third subpixel is a blue subpixel B. The arrangement order of the different sub-pixel colors is not limited in the embodiment of the present application.
A plurality of Scan lines Scan configured to Scan with one Scan unit in two adjacent pixel rows, one Scan unit including an odd pixel row and a next even pixel row adjacent to the odd pixel row.
And the Data lines Data are configured to write Data into the pixel columns, and the same sub-pixels correspond to the same pixel column.
In the embodiment of the present application, the gate driving circuit supplies the gate signals to the plurality of Scan lines Scan, and the source driver supplies the Data signals to the plurality of Data lines Data. Illustratively, the gate driving circuit is located at left and right sides of a non-display area of the display panel, and the source driver is located at upper and lower sides of the non-display area of the display panel. In the embodiment of the present application, the number of gate driving circuits is not limited.
And a line timing control circuit 100, wherein the line timing control circuit 100 is configured to sequentially turn on connection of the Scan line Scan to the odd pixel row and the even pixel row in the Scan unit.
A column timing control circuit 200, wherein the column timing control circuit 200 is configured to control the Data writing sequence of the Data line Data to the sub-pixels to be a first sub-pixel, a second sub-pixel and a third sub-pixel when the Scan line Scan scans the odd pixel row; when the scanning line Scan scans the even pixel row, the sequence of Data writing of the Data line Data into the sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
In the prior art, when performing display driving, since the pixel units in the same pixel column are electrically connected to the same Data line Data, in order to realize different display of different pixel units, it is necessary to perform time-sharing scanning on the gate lines, that is, scanning the gate lines one by one, and charging one pixel unit in a column of pixel units at a time. The higher the resolution of the display panel, the larger the display panel, and the more gate lines it has. When the display panel is driven, the scanning gate lines can only be turned on one by one, so that the progressive scanning of pixels is realized.
At high frame rate display, crosstalk is particularly severe when the product is loaded much, and NG (bad) can exist in crosstalk tests, especially in green blocks. The relationship between crosstalk and charging time is shown in fig. 2, which shows charging curves with refresh rates of 60Hz and 120Hz, and it can be seen from the figure that crosstalk can be significantly emphasized by reducing the charging time of panel.
This is due to the fact that the capacitance is generated between mutually insulated conductors, and the gate and source traces inside the TFT are mutually insulated, and thus the coupling capacitance is generated, which can only be optimized by the TFT manufacturing process, since it cannot be eliminated in the panel. In addition, a coupling capacitance part exists mainly between the Data line Data and the common voltage.
The capacitive coupling effect between the pixel electrode and the Data line Data voltage is large, when the pixel voltage instantaneously changes, the common electrode voltage can be influenced to deviate from the set potential, and the common electrode voltage can be continuously influenced due to the continuous jump change of the Data line Data voltage, so that the common electrode voltage VCOM is unstable to cause horizontal crosstalk.
At low frame rate display, the source to VCOM coupling may be slowly restored, as shown in FIG. 3 (b); at a high frame rate, however, the on time of 1-line GATE is reduced, so that the VCOM recovery thereof is worse than that at a low frame rate, as shown in (a) of fig. 3.
At present, a product containing a MUX design can control the output of a source signal through a MUX unit, and when R pixel output is needed, MUXR is turned on; when G pixel output is needed, MUXG is turned on; when a B pixel output is required, MUXB is turned on. For the progressive scanning display, when the charging time of the R/G/B sub-pixels is consistent, the VCOM recovery time is consistent, so that the VCOM coupling charging difference exists no matter the red block, the green block and the blue block are displayed. But the wavelengths of the three primary colors of RGB are different. As shown in fig. 4, the total green duty ratio is 60% or more, and the red duty ratio is about 30% and the blue duty ratio is about 10% in the white light duty ratio in the vicinity of 550 nm.
When the middle block is green, the VCOM coupling when the MUXG is turned on affects the green charging of the peripheral pixels, and since MUXR is already turned off at this time, MUXB is not yet turned on, the coupling of the middle green block to VCOM only acts on the period when the peripheral gray-scale MUXG is turned on. Similarly, when charging, VCOM coupling affects the charging of the red or blue color of the peripheral pixels.
As shown in fig. 5, assuming that the coupling voltage pair causes the gray scale voltage to be from l127→l129, when the middle block is red, the sub-pixels after the peripheral gray scale is affected are R129, G127, B127, respectively; when the middle block is green, the sub-pixels after the peripheral gray scale is affected are R127, G129 and B127 respectively; when the middle block is blue, the sub-pixels are R127, G127 and B129 after the peripheral gray scale is affected.
As can be seen from fig. 4, the effect of different coupling voltages on the gray scale display of the display panel is different. Therefore, when the peripheral gray scale is displayed, the coupling voltages RGB are uniform, but the influence of the green itself on the brightness is large, so that the gray scale variation in the green is large. When the middle block is red or blue, the coupling voltage is consistent, but the influence of red and blue on brightness is small, and the gray scale brightness change is not obvious; so only the middle block is green, crosstalk NG.
In the embodiment of the application, by controlling the driving sequence of different sub-pixel colors, controlling one scanning unit per two pixel rows, and controlling the opening sequence of the colors of the sub-pixels in one scanning unit, the coupling recovery time caused by the Data line Data when the green sub-pixels are opened is prolonged.
When the pixel rows are scanned, a scanning unit is realized for every two pixel rows through the gate driving circuit, and when the pixel rows are specifically arranged, two adjacent pixel rows in the same scanning unit are connected through the same scanning line Scan. The line sequence control circuit 100 includes a first control line gate1 for controlling the Scan line Scan to Scan the odd pixel row and a second control line gate2 for controlling the Scan line Scan to Scan the even pixel row.
The line sequence control circuit 100 includes first transistors D1 in one-to-one correspondence with the odd pixel rows and second transistors D2 in one-to-one correspondence with the even pixel rows.
The first end of the first transistor D1 is connected to the corresponding odd pixel row, the second end of the first transistor D1 is connected to the Scan line Scan corresponding to the pixel row, and the control end of the first transistor D1 is connected to the first control line gate 1.
The first end of the second transistor D2 is connected to the corresponding even pixel row, the second end of the second transistor D2 is connected to the Scan line Scan corresponding to the pixel row, and the control end of the second transistor D2 is connected to the second control line gate2.
In a scanning period in which the scanning line Scan scans one of the scanning units, the line timing control circuit 100 includes a first control signal provided to the first control line gate1 and a second control signal provided to the second control line gate2, where the first control signal includes a first active level controlling the first transistor D1 to be turned on and a first inactive level controlling the first transistor D1 to be turned off, and the second control signal includes a second active level controlling the second transistor D2 to be turned on and a second inactive level controlling the second transistor D2 to be turned off.
In the embodiment of the present application, the transistors are used to respectively correspond to the switches of the odd pixel rows and the even pixel rows, so that the two pixel rows driven simultaneously are respectively controlled. Of course, other manners of controlling the same scanning unit may also be included in the embodiments of the present application.
It can be known that, for the driving mode of the pixel rows, one end driving may be performed, two end driving may be performed, one row of pixel circuits may be performed by two ends driving, one end driving odd row of pixel circuits may be performed, the other end driving even row of pixel circuits may be performed, for the mode of driving two rows of pixel circuits in the pixel circuits simultaneously, by means of a shift register or an inverter, the change of the input/output signal sequence of the shift register and the inverter is consistent with the driving principle of the present embodiment, which is not repeated in this application.
In the embodiment of the present application, the pixel circuit unit may be a specific pixel driving circuit such as 2T1C, 3T1C, 6T1C, 7T1C, or the like. GOA (Gate Driver on Array, array substrate row driving) technology is one of the most commonly used gate driving circuit technologies in display panels at present, and the gate driving circuit is directly integrated on the array substrate of the display panel through a photolithography process. The preparation method of the gate driving circuit in the embodiment of the present application may adopt a scheme in the prior art, and this application is not repeated here.
In a specific setting, the column timing control circuit 200 includes a first gate line MUX1 for controlling the Data line Data to write Data into a pixel column where a first subpixel is located, a second gate line MUX2 for controlling the Data line Data to write Data into a pixel column where a second subpixel is located, and a third gate line MUX3 for controlling the Data line Data to write Data into a pixel column where a third subpixel is located.
The column timing control circuit 200 includes a third transistor D3 in one-to-one correspondence with the pixel column in which the first subpixel is located, a fourth transistor D4 in one-to-one correspondence with the pixel column in which the second subpixel is located, and a fifth transistor D5 in one-to-one correspondence with the pixel column in which the third subpixel is located.
A first end of the third transistor D3 is connected to a corresponding pixel column, a second section of the third transistor D3 is connected to a Data line Data corresponding to the pixel column, and a control end of the third transistor D3 is connected to the first gate line MUX 1;
the first end of the fourth transistor D4 is connected to the corresponding pixel column, the second segment of the fourth transistor D4 is connected to the Data line Data corresponding to the pixel column, and the control end of the fourth transistor D4 is connected to the second gate line MUX 2;
the first end of the fifth transistor D5 is connected to the corresponding pixel column, the second segment of the fifth transistor D5 is connected to the Data line Data corresponding to the pixel column, and the control end of the fifth transistor D5 is connected to the third gate line MUX3.
In this embodiment, the order of the sub-pixels in the order of R/G/B is taken as an example for illustration, all the pixel units in the first pixel column are R pixel units, all the pixel units in the second pixel column are G pixel units, all the pixel units in the third pixel column are B pixel units, the corresponding first gate line MUX1 is MUXR, the second gate line MUX2 is MUXG, and the third gate line MUX3 is MUXB.
In the present application, the turn-on sequence of the sub-pixels in two pixel rows in one of the scanning units is one of the following sequences:
example 1
The odd pixel rows are sequentially turned on by red/blue/green sub-pixels, and the even pixel rows are sequentially turned on by green/blue/red sub-pixels.
As shown in fig. 6, in the first line (odd line) scanning time, MUXR, MUXB, MUXG is turned on sequentially, and the second line (even line) is turned on sequentially MUXG, MUXB, MUXR, and two lines are cycled. Under the setting, MUXB becomes the condition of shortest charging time, under the red block picture, the coupling corresponding to MUXR has enough time to recover, the crosstalk OK of the red block picture; under the green picture, the coupling corresponding to MUXG has enough time to recover, and the green block picture crosstalk OK; in the blue block picture, the coupling recovery time corresponding to MUXB is the shortest, but the influence of blue on brightness is small, so that the influence on the change of gray-scale brightness is little, and the blue block picture crosstalk OK.
Example two
The odd pixel rows are sequentially turned on according to the blue/red/green sub-pixels, and the even pixel rows are sequentially turned on according to the green/red/blue sub-pixels.
As shown in fig. 7, in the first line (odd line) scanning time, MUXB, MUXR, MUXG is turned on sequentially, and the second line (even line) is turned on sequentially MUXG, MUXR, MUXB, and two lines are cycled. Under the setting, MUXR becomes the condition of shortest charging time, under the blue block picture, the coupling corresponding to MUXB has enough time to recover, blue block picture crosstalk OK; under the green picture, the coupling corresponding to MUXG has enough time to recover, and the green block picture crosstalk OK; in the red block picture, the coupling recovery time corresponding to MUXR is shortest, but the influence of red on brightness is small, so that the influence on the change of gray scale brightness is little, and the crosstalk OK of the red block picture is realized.
Example III
As shown in fig. 8, the odd pixel rows are sequentially turned on by green\red\blue sub-pixels, and the even pixel rows are sequentially turned on by blue\red\green sub-pixels.
In the first row (odd row) scan time, MUXG, MUXR, MUXB is turned on sequentially and the second row (even row) becomes MUXB, MUXR, MUXG turned on sequentially, two rows and one cycle. Under the setting, MUXR becomes the condition of shortest charging time, under the blue block picture, the coupling corresponding to MUXB has enough time to recover, blue block picture crosstalk OK; under the green picture, the coupling corresponding to MUXG has enough time to recover, and the green block picture crosstalk OK; in the red block picture, the coupling recovery time corresponding to MUXR is shortest, but the influence of red on brightness is small, so that the influence on the change of gray scale brightness is little, and the crosstalk OK of the red block picture is realized.
Example IV
The odd pixel rows are sequentially opened according to the green/blue/red sub-pixels, and the even pixel rows are sequentially opened according to the red/blue/green sub-pixels.
As shown in fig. 9, in the first line (odd line) scanning time, MUXG, MUXB, MUXR is turned on sequentially, and the second line (even line) is turned on sequentially MUXR, MUXB, MUXG, and two lines are cycled. Under the setting, MUXB becomes the condition of shortest charging time, under the red block picture, the coupling corresponding to MUXR has enough time to recover, the crosstalk OK of the red block picture; under the green picture, the coupling corresponding to MUXG has enough time to recover, and the green block picture crosstalk OK; in the blue block picture, the coupling recovery time corresponding to MUXB is the shortest, but the influence of blue on brightness is small, so that the influence on the change of gray-scale brightness is little, and the blue block picture crosstalk OK.
In various embodiments of the present application, the column timing control circuit 200 continues the active level of the third gate signal supplied to the third gate line MUX3 during a Scan period in which the Scan line Scan scans one of the Scan cells.
It should be noted that, in the embodiment of the present disclosure, the active signal (level) refers to a signal (level) for turning on the corresponding switching element, and the inactive signal (level) refers to a signal (level) for turning off the corresponding switching element. Similarly, in other embodiments of the present application, this explanation is made. The active level and the inactive level only represent that the level of the signal has 2 state quantities, and do not represent that the active level or the inactive level has a specific value throughout.
The time sequence of the effective level of the third gating signal is partially overlapped with the time sequence of the first effective level, and the time sequence of the effective level of the third gating signal is partially overlapped with the time sequence of the second effective level.
The column timing control circuit 200 supplies a first gate signal to the first gate line MUX1, the timing of the active level of the first gate signal partially coincides with the timing of the first inactive level, and the timing of the active level of the first gate signal partially coincides with the timing of the first active level.
In the embodiment of the application, the duration time of the first gating signal is connected in the scanning time of the odd-numbered row and the even-numbered row, the duration time of the third gating signal is connected in the scanning time of the odd-numbered row and the even-numbered row, the charging time of the sub-pixel corresponding to the first gating signal in the scanning unit is increased, the coupling recovery time is increased by increasing the charging time of the sub-pixel corresponding to the third gating signal in the scanning unit, and the crosstalk between pixels is reduced.
The "control terminal" refers specifically to the gate of the transistor, the "first terminal" refers specifically to the source of the transistor, and the "second terminal" refers specifically to the drain of the transistor. Of course, it will be appreciated by those skilled in the art that the "first end" and "second end" are interchangeable, i.e., the "first end" refers specifically to the drain of the transistor and the "second end" refers specifically to the source of the transistor.
The first power supply voltage terminal VDD in the embodiment of the present application, for example, holds an input dc high level signal, and the dc high level is referred to as a first voltage; the second power supply voltage terminal VSS holds, for example, an input dc low level signal, which is referred to as a second voltage, lower than the first voltage. The following embodiments are the same as this and will not be described in detail.
In addition, transistors can be classified into N-type transistors and P-type transistors according to the semiconductor characteristics of the transistors. When the transistor is used as a switching transistor, the N-type switching transistor is controlled by a high-level switching control signal to be turned on and is controlled by a low-level switching control signal to be turned off; the P-type switching transistor is controlled by a low-level switching control signal to be turned on and is controlled by a high-level switching control signal to be turned off.
The application also provides a driving method of the display panel, which is applied to the display panel as described in any one of the above, and the method comprises the following steps:
s100, scanning is performed by one scanning unit in two adjacent pixel rows through a scanning line Scan, wherein a scanning period corresponding to one scanning unit comprises an odd-line scanning stage and an even-line scanning stage.
S200, in the odd-numbered line scanning stage, the connection between the scanning line Scan and the odd-numbered pixel lines is controlled to be opened by a line sequence control circuit 100; the sequence of controlling the Data writing of the Data line Data to the sub-pixels is controlled by the column timing control circuit 200 to be a first sub-pixel, a second sub-pixel and a third sub-pixel.
S300, in the even line scanning stage, the connection between the scanning line Scan and the even pixel lines is controlled to be opened by the line sequence control circuit 100; the Data writing sequence of the Data line Data to the sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
In a third aspect, the present application provides a display device comprising a display panel as described in any one of the above.
The invention is not particularly limited in application to display devices, and can be any product or component with display function, such as televisions, notebook computers, tablet computers, wearable display equipment, mobile phones, vehicle-mounted display, navigation, electronic books, digital photo frames, advertisement lamp boxes and the like.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the invention. Terms such as "disposed" or the like as used herein may refer to either one element being directly attached to another element or one element being attached to another element through an intermediate member. Features described herein in one embodiment may be applied to another embodiment alone or in combination with other features unless the features are not applicable or otherwise indicated in the other embodiment.
The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. Those skilled in the art will appreciate that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed.
Claims (13)
1. A display panel, comprising:
the pixel units are arranged in an array manner, form a plurality of pixel rows which are arrayed along a first direction and a plurality of pixel columns which are arrayed along a second direction, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel which are sequentially arranged along the row direction, and further comprises a plurality of time sequence control lines and a plurality of gating control lines;
a plurality of scanning lines configured to scan with one scanning unit in two adjacent pixel rows, one of the scanning units including an odd pixel row and a next even pixel row adjacent to the odd pixel row;
the data lines are configured to write data into the pixel columns, and the same sub-pixels correspond to the same pixel column;
a row timing control circuit configured to sequentially turn on connection of the scanning lines with the odd-numbered pixel rows and the even-numbered pixel rows in the scanning unit;
a column timing control circuit configured to control an order of data writing of the data lines to the sub-pixels to be a first sub-pixel, a second sub-pixel, and a third sub-pixel when the scanning line scans the odd-numbered pixel row; when the scanning line scans the even pixel rows, the data writing sequence of the data line to the sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
2. The display panel according to claim 1, wherein the line timing control circuit includes a first control line that controls the scanning line to scan an odd pixel row and a second control line that controls the scanning line to scan an even pixel row.
3. The display panel of claim 2, wherein the row timing control circuit comprises first transistors in one-to-one correspondence with the odd pixel rows and second transistors in one-to-one correspondence with the even pixel rows, wherein,
the first end of the first transistor is connected with the corresponding odd pixel row, the second end of the first transistor is connected with the scanning line corresponding to the pixel row, and the control end of the first transistor is connected with the first control line;
the first end of the second transistor is connected with the corresponding even pixel row, the second end of the second transistor is connected with the scanning line corresponding to the pixel row, and the control end of the second transistor is connected with the second control line.
4. The display panel according to claim 1, wherein the column timing control circuit includes a first gate line that controls the data line to write data to a pixel column where a first subpixel is located, a second gate line that controls the data line to write data to a pixel column where a second subpixel is located, and a third gate line that controls the data line to write data to a pixel column where a third subpixel is located.
5. The display panel of claim 4, wherein the column timing control circuit includes a third transistor in one-to-one correspondence with a pixel column in which the first subpixel is located, a fourth transistor in one-to-one correspondence with a pixel column in which the second subpixel is located, and a fifth transistor in one-to-one correspondence with a pixel column in which the third subpixel is located,
the first end of the third transistor is connected with the corresponding pixel column, the second end of the third transistor is connected with the data line corresponding to the pixel column, and the control end of the third transistor is connected with the first gating line;
the first end of the fourth transistor is connected with the corresponding pixel column, the second section of the fourth transistor is connected with the data line corresponding to the pixel column, and the control end of the fourth transistor is connected with the second gating line;
the first end of the fifth transistor is connected with the corresponding pixel column, the second section of the fifth transistor is connected with the data line corresponding to the pixel column, and the control end of the fifth transistor is connected with the third gating line.
6. The display panel of claim 1, wherein the sub-pixels in two pixel rows in one of the scan cells are turned on in one of the following orders:
the odd pixel rows are sequentially opened according to red/blue/green sub-pixels, and the even pixel rows are sequentially opened according to green/blue/red sub-pixels;
the odd pixel rows are sequentially opened according to the blue/red/green sub-pixels, and the even pixel rows are sequentially opened according to the green/red/blue sub-pixels;
the odd pixel rows are sequentially opened according to green\red\blue sub-pixels, and the even pixel rows are sequentially opened according to blue\red\green sub-pixels; a kind of electronic device with high-pressure air-conditioning system
The odd pixel rows are sequentially opened according to the green/blue/red sub-pixels, and the even pixel rows are sequentially opened according to the red/blue/green sub-pixels.
7. The display panel according to claim 3, wherein the line timing control circuit includes a first control signal supplied to the first control line and a second control signal supplied to the second control line during a scan period in which the scan line scans one of the scan cells, wherein the first control signal includes a first active level controlling the first transistor to be turned on and a first inactive level controlling the first transistor to be turned off, and the second control signal includes a second active level controlling the second transistor to be turned on and a second inactive level controlling the second transistor to be turned off.
8. The display panel according to claim 7, wherein the column timing control circuit continues an active level of a third gate signal supplied to a third gate line during a scanning period in which one of the scanning units is scanned by the scanning line.
9. The display panel according to claim 8, wherein a timing of the active level of the third gate signal partially coincides with a timing of the first active level, and a timing of the active level of the third gate signal partially coincides with a timing of the second active level.
10. The display panel according to claim 7, wherein the column timing control circuit supplies a first gate signal to a first gate line, a timing of an active level of the first gate signal partially coincides with a timing of the first inactive level, and a timing of an active level of the first gate signal partially coincides with a timing of the first active level.
11. The display panel of claim 1, wherein two adjacent rows of pixels in a same scanning unit are connected by a same scanning line.
12. A driving method of a display panel, characterized in that it is applied to the display panel according to any one of claims 1 to 11, the method comprising:
scanning is performed by the scanning line in one scanning unit in two adjacent pixel rows, wherein the scanning period corresponding to one scanning unit comprises an odd line scanning stage and an even line scanning stage,
in the odd-numbered line scanning stage, the connection between the scanning line and the odd-numbered pixel line is controlled and started by a line time control circuit; the sequence of controlling the data writing of the data line sub-pixels is controlled to be a first sub-pixel, a second sub-pixel and a third sub-pixel through a column time sequence control circuit;
in the even line scanning stage, the connection between the scanning line and the even pixel line is controlled to be started through a time sequence control circuit; the data writing sequence of the data line sub-pixels is controlled to be a third sub-pixel, a second sub-pixel and a first sub-pixel; wherein,
the sub-pixels comprise a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the green sub-pixel is an optional first sub-pixel or third sub-pixel.
13. A display device comprising a display panel as claimed in any one of claims 1-11.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103578422A (en) * | 2012-07-31 | 2014-02-12 | 索尼公司 | Display device and electronic apparatus, and driving method of display panel |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| CN110136630A (en) * | 2019-06-18 | 2019-08-16 | 京东方科技集团股份有限公司 | A kind of display panel and its driving method, display device |
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| CN105511184B (en) * | 2016-01-13 | 2019-04-02 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and its driving method |
| US10748495B2 (en) * | 2018-04-12 | 2020-08-18 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Pixel driving circuit and liquid crystal display circuit with the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103578422A (en) * | 2012-07-31 | 2014-02-12 | 索尼公司 | Display device and electronic apparatus, and driving method of display panel |
| CN106292096A (en) * | 2016-10-13 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of De mux liquid crystal display and driving method thereof |
| CN110136630A (en) * | 2019-06-18 | 2019-08-16 | 京东方科技集团股份有限公司 | A kind of display panel and its driving method, display device |
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