CN110136630A - A kind of display panel and its driving method, display device - Google Patents
A kind of display panel and its driving method, display device Download PDFInfo
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- CN110136630A CN110136630A CN201910527748.XA CN201910527748A CN110136630A CN 110136630 A CN110136630 A CN 110136630A CN 201910527748 A CN201910527748 A CN 201910527748A CN 110136630 A CN110136630 A CN 110136630A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
Abstract
A kind of display panel and its driving method, display device, wherein, display panel includes: that M row N column pixel unit, M+1 horizontal scanning line, N column data line, multiplexer circuit and source electrode drive circuit, the i-th row pixel unit are connect with the i-th horizontal scanning line and i+1 horizontal scanning line respectively；Jth column pixel unit is connect with jth column data line, 1≤i≤M, 1≤j≤N, multiplexer circuit, it is connect respectively with selection control terminal, source electrode drive circuit and N column data line, for under the control of selection control terminal, the data-signal timesharing that source electrode drive circuit exports to be input in corresponding data line.Every row pixel unit is connect with two horizontal scanning lines in technical solution provided by the present application, by the difference of the charge rate with the use of the pixel unit that can reduce different lines of multiple selector, to avoid vertical line is generated, and then improves the display effect of display panel.
Description
Technical field
Present document relates to field of display technology, and in particular to a kind of display panel and its driving method, display device.
Background technique
With the continuous development of display technology, it for showing that the display panel of picture is also varied, and can show
Colourful picture.Specifically, display panel includes: the scan line and data line, gate driving of pixel unit, transverse and longitudinal intersection
Circuit and source electrode drive circuit, source electrode drive circuit be used for data line provide data-signal, gate driving circuit be used for by
Row scanning scan line, to provide data-signal, the final normal display for realizing image to pixel unit, wherein source drive electricity
Road includes: multiple source driving chips.
In order to realize the narrow frame of display panel, display panel in the related technology is all made of multichannel multiplexing technology, i.e.,
Each source driving chip in display panel is all connected at least two column data lines, through inventor the study found that using multichannel
The charge rate of the pixel unit of the different lines of the display panel of multiplexing technology has differences, and then can generate vertical line, affects aobvious
Show the display effect of panel.
Summary of the invention
This application provides a kind of display panel and its driving methods, display device, can reduce the pixel list of different lines
The difference of the charge rate of member to avoid vertical line is generated, and then improves the display effect of display panel.
In a first aspect, this application provides a kind of display panels, comprising: M row N column pixel unit, M+1 horizontal scanning line, N column
Data line, multiplexer circuit and source electrode drive circuit；
I-th row pixel unit, connect with the i-th horizontal scanning line and i+1 horizontal scanning line respectively；Jth column pixel unit and jth
Column data line connection, 1≤i≤M, 1≤j≤N；
The multiplexer circuit connect with selection control terminal, source electrode drive circuit and N column data line respectively, is used for
Under the control for selecting control terminal, the data-signal timesharing that source electrode drive circuit exports is input in corresponding data line.
Optionally, for the i-th row jth column pixel unit, as j=4k+1 or 4k+2, the i-th row jth column pixel unit with
The connection of i-th horizontal scanning line；
As j=4k+3 or 4k+4, the i-th row jth column pixel unit is connect with i+1 horizontal scanning line, 0≤k < N/4.
Optionally, s horizontal scanning line includes: the first sub- scan line and the second sub- scan line, 1 < s≤M；
First sub- scan line of the s horizontal scanning line is connect with s-1 row t1 column pixel unit, wherein t1=4k+
3 or 4k+4,0≤k < N/4；
Second sub- scan line of the s horizontal scanning line is connect with s row t2 column pixel unit, wherein t2=4k+1
Or 4k+2；
First horizontal scanning line is connect with the first row t2 column pixel unit, M+1 horizontal scanning line and M row t1 column pixel
Unit connection.
Optionally, for the i-th row jth column pixel unit, the pixel unit includes: display element and switch element, institute
Stating switch element includes: the first transistor；
As j=4k+1 or 4k+2, the control electrode of the first transistor is connect with the i-th horizontal scanning line, and the of the first transistor
One pole is connect with jth column data line, and the second pole of the first transistor is connect with display element；
As j=4k+3 or 4k+4, the control electrode of the first transistor is connect with i+1 horizontal scanning line, the first transistor
First pole is connect with jth column data line, and the second pole of the first transistor is connect with display element.
Optionally, the source electrode drive circuit includes: P source drive unit, and the multiplexer circuit includes: Q
Selection circuit, the selection control terminal include: Q selection control terminal, select control terminal and selection circuit to correspond, wherein P
× Q=N；
I-th of selection circuit, respectively with corresponding selection control terminal, P source drive unit, 2Qk+2i-1 column data
Line and the connection of 2Qk+2i column data line, wherein 1≤i≤Q, 0≤k < N/2Q.
Optionally, i-th of selection circuit includes: P i+1 transistor；
The selection control terminal connection corresponding with i-th of selection circuit of the control electrode of j-th of i+1 transistor, j-th i-th+
First pole of 1 transistor is connect with j-th of source drive unit；
When j is even number, the second pole of j-th of i+1 transistor is connect with (j-2) Q+2i column data line, when j is surprise
Number, the second pole of j-th of i+1 transistor are connect with (j-1) Q+2i-1 column data line, 1≤j≤P.
Optionally, electric signal on adjacent multiple data lines puts in order successively according to positive polarity, negative polarity
Arrangement.
Optionally, the multiplexer circuit and the source electrode drive circuit are located at the non-display area of the display panel
Domain.
Second aspect, the embodiment of the present application also provide a kind of display device, comprising: above-mentioned display panel.
The third aspect, the embodiment of the present application also provide a kind of driving method of display panel, for driving above-mentioned display surface
Plate, which comprises
Under the control of selection control terminal, the data-signal timesharing that multiplexer circuit exports source electrode drive circuit is inputted
Into corresponding data line.
This application provides a kind of display panel and its driving methods, display device, wherein display panel includes: M row N
Column pixel unit, M+1 horizontal scanning line, N column data line, multiplexer circuit and source electrode drive circuit, the i-th row pixel unit, point
It is not connect with the i-th horizontal scanning line and i+1 horizontal scanning line；Jth column pixel unit is connect with jth column data line, 1≤i≤M, 1≤
J≤N, multiplexer circuit are connect with selection control terminal, source electrode drive circuit and N column data line respectively, for controlling in selection
Under the control at end, the data-signal timesharing that source electrode drive circuit exports is input in corresponding data line.It is provided by the present application
Every row pixel unit is connect with two horizontal scanning lines in technical solution, can reduce different lines by being used cooperatively for multiple selector
The difference of charge rate of pixel unit and then improve the display effect of display panel to avoid vertical line is generated.
Other features and advantage will illustrate in the following description, also, partly become from specification
It obtains it is clear that being understood and implementing the application.Other advantages of the application can be by specification, claims
And scheme described in attached drawing is achieved and obtained.
Detailed description of the invention
Attached drawing is used to provide the understanding to technical scheme, and constitutes part of specification, with the application's
Embodiment is used to explain the technical solution of the application together, does not constitute the limitation to technical scheme.
Fig. 1 is the structural schematic diagram of display panel in the related technology；
Fig. 2 is the working timing figure for the display panel that Fig. 1 is provided；
Fig. 3 is the structural schematic diagram one of display panel provided by the embodiments of the present application；
Fig. 4 is the structural schematic diagram two of display panel provided by the embodiments of the present application
Fig. 5 is the equivalent circuit diagram one of display panel provided by the embodiments of the present application；
Fig. 6 is the equivalent circuit diagram two of display panel provided by the embodiments of the present application；
Fig. 7 is the equivalent circuit diagram three of display panel provided by the embodiments of the present application；
Fig. 8 is the working timing figure for the display panel that Fig. 5 is provided；
Fig. 9 is the working timing figure for the display panel that Fig. 6 is provided.
Specific embodiment
This application describes multiple embodiments, but the description is exemplary, rather than restrictive, and for this
It is readily apparent that can have more in the range of embodiments described herein includes for the those of ordinary skill in field
More embodiments and implementation.Although many possible feature combinations are shown in the attached drawings, and in a specific embodiment
It is discussed, but many other combinations of disclosed feature are also possible.Unless the feelings specially limited
Other than condition, any feature or element of any embodiment can be with any other features or element knot in any other embodiment
It closes and uses, or any other feature or the element in any other embodiment can be substituted.
The application includes and contemplates the combination with feature known to persons of ordinary skill in the art and element.The application is
It can also combine with any general characteristics or element through disclosed embodiment, feature and element, be defined by the claims with being formed
Unique scheme of the invention.Any feature or element of any embodiment can also be with features or member from other scheme of the invention
Part combination, to form the unique scheme of the invention that another is defined by the claims.It will thus be appreciated that showing in this application
Out and/or any feature of discussion can be realized individually or in any suitable combination.Therefore, in addition to according to appended right
It is required that and its other than the limitation done of equivalent replacement, embodiment is not limited.Furthermore, it is possible in the guarantor of appended claims
It carry out various modifications and changes in shield range.
In addition, method and/or process may be rendered as spy by specification when describing representative embodiment
Fixed step sequence.However, in the degree of this method or process independent of the particular order of step described herein, this method
Or process should not necessarily be limited by the step of particular order.As one of ordinary skill in the art will appreciate, other steps is suitable
Sequence is also possible.Therefore, the particular order of step described in specification is not necessarily to be construed as limitations on claims.This
Outside, the claim for this method and/or process should not necessarily be limited by the step of executing them in the order written, art technology
Personnel are it can be readily appreciated that these can sequentially change, and still remain in the spirit and scope of the embodiment of the present application.
Unless otherwise defined, the embodiment of the present invention discloses the technical term used or scientific term should be institute of the present invention
The ordinary meaning that personage in category field with general technical ability is understood." first ", " second " used in the embodiment of the present invention
And similar word is not offered as any sequence, quantity or importance, and be used only to distinguish different component parts.
The similar word such as " comprising " or "comprising", which means to occur element or object before the word, to be covered to appear in and arranges behind the word
The element of act perhaps object and its equivalent and be not excluded for other elements or object.The similar word such as " connection " or " connected "
Language is not limited to physics or mechanical connection, but may include electrical connection, either direct or indirect
's.
It will be understood by those skilled in the art that all transistors used in the examples of the application all can be film crystal
Pipe or field-effect tube or the identical device of other characteristics.Preferably, thin film transistor (TFT) used in the embodiment of the present invention can be
Oxide semi conductor transistor.Since the source electrode of the transistor used here, drain electrode are symmetrical, so its source electrode, drain electrode can
To exchange.In embodiments of the present invention, to distinguish the two poles of the earth in addition to grid of switching transistor, one of electrode is known as the
One pole, another electrode are known as the second pole, and first extremely can be source electrode or drain electrode, and second can be extremely drain electrode or source electrode.
Fig. 1 is the structural schematic diagram of display panel in the related technology, as shown in Figure 1, display panel in the related technology
In include: array setting pixel unit 11, scan line Gate, data line Data, the first multiple selector 12 and the second multichannel
Selector 13 and multiple source drive cell Ss.
Wherein, the first multiple selector 12 is connect with first choice control terminal MUX1, the second multiple selector 13 and second
Select control terminal MUX2 connection, it should be noted that each source drive unit is connect with two column data lines in Fig. 1, with first
For a source drive unit, first source drive cell S 1 is provided by the first multiple selector 12 to red sub-pixel R
Data-signal provides data-signal to blue subpixels B by the second multiple selector 13.
Fig. 2 is the working timing figure for the display panel that Fig. 1 is provided, combined with Figure 1 and Figure 2, to show the first row first four picture
For plain unit, wherein include: two red sub-pixels in four pixel units, will be close to the sub- picture of red of green sub-pixels
Element becomes the first red sub-pixel, another is known as the second red sub-pixel, specifically, the work of display panel in the related technology
Include: as process
First stage t1, first choice control terminal MUX1 provide significant level, and the first scan line Gate1 provides effectively electricity
Flat, first source drive cell S 1 gives green sub-pixels to first red sub-pixel charging, the second source drive cell S 2
Charging.
Second stage t2, first choice control terminal MUX1 provide inactive level, first source drive cell S 1 stop to
First red sub-pixel charging, the second source drive cell S 2 stop green sub-pixels charging, at this point, the first red sub-pixel and
Green sub-pixels are influenced by first choice control terminal MUX1 deposit capacitor, and pixel voltage is pulled, and decline △ V1, at this point,
Second selection control terminal MUX2 provides significant level, and first source drive cell S 1 charges to blue subpixels, the second source electrode
Driving unit S2 charges to the second red sub-pixel.
After second stage t2, the second selection control terminal MUX2 provides inactive level, and the first scan line Gate1 provides nothing
Level is imitated, the first red sub-pixel and green sub-pixels are influenced by the first scan line Gate1 deposit capacitor again, pixel voltage
It is pulled for the second time, declines △ V2 again, and blue subpixels and the second red sub-pixel are only posted by the first scan line Gate1
The influence of capacitor is deposited, pixel voltage is pulled primary, decline △ V3.Due to △ V1+ △ V2 ≠ △ V3, the first red son
Pixel is different with the pixel voltage of blue subpixels, so that the first red sub-pixel and the charge rate of blue subpixels are
Difference, macroscopically performance is the difference of light levels, causes the vertical line under grayscale, can see that flashing under serious situation
Light and shade vertical line, affect the display effect of display panel.
In order to solve the above-mentioned technical problem, the embodiment of the present application provides a kind of display panel and its driving method, display
Device is described as follows:
The some embodiments of the application provide a kind of display panel, and Fig. 3 is the knot of display panel provided by the embodiments of the present application
Structure schematic diagram one, as shown in figure 3, display panel provided by the embodiments of the present application includes: that M row N column pixel unit 10, M+1 row are swept
Retouch line G1~GM+1, N column data line D1~DN, multiplexer circuit and source electrode drive circuit.
Specifically, the i-th row pixel unit, connect with the i-th horizontal scanning line Gi and i+1 horizontal scanning line Gi+1 respectively；Jth column
Pixel unit is connect with jth column data line Dj, 1≤i≤M, 1≤j≤N, multiplexer circuit, respectively with selection control terminal MUX,
Source electrode drive circuit is connected with N column data line D1~DN, for selection control terminal MUX control under, by source electrode drive circuit
The data-signal timesharing of output is input in corresponding data line.
Specifically, the first row pixel unit, connect with the first horizontal scanning line G1 and the second horizontal scanning line G2, the second row respectively
Pixel unit is connect with the second horizontal scanning line G2 and third horizontal scanning line G3 respectively, and so on, first row pixel unit and
One column data line D1 connection, secondary series pixel unit are connect with the second column data line D2, and so on.It should be noted that M and
N is the positive integer more than or equal to 1, and the application is not limited in any way this, is limited with specific reference to actual demand.
In the embodiment of the present application, display panel includes: display area and non-display area, scan line, data line and pixel
Unit is located at display area, and multiplexer circuit and source electrode drive circuit are located at the non-display area of display panel.
Specifically, the pixel unit in the embodiment of the present application is sub-pixel, sub-pixel includes: red sub-pixel R, blue
Pixel B or green sub-pixels G.
Display panel provided by the embodiments of the present application can use low-temperature polysilicon silicon technology (Low Temperature
Poly-silicon, abbreviation LTPS) processing procedure or oxide process.
Specifically, multiplexer circuit includes: multiple signal input parts and multiple signal output ends, wherein multiple signals
Input terminal is connect with source electrode drive circuit, and the number of signal input part is less than the number of signal output end, by display surface
Multiplexer circuit is arranged in plate can reduce the size of source electrode drive circuit, and then can be realized the narrow frame of display panel.
Display panel provided by the embodiments of the present application include: M row N column pixel unit, M+1 horizontal scanning line, N column data line,
Multiplexer circuit and source electrode drive circuit, the i-th row pixel unit connect with the i-th horizontal scanning line and i+1 horizontal scanning line respectively
It connects；Jth column pixel unit is connect with jth column data line, 1≤i≤M, 1≤j≤N, multiplexer circuit, is controlled respectively with selection
End, source electrode drive circuit are connected with N column data line, under the control of selection control terminal, source electrode drive circuit to be exported
Data-signal timesharing is input in corresponding data line.Every row pixel unit and two rows scan in technical solution provided by the present application
Line connection, by multiple selector with the use of the difference of the charge rate for the pixel unit that can reduce different lines, to avoid
Vertical line is generated, and then improves the display effect of display panel.
Optionally, as shown in figure 3, for the i-th row jth column pixel unit, as j=4k+1 or 4k+2, the i-th row jth column
Pixel unit is connect with the i-th horizontal scanning line Gi, and as j=4k+3 or 4k+4, the i-th row jth column pixel unit and i+1 row are scanned
Line Gi+1 connection, 0≤k < N/4.
Specifically, the first row first row pixel unit is connect with the first horizontal scanning line G1, the first row secondary series pixel unit
It is connect with the first horizontal scanning line G2, the first row third column pixel unit is connect with the second horizontal scanning line G2, the 4th column picture of the second row
Plain unit is connect with the second horizontal scanning line G2, and so on, the embodiment of the present application is not limited in any way this.It needs to illustrate
It is that every horizontal scanning line in Fig. 3 is a signal wire.
Optionally, Fig. 4 is the structural schematic diagram two of display panel provided by the embodiments of the present application, as shown in figure 4, s row
Scan line Gs includes: the first sub- sub- scan line Gs2 of scan line Gs1 and second, 1 < s≤M.
Specifically, the first sub- scan line Gs1 of s horizontal scanning line Gs is connect with s-1 row t1 column pixel unit,
In, t1=4k+3 or 4k+4, the sub- scan line Gs2 of the second of s horizontal scanning line Gs are connect with s row t2 column pixel unit,
In, t2=4k+1 or 4k+2, the first horizontal scanning line G1 are connect with the first row t2 column pixel unit, M+1 horizontal scanning line and M
The connection of row t1 column pixel unit.
Specifically, as shown in figure 4, the second horizontal scanning line G2 includes: the first sub- sub- scan line G22 of scan line G21 and second,
The sub- scan line G21 of the first of second horizontal scanning line G2 and the first row third column pixel unit, the 4th column pixel unit of the first row, the
The connection such as the 7th column pixel unit of a line, the 8th column pixel unit of the first row, the sub- scan line G22 of the second of the second horizontal scanning line G2
It is arranged with the second row first row pixel unit, the second row secondary series pixel unit, the 5th column pixel unit of the second row, the second row the 6th
The connection such as pixel unit, third horizontal scanning line G3 include: the first sub- sub- scan line G32 of scan line G31 and second, the third line scanning
The sub- scan line G31 of the first of line G3 and the second row third column pixel unit, the 4th column pixel unit of the second row, the second row the 7th arrange
The connection such as pixel unit, the 8th column pixel unit of the second row, the sub- scan line G32 of the second of third horizontal scanning line G3 and the third line the
One column pixel unit, the third line secondary series pixel unit, the 5th column pixel unit of the third line, the 6th column pixel unit of the third line etc.
Connection, and so on.It should be noted that the first horizontal scanning line and M+1 horizontal scanning line in Fig. 4 are a signal wire, remove
Scan line except first horizontal scanning line and M+1 horizontal scanning line includes two signal wires.
Optionally, as shown in Figures 3 and 4, for the i-th row jth column pixel unit, pixel unit 10 includes: display element 20
And switch element.
Specifically, switch element includes: the first transistor M1.
As j=4k+1 or 4k+2, the control electrode of the first transistor M1 is connect with the i-th horizontal scanning line Gi, the first transistor
The first pole of M1 is connect with jth column data line Dj, and the second pole of the first transistor M1 is connect with display element 20；Work as j=4k+3
Or when 4k+4, the control electrode of the first transistor M1 is connect with i+1 horizontal scanning line Gi+1, the first pole of the first transistor M1 and the
The Dj connection of j column data line, the second pole of the first transistor M1 are connect with display element 20.
As shown in Figure 3 and Figure 4, technical solution provided by the embodiments of the present application is by the switch element in every row pixel unit
Connection type, so that the switch element in every row pixel unit is according to the inverted structural arrangement of Z-type.
Optionally, the electric signal on adjacent multiple data lines is arranged successively according to positive polarity, putting in order for negative polarity.
Optionally, Fig. 5 is the equivalent circuit diagram one of display panel provided by the embodiments of the present application, and Fig. 6 is the application implementation
The equivalent circuit diagram two for the display panel that example provides, Fig. 7 are the equivalent circuit diagram three of display panel provided by the embodiments of the present application,
As shown in Fig. 5, Fig. 6 and Fig. 7, source electrode drive circuit provided by the embodiments of the present application includes: P source drive 1~SP of cell S,
Multiplexer circuit includes: Q selection circuit, and selecting control terminal MUX includes: Q selection control terminal MUX1~MUXQ, selection control
End processed and selection circuit correspond, wherein P × Q=N.
Specifically, i-th of selection circuit, respectively with corresponding selection control terminal MUXi, P source drive cell S 1~
SP, 2Qk+2i-1 column data line and 2Qk+2i column data line, wherein 1≤i≤Q, 0≤k < N/2Q.
Optionally, i-th of selection circuit includes: P i+1 transistor Mi+1.
Specifically, the control electrode of j-th of i+1 transistor Mi+1 selection control terminal corresponding with i-th of selection circuit
MUXi connection, the first pole of j-th of i+1 transistor Mi+1 are connect with j-th of source drive cell S j；When j is even number, jth
The second pole of a i+1 transistor Mi+1 is connect with (j-2) Q+2i column data line, when j is odd number, j-th of i+1 transistor
The second pole connect with (j-1) Q+2i-1 column data line, 1≤j≤P.
It should be noted that Fig. 5 and Fig. 6 are illustrated by taking Q=2 as an example, the embodiment of the present application does not make this any
It limits.Specifically, multiplexer circuit includes: first selection circuit and the second selection circuit.
Wherein, first choice circuit includes: P second transistor M2, the control electrode of first second transistor M2 and the
One selection control terminal MUX1 connection, the first pole are connect with first source drive cell S 1, the second pole and the first columns
According to line D1 connection, the control electrode of second second transistor M2 is connect with first selection control terminal MUX1, the first pole and the
Two source drive cell Ss 2 connect, and the second pole is connect with the second column data line D2, the control of third second transistor M2
Pole is connect with first selection control terminal MUX1, and the first pole is connect with third source drive cell S 3, the second pole and the
Five column data line D5 connections, and so on.
Wherein, the second selection circuit includes: P third transistor M3, the control electrode of first third transistor M3 and the
Two selection control terminal MUX2 connections, the first pole are connect with first source drive cell S 1, the second pole and third columns
According to line D3 connection, the control electrode of second third transistor M3 is connect with second selection control terminal MUX2, the first pole and the
Two source drive cell Ss 2 connect, and the second pole is connect with the 4th column data line D4, the control of third third transistor M3
Pole is connect with second selection control terminal MUX2, and the first pole is connect with third source drive cell S 3, the second pole and the
Seven column data line D7 connections, and so on.
It should be noted that Fig. 7 is illustrated by taking Q=3 as an example, the embodiment of the present application is not limited in any way this.
Specifically, multiplexer circuit includes: first selection circuit, the second selection circuit and third selection circuit.
Wherein, first choice circuit includes: P second transistor M2, the control electrode of first second transistor M2 and the
One selection control terminal MUX1 connection, the first pole are connect with first source drive cell S 1, the second pole and the first columns
According to line D1 connection, the control electrode of second second transistor M2 is connect with first selection control terminal MUX1, the first pole and the
Two source drive cell Ss 2 connect, and the second pole is connect with the second column data line D2, the control of third second transistor M2
Pole is connect with first selection control terminal MUX1, and the first pole is connect with third source drive cell S 3, the second pole and the
Seven column data line D7 connections, and so on.
Wherein, the second selection circuit includes: P third transistor M3, the control electrode of first third transistor M3 and the
Two selection control terminal MUX2 connections, the first pole are connect with first source drive cell S 1, the second pole and third columns
According to line D3 connection, the control electrode of second third transistor M3 is connect with second selection control terminal MUX2, the first pole and the
Two source drive cell Ss 2 connect, and the second pole is connect with the 4th column data line D4, the control of third third transistor M3
Pole is connect with second selection control terminal MUX2, and the first pole is connect with third source drive cell S 3, the second pole and the
Nine column data line D9 connections, and so on.
Wherein, third selection circuit includes: P the 4th transistor M4, the control electrode of first the 4th transistor M4 and the
Three selection control terminal MUX3 connections, the first pole are connect with first source drive cell S 1, the second pole and the 5th columns
According to line D5 connection, the control electrode of second the 4th transistor M4 connect with third selection control terminal MUX3, the first pole and the
Two source drive cell Ss 2 connect, and the second pole is connect with the 6th column data line D6, the control of the 4th transistor M4 of third
Pole and third selection control terminal MUX3 connects, and the first pole is connect with third source drive cell S 3, the second pole and the
11 column data line D11 connections, and so on.
In the present embodiment, transistor M1~MQ+1 all can be N-type TFT or P-type TFT, can be with
Unified process flow, can reduce manufacturing process, help to improve the yield of product.In addition, it is contemplated that low-temperature polysilicon film
The leakage current of transistor is smaller, and therefore, preferably all transistors of the embodiment of the present application are low-temperature polysilicon film transistor, film
Transistor specifically can choose the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure, as long as can be realized out
Close function.
The technical solution of the embodiment of the present application is further illustrated below by the course of work of display panel.
By taking transistor M1~M3 in the display panel that Fig. 5 is provided is N-type TFT as an example, Fig. 8 provides for Fig. 5
Display panel working timing figure, as shown in Figure 5 and Figure 8, the course of work of display panel provided by the embodiments of the present application has
Body includes:
A frame time is defined as T now, includes: first stage T1 and second stage T2, tool within the time of upper field
Body:
First stage T1, first selects the input signal of control terminal MUX1 for high level, and all second transistor M2 are led
Logical, the input signal of the first scan line G1 is high level, and first in all pixels unit connecting with the first scan line G1 is brilliant
Body pipe M1 conducting, at this point, first source drive cell S 1 charges to the red sub-pixel of the first row first row, second source electrode
Driving unit S2 charges to the green sub-pixels of the first row secondary series, and third source drive cell S 3 is arranged to the first row the 5th
Green sub-pixels charging, and so on.
Second stage T2, first selects the input signal of control terminal MUX1 for low level, and all second transistor M2 are cut
Only, the input signal of the first scan line G1 is low level, the first transistor in pixel unit connecting with the first scan line G1
M1 cut-off, first source drive cell S 1 stop charging to the red sub-pixel of the first row first row, second source drive
Cell S 2 stops charging to the green sub-pixels of the first row secondary series, and third source drive cell S 3 stops to the first row the 5th
The green sub-pixels of column charge, and so on, at this point, realizing that the pixel unit of charging will receive first in upper stage T1
The coupling influence of control terminal MUX1 and the first scan line G1 deposit capacitor is selected, pixel voltage can decline.Meanwhile second choosing
The input signal for selecting control terminal MUX2 is high level, all third transistor M3 conductings, the input signal of the second horizontal scanning line G2
For high level, first source drive cell S 1 charges to the tertial blue subpixels of the first row, second source drive list
The red sub-pixel charging that first S2 is arranged to the first row the 4th, red that third source drive cell S 3 is arranged to the first row the 7th
Pixel charging, and so on, at this point, the first row pixel unit is lit entirely.
After second stage T2, second selects the input signal of control terminal MUX2 for low level, the second scan line G2
Input signal be low level, the first transistor M1 in pixel unit connect with the second scan line G2 ends, first source
Pole driving unit S1 stops to the tertial blue subpixels charging of the first row, and second source drive cell S 2 stops to first
The red sub-pixel charging that row the 4th arranges, third source drive cell S 3 stop filling to the red sub-pixel that the first row the 7th arranges
Electricity, and so on, at this point, realizing that the pixel unit of charging will receive second selection control terminal MUX2 and the in second stage T2
Two scan line G2 deposit the coupling influence of capacitor, and pixel voltage can decline.
Then similar with first stage T1 and second stage T2, successive scanning third scan line G3 and the 4th scan line G4,
At this point, the third line pixel unit is lit, and so on, until upper half frame time, that is, T/2 terminates, at this point, entire screen is presented
The state that the bright even rows unit of odd-line pixels unit does not work, wherein.
When lower field, that is, T/2 starts, comprising: phase III T3, fourth stage T4 and the 5th stage T5, specific:
The input signal of phase III T3, first selection control terminal MUX1 and second selection control terminal MUX2 are low
Level, second transistor M2 and third transistor M3 cut-off, the input signal of the first scan line G1 are high level, with the first scanning
The first transistor M1 conducting in the pixel unit of line G1 connection.
Fourth stage T4, first selects the input signal of control terminal MUX1 for high level, second transistor M2 conducting, the
The input signal of two horizontal scanning line G2 is high level, at this point, red of first source drive cell S 1 to the second row first row
Sub-pixel charging, second source drive cell S 2 charge to the green sub-pixels of the second row secondary series, third source drive
The green sub-pixels charging that cell S 3 is arranged to the second row the 5th, and so on.
5th stage T5, first selects the input signal of control terminal MUX1 for low level, and all second transistor M2 are cut
Only, the input signal of the second scan line G2 is low level, the first transistor in pixel unit connecting with the second scan line G2
M1 cut-off, first source drive cell S 1 stop charging to the red sub-pixel of the second row first row, second source drive
Cell S 2 stops charging to the green sub-pixels of the second row secondary series, and third source drive cell S 3 stops to the second row the 5th
The green sub-pixels of column charge, and so on, at this point, realizing that the pixel unit of charging will receive first in upper stage T3
The coupling influence of control terminal MUX1 and the second scan line G2 deposit capacitor is selected, pixel voltage can decline.Meanwhile the third line is swept
The input signal for retouching line G3 is high level, and first source drive cell S 1 charges to the tertial blue subpixels of the second row,
The red sub-pixel charging that second source drive cell S 2 is arranged to the second row the 4th, third source drive cell S 3 to second
The red sub-pixel charging that row the 7th arranges, and so on, and so on, the second row pixel unit is lit entirely.
After the 5th stage T5, second selects the input signal of control terminal MUX2 for low level, third horizontal scanning line
The input signal of G3 is low level, the first transistor M1 cut-off in the pixel unit connecting with third horizontal scanning line G3, first
A source drive cell S 1 stops to the tertial blue subpixels charging of the second row, second source drive cell S 2 stop to
The red sub-pixel charging of second row the 4th column, third source drive cell S 3 stop the sub- picture of red arranged to the second row the 7th
Element charging, and so on, at this point, realizing that the pixel unit of charging will receive second selection control terminal MUX2 in the 5th stage T5
With the coupling influence of third scan line G3 deposit capacitor, pixel voltage can decline.
Then similar with fourth stage T4 and second stage T5, successive scanning third scan line G3 and the 4th scan line G4,
At this point, fourth line pixel unit is lit, and so on, until lower half frame time, that is, T/2 terminates, such frame end when
The pixel for waiting entire screen is lit entirely.
In the working sequence that Fig. 8 is provided, every horizontal scanning line can all be opened twice inside a frame time, sweep for the first time
Line opening is retouched, odd-line pixels are bright, and second of scan line is opened, and even rows are bright.
In the embodiment of the present application, under this sequential operation, since the signal of scan line and selection control terminal simultaneously declines,
So that only will receive a coupling influence after each pixel unit charging complete, the pixel voltage drop-out value of each pixel unit is big
Small consistent, thus eliminating the need the pixel unit charge rate differences of adjacent column, and then avoid generating vertical line, improve display panel
Display effect.
Transistor M1~M3 in the shift register of the offer in display panel provided with Fig. 6 is that N-type film is brilliant
For body pipe, Fig. 9 is the working timing figure for the display panel that Fig. 6 is provided, provided by the embodiments of the present application as shown in Fig. 6 and Fig. 9
The course of work of display panel specifically includes:
First stage T1, first selects the input signal of control terminal MUX1 for high level, and all second transistor M2 are led
Logical, the signal that the first scan line G1 is provided is high level, the first transistor in pixel unit connecting with the first scan line G1
M1 conducting, at this point, first source drive cell S 1 charges to the red sub-pixel of the first row first row, second source drive
Cell S 2 charges to the green sub-pixels of the first row secondary series, the green that third source drive cell S 3 is arranged to the first row the 5th
Sub-pixel charging, and so on.
Second stage T2, first selects the input signal of control terminal MUX1 for low level, and all second transistor M2 are cut
Only, the input signal of the first scan line G1 is low level, the first transistor in pixel unit connecting with the first scan line G1
M1 cut-off, first source drive cell S 1 stop charging to the red sub-pixel of the first row first row, second source drive
Cell S 2 stops charging to the green sub-pixels of the first row secondary series, and third source drive cell S 3 stops to the first row the
The green sub-pixels charging of five column, and so on, at this point, realizing that the pixel unit of charging will receive first in upper stage T1
The coupling influence of a selection control terminal MUX1 and the first scan line G1 deposit capacitor, pixel voltage can decline.Second selection
The input signal of control terminal MUX2 is high level, all third transistor M3 conductings, the first son scanning of the second horizontal scanning line G2
The input signal of line G21 is high level, and first source drive cell S 1 charges to the tertial blue subpixels of the first row, the
The charging of red sub-pixel that two source drive cell Ss 2 are arranged to the first row the 4th, third source drive cell S 3 is to the first row
The red sub-pixel charging of 7th column, and so on, at this point, the first row pixel unit is lit entirely.
After second stage T2, second selects the input signal of control terminal MUX2 for low level, the second scan line G2
The first sub- scan line G21 input signal be low level, the pixel being connect with the first sub- scan line G21 of the second scan line G2
The first transistor M1 cut-off in unit, first source drive cell S 1 stop filling to the tertial blue subpixels of the first row
Electricity, second source drive cell S 2 stop the red sub-pixel charging arranged to the first row the 4th, third source drive unit
S3 stops the red sub-pixel charging arranged to the first row the 7th, and so on, at this point, realizing the pixel of charging in second stage T2
Unit will receive the coupling shadow of the first sub- scan line G21 deposit capacitor of second selection control terminal MUX2 and the second scan line G2
It rings, pixel voltage can decline.
Then similar with first stage T1 and second stage T2, the second sub- scan line of the second scan line of successive scanning G2
The first sub- scan line G31 of G22 and third scan line G3, at this point, the second row pixel unit is lit, and so on, such one
Frame pixel of entire screen when terminating is lit entirely.
In the embodiment of the present application, under this sequential operation, since the signal of scan line and selection control terminal simultaneously declines,
So that only will receive primary coupling influence after each pixel unit charging complete, the pixel voltage drop-out value of each pixel unit
In the same size, thus eliminating the need the pixel unit charge rate differences of adjacent column, and then avoid generating vertical line, improve display surface
The display effect of plate.
Based on the same inventive concept, some embodiments of the application also provide a kind of driving method of display panel, for driving
The display panel of dynamic previous embodiment.The driving method of display panel provided by the embodiments of the present application includes: in selection control terminal
Control under, the data-signal timesharing that source electrode drive circuit exports is input in corresponding data line by multiplexer circuit.
Wherein, the display that the driving method of display panel provided by the embodiments of the present application is used to that previous embodiment to be driven to provide
Panel, realization principle is similar with effect is realized, and details are not described herein.
Based on the same inventive concept, some embodiments of the application also provide a kind of display device, which includes: aobvious
Show panel.
Optionally, which can be with are as follows: oled panel, mobile phone, tablet computer, television set, display, notebook electricity
Any products or components having a display function such as brain, Digital Frame, navigator, the embodiment of the present application do not make any limit to this
It is fixed.
Wherein, display panel is the display panel that previous embodiment provides, and realization principle is similar with effect is realized, herein
It repeats no more.
Display device may include display base plate, and pixel circuit can be set on display base plate.Preferably,
Attached drawing of the embodiment of the present invention is pertained only to the present embodiments relate to the structure arrived, and other structures, which can refer to, usually to be set
Meter.
Although disclosed herein embodiment it is as above, the content only for ease of understanding the present invention and use
Embodiment is not intended to limit the invention.Technical staff in any fields of the present invention is taken off not departing from the present invention
Under the premise of the spirit and scope of dew, any modification and variation, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of display panel characterized by comprising M row N column pixel unit, M+1 horizontal scanning line, N column data line, multichannel
Selection circuit and source electrode drive circuit；
I-th row pixel unit, connect with the i-th horizontal scanning line and i+1 horizontal scanning line respectively；Jth column pixel unit and jth columns
It is connected according to line, 1≤i≤M, 1≤j≤N；
The multiplexer circuit is connect, for selecting respectively with selection control terminal, source electrode drive circuit and N column data line
Under the control of control terminal, the data-signal timesharing that source electrode drive circuit exports is input in corresponding data line.
2. display panel according to claim 1, which is characterized in that for the i-th row jth column pixel unit, work as j=4k+1
Or when 4k+2, the i-th row jth column pixel unit is connect with the i-th horizontal scanning line；
As j=4k+3 or 4k+4, the i-th row jth column pixel unit is connect with i+1 horizontal scanning line, wherein 0≤k < N/4.
3. display panel according to claim 1, which is characterized in that s horizontal scanning line includes: the first sub- scan line and
Two sub- scan lines, 1 < s≤M；
First sub- scan line of the s horizontal scanning line is connect with s-1 row t1 column pixel unit, wherein t1=4k+3 or
4k+4,0≤k < N/4；
Second sub- scan line of the s horizontal scanning line is connect with s row t2 column pixel unit, wherein t2=4k+1 or 4k+
2；
First horizontal scanning line is connect with the first row t2 column pixel unit, M+1 horizontal scanning line and M row t1 column pixel unit
Connection.
4. display panel according to claim 2 or 3, which is characterized in that for the i-th row jth column pixel unit, the picture
Plain unit includes: display element and switch element, and the switch element includes: the first transistor；
As j=4k+1 or 4k+2, the control electrode of the first transistor is connect with the i-th horizontal scanning line, the first pole of the first transistor
It is connect with jth column data line, the second pole of the first transistor is connect with display element；
As j=4k+3 or 4k+4, the control electrode of the first transistor is connect with i+1 horizontal scanning line, and the first of the first transistor
Pole is connect with jth column data line, and the second pole of the first transistor is connect with display element.
5. display panel according to claim 4, which is characterized in that the source electrode drive circuit includes: P source drive
Unit, the multiplexer circuit include: Q selection circuit, and the selection control terminal includes: Q selection control terminal, the choosing
It selects control terminal and the selection circuit corresponds, wherein P × Q=N；
I-th of selection circuit, respectively with corresponding selection control terminal, P source drive unit, 2Qk+2i-1 column data line and
2Qk+2i column data line connection, wherein 1≤i≤Q, 0≤k < N/2Q.
6. display panel according to claim 5, which is characterized in that i-th of selection circuit includes: P i+1 crystal
Pipe；
The selection control terminal connection corresponding with i-th of selection circuit of the control electrode of j-th of i+1 transistor, j-th of i+1 are brilliant
First pole of body pipe is connect with j-th of source drive unit；
When j is even number, the second pole of j-th of i+1 transistor is connect with (j-2) Q+2i column data line, when j is odd number
When, the second pole of j-th of i+1 transistor is connect with (j-1) Q+2i-1 column data line, 1≤j≤P.
7. display panel according to claim 1, which is characterized in that the electric signal root on adjacent multiple data lines
It is arranged successively according to positive polarity, putting in order for negative polarity.
8. display panel according to claim 1, which is characterized in that the multiplexer circuit and source drive electricity
Road is located at the non-display area of the display panel.
9. a kind of display device characterized by comprising display panel as described in any one of claims 1 to 8.
10. a kind of driving method of display panel, which is characterized in that as described in any one of claims 1 to 8 aobvious for driving
Show panel, which comprises
Under the control of selection control terminal, the data-signal timesharing that source electrode drive circuit exports is input to pair by multiplexer circuit
In the data line answered.
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