CN106548745A - A kind of array base palte, display floater and display device - Google Patents
A kind of array base palte, display floater and display device Download PDFInfo
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- CN106548745A CN106548745A CN201710044158.2A CN201710044158A CN106548745A CN 106548745 A CN106548745 A CN 106548745A CN 201710044158 A CN201710044158 A CN 201710044158A CN 106548745 A CN106548745 A CN 106548745A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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Abstract
The invention discloses a kind of array base palte, display floater and display device, by arranging display control unit between every adjacent two grid lines in every grid line group, in first resolution, all display control units are used for two grid lines for disconnecting.In second resolution, at least part of display control unit in same grid line group is used for two grid lines for turning on connection, and first resolution is more than second resolution.Due in second resolution, two grid lines of at least part of display control unit conducting connection in same grid line group, make that there is on the grid line of conducting identical scanning signal, so that the corresponding pixel of grid line with same scan signal is opened to be input into identical data signal simultaneously, to show identical grey scale pattern, therefore display driver chip can export scanning signal to specific part grid line with precise control without carrying out substantial amounts of data processing again, you can realize the function that low resolution shows.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte, display floater and display device.
Background technology
Display generally comprises the display floater with multirow grid line and pixel corresponding with every row grid line, for driving
Gate driver circuit that pixel is opened, for the source electrode drive circuit to the pixel input data signal opened and for controlling
Gate driver circuit processed exports the display driver chip of scanning signal.Wherein, display driver chip is exported to gate driver circuit
Various control signal, makes gate driver circuit be input into scanning signal to every row grid line successively, to control the often corresponding picture of row grid line
Element is opened, and so as to data signal is input in corresponding pixel, makes display realize image display function.At present, display one
As show including high-resolution and low resolution shows, what the image display effect that high-resolution shows was shown than low resolution
Image display effect is good, but high-resolution shows and means that power consumption is also larger.But in actual displayed, high-resolution shows
The display effect of some pictures not may be improved significantly, but power consumption but substantially increases, and low resolution show can
So that lower power consumption.Show to carry out low resolution, display driver chip needs precise control gate driver circuit to specific
Part grid line output scanning signal, makes display to realize low resolution with input data signal to control the unlatching of specific part pixel
Display function.Can so cause display driver chip to need to carry out substantial amounts of data processing, and then cause display driver chip to need
The problem for wanting specific customization, data processing time length and power consumption higher.
The content of the invention
The embodiment of the present invention provides a kind of array base palte, display floater and display device, to solve in prior art
When low resolution shows, need display driver chip to carry out substantial amounts of data processing, cause display driver chip needs special fixed
The higher problem of system, data processing time length and power consumption.
Therefore, a kind of array base palte is embodiments provided, including：A plurality of grid line；All grid lines are divided into
Multiple grid line groups, each described grid line group include two at least adjacent grid lines；The array base palte also includes：It is connected to each
The display control unit between every adjacent two grid lines in the grid line group；
In first resolution, each display control unit is used for two grid lines for disconnecting；
In second resolution, at least part of display control unit in the same grid line group is used to turn on the two of connection
Bar grid line；Wherein, the first resolution is more than the second resolution.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, also include：Drive control unit；
The drive control unit for control in the first resolution that each display control unit is disconnected two
Bar grid line, controls what at least described part display control unit conducting in the same grid line group connected in second resolution
Two grid lines.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, each display control unit passes through respectively
One-to-one first control signal wire is connected with the drive control unit；Or,
The all of display control unit is connected with the drive control unit by same second control signal wire；Or
Person,
The part display control unit in the same grid line group is by same 3rd control signal wire and the drive
Dynamic control unit is connected, and remainder display control unit passes through one-to-one 4th control signal wire or same 5th control
Holding wire is connected with the drive control unit.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, it is connected to every in each grid line group
Display control unit between adjacent two grid lines is one, and same one end of the grid line positioned at connection；Or,
The display control unit being connected between every adjacent two grid lines in each grid line group is two, and respectively
Positioned at the two ends of the grid line of connection.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, the display control unit includes：Switch is brilliant
Body pipe；Wherein,
The grid of the switching transistor is used for the drive control signal for receiving drive control unit output, and the switch is brilliant
The source electrode of body pipe is drained with which and be connected with corresponding adjacent two grid lines respectively.
Preferably, it is in above-mentioned array base palte provided in an embodiment of the present invention, in the second resolution, same described
The whole display control unit in grid line group is used for two grid lines for turning on connection.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, the array base palte also includes：It is located at least in
The gate driver circuit of each described grid line one end；
The gate driver circuit includes the multi-stage shift register unit for cascading, and the shift register cell at different levels
Respectively M levels shift register cell；Wherein, M is the integer more than or equal to 1, and the shift register list at different levels
The outfan of unit connects one to one a grid line；Or,
The array base palte also includes：Respectively positioned at the gate driver circuit at each grid line two ends；Wherein,
Gate driver circuit positioned at each described grid line one end includes：The multi-stage shift register unit of cascade, and it is at different levels
The shift register cell is respectively 2N-1 level shift register cells；Positioned at the raster data model of each grid line other end
Circuit includes：The multi-stage shift register unit of cascade, and the shift register cell at different levels be respectively 2N levels displacement post
Storage unit；Wherein, N is the integer more than or equal to 1, and the outfan of the shift register cell at different levels is corresponded
One grid line of connection.
Preferably, in above-mentioned array base palte provided in an embodiment of the present invention, also include：Display driver chip；
In the first resolution, the display driver chip is used to control all shift register cells successively
Output scanning signal；
In the second resolution, the display driver chip is used to control kth N- (k-n) level shift register cell
It is sequentially output scanning signal；Wherein, k is the sum of grid line in each grid line group, and n is the integer less than or equal to k.
Correspondingly, the embodiment of the present invention additionally provides a kind of display floater, including above-mentioned provided in an embodiment of the present invention
A kind of array base palte.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including provided in an embodiment of the present invention above-mentioned aobvious
Show panel.
The present invention has the beneficial effect that：
Array base palte provided in an embodiment of the present invention, display floater and display device, by every in each grid line group
Between adjacent two grid lines, display control unit is set, in first resolution, two disconnected by display control unit
Bar grid line, can make every grid line separate, such that it is able to make to have respective scanning signal on every grid line, and then make each
Data signal needed for the corresponding pixel input of grid line, to realize that each pixel shows respective grey scale pattern.Differentiate second
During rate, two grid lines of connection are turned on by least part of display control unit, can make that there is on the grid line of mutual conduction phase
Same scanning signal, so that the corresponding pixel of grid line with same scan signal is opened to be input into identical data letter simultaneously
Number, and then make the corresponding pixel of the grid line with same scan signal show identical grey scale pattern.Therefore differentiate using first
Rate carries out display and can realize that high-resolution high definition shows, carries out display using second resolution and can realize that low resolution shows
Show, such that it is able to realize that high-resolution shows the translation function shown with low resolution.And with low point is realized in prior art
Resolution shows to be compared, and array base palte provided in an embodiment of the present invention is in fit on display driver chip and gate driver circuit
Afterwards, as the grid line for turning on has identical scanning signal, therefore display driver chip can be without carrying out substantial amounts of data again
Process and scanning signal is exported to specific part grid line with precise control, you can realize the function that low resolution shows.And so
The structural design change of array substrate is less, can reduce technique and be conducive to saving cost of manufacture.
Description of the drawings
Fig. 1 a are one of structural representation of array base palte provided in an embodiment of the present invention；
Fig. 1 b are the two of the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 1 c are the three of the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 1 d are the four of the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 1 e are the five of the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 2 a are one of concrete structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 2 b are the two of the concrete structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 2 c are the three of the concrete structure schematic diagram of array base palte provided in an embodiment of the present invention；
Fig. 3 is the concrete structure schematic diagram of shift register cell provided in an embodiment of the present invention；
Input and output sequential charts of Fig. 4 a for the shift register cell shown in Fig. 3 in first resolution；
Input and output sequential charts of Fig. 4 b for the shift register cell shown in Fig. 3 in second resolution.
Specific embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention
The specific embodiment of the array base palte, display floater and display device of offer is described in detail.It should be appreciated that following institute
The preferred embodiment of description is merely to illustrate and explains the present invention, is not intended to limit the present invention.And in situation about not conflicting
Under, the feature in embodiment and embodiment in the application can be mutually combined.
In accompanying drawing, size and shape of each figure etc. does not reflect the actual proportions of array base palte, and purpose is schematically illustrate
Present invention.
A kind of array base palte is embodiments provided, as shown in Fig. 1 a to Fig. 1 e, including：A plurality of grid line 100；By institute
There is 100 points of grid line to be multiple grid line groups 200, each grid line group 200 includes two at least adjacent grid lines；Array base palte is also wrapped
Include：The display control unit 300 being connected between every adjacent two grid lines 100 in each grid line group 200；
In first resolution, each display control unit 300 is used for two grid lines 100 for disconnecting；
In second resolution, at least part of display control unit 300 in same grid line group 200 is used to turn on connection
Two grid lines 100；Wherein, first resolution is more than second resolution.
Above-mentioned array base palte provided in an embodiment of the present invention, by between every adjacent two grid lines in each grid line group
Display control unit is set, and in first resolution, two grid lines disconnected by display control unit can be made per bar
Grid line is separate, such that it is able to make to have respective scanning signal on every grid line, and then makes the corresponding pixel of each grid line defeated
Data signal needed for entering, to realize that each pixel shows respective grey scale pattern.In second resolution, by least part of
Two grid lines of display control unit conducting connection, can make have identical scanning signal on the grid line of mutual conduction, so as to
The corresponding pixel of the grid line with same scan signal is made while opening to be input into identical data signal, and then make with identical
The corresponding pixel of grid line of scanning signal shows identical grey scale pattern.Therefore carry out display using first resolution to realize
High-resolution high definition shows, carries out display using second resolution and can realize that low resolution shows, such that it is able to realize height
The translation function that resolution shows and low resolution shows.And compared with realizing in prior art that low resolution shows, this
The array base palte that bright embodiment is provided after fit on display driver chip and gate driver circuit, due to the grid line tool for turning on
There is an identical scanning signal, therefore display driver chip can be without carrying out substantial amounts of data processing with precise control to specific again
Part grid line output scanning signal, you can realize the function that low resolution shows.And such structure design of array substrate
Change less, technique can be reduced and be conducive to saving cost of manufacture.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, can be by all grid line average marks
For multiple grid line groups.For example shown in Fig. 1 a and Fig. 1 e, each grid line group 200 can include two grid lines 100.Or such as Fig. 1 b institutes
Show, each grid line group 200 can include three grid lines 100.Or as illustrated in figure 1 c, each grid line group 200 can include four grid
Line 100.Or as shown in Figure 1 d, each grid line group 200 can include five grid lines 100.
Or, in the specific implementation, it would however also be possible to employ all grid lines are arbitrarily divided into multiple grid by the method for non-average division
Line group.Two grid lines can be included in i.e. a part of grid line group, three grid lines in another part grid line group, can be included.Or, the
Two grid lines can be included in a part of grid line group, three grid lines, Part III grid line in Part II grid line group, can be included
Four grid lines can be included in group.Certainly in actual applications, grid line group with divide need according to practical situations come
It is determined that, it is not limited thereto.Below as a example by averagely dividing grid line group, array base palte provided in an embodiment of the present invention is carried out
Explanation.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, in second resolution, same grid
Part display control unit in line group is used for two grid lines for turning on connection.Specifically, as shown in Figure 1 b, in each grid line group
200 when including three grid lines 100, in second resolution, in two display control units 300 in same grid line group 200
Two in one two grid line for being used to turn on connection, therefore every grid line group 200 in three grid lines 100 can turn on to have
Identical scanning signal, allows the 100 corresponding pixel of grid line of this two conductings while opening to be input into identical data letter
Number, so that two pixels in this two grid lines, 100 corresponding two row and same row of conducting are equivalent to one pixel of display
Grey scale pattern, can make second resolution be less than first resolution.Or, as illustrated in figure 1 c, include in each grid line group 200
It is during four grid lines 100, in second resolution, two neighboring in three display control units 300 in same grid line group 200
For turning on two grid lines 100 of connection, therefore in four grid lines 100, adjacent three grids can be led in each grid line group 200
Pass to identical scanning signal, the 100 corresponding pixel of grid of this three conductings is allow while opening identical to be input into
Data signal so that conducting this three grid lines, 100 corresponding three row and same row in three pixels equivalent to display
The pattern of one pixel, can make second resolution be less than first resolution.Certainly, four grid are included in each grid line group 200
During line 100, in second resolution, second display control unit 300 in same grid line group 200 is used to turn on the two of connection
Bar grid line 100, therefore can be turned on per the Article 2 grid line 100 and Article 3 grid line 100 in grid line group 200 with identical
Scanning signal, allows the 100 corresponding pixel of grid of this two conductings while opening to be input into identical data signal, so as to
Two pixels in this two grid lines, 100 corresponding two row and same row of conducting are made equivalent to the pattern for showing a pixel,
Second resolution can be made to be less than first resolution.Or, as shown in Figure 1 d, include five grid lines 100 in each grid line group 200
When, in second resolution, one or two or three display control units 300 in same grid line group 200 are used for the company of conducting
The 100 corresponding pixel of grid turned in two grid lines 100 for connecing, therefore every grid line group 200 can be while open to be input into phase
With data signal so that in the corresponding several rows of this several grid lines 100 of conducting and several pixels in same row are suitable
In the pattern for showing a pixel, second resolution can be made to be less than first resolution.In the same manner, the rest may be inferred, and here is not gone to live in the household of one's in-laws on getting married
State, such that it is able to realize translation function that various resolution show.
Or, in the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, in second resolution,
Whole display control units in same grid line group are used for two grid lines for turning on connection.Specifically, as shown in Fig. 1 a and Fig. 1 e,
When each grid line group 200 includes two grid lines 100, the display control unit in second resolution, in same grid line group 200
300 are used to turn on two grid lines 100 of connection, i.e., opened per two grid lines, the 100 corresponding pixel in grid line group 200 simultaneously with
Input identical data signal, so that two pixel phases in this two grid lines, 100 corresponding two row and same row of conducting
It is first resolution when second resolution in the pattern for showing a pixel, can be madeOr, as shown in Figure 1 b, every
Display control unit 300 when individual grid line group 200 includes three grid lines 100, in second resolution, in same grid line group 200
For turning on two grid lines 100 of connection, therefore can beat simultaneously per three grid lines, the 100 corresponding pixel in grid line group 200
Open to be input into identical data signal, so that three pictures in this three grid lines, 100 corresponding three row and same row of conducting
Element can make second resolution for first resolution equivalent to the pattern for showing a pixelOr, as illustrated in figure 1 c,
Display control unit when each grid line group 200 includes four grid lines 100, in second resolution, in same grid line group 200
300 are used to turn on two grid lines 100 of connection, therefore can be per four grid lines, the 100 corresponding pixel in grid line group 200 simultaneously
Open to be input into identical data signal, so that four in this four grid lines, 100 corresponding four row and same row of conducting
Pixel can make second resolution for first resolution equivalent to the pattern for showing a pixelOr, such as Fig. 1 d institutes
Show, when each grid line group 200 includes five grid lines 100, the display control in second resolution, in same grid line group 200
Unit 300 is used for two grid lines 100 for turning on connection, therefore can be with per five grid lines, the 100 corresponding pixel in grid line group 200
Open to be input into identical data signal simultaneously, so that in the 100 corresponding five elements of this five grid lines of conducting and same row
Five pixels can make second resolution for first resolution equivalent to the pattern for showing a pixelIn the same manner, class according to this
Push away, therefore not to repeat here, such that it is able to realize translation function that Resolutions show.
In the specific implementation, above-mentioned array base palte provided in an embodiment of the present invention can also include arranging each grid line and each
The underlay substrate of display control unit.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 1 a to Fig. 1 e, also wrap
Include：Drive control unit 400；
Drive control unit 400 for controlling two grid that each display control unit is disconnected in first resolution
Line, controls two grid lines of at least part of display control unit conducting connection in same grid line group in second resolution.Should
Drive control unit can be to display control unit output driving control signal, so that each display control is controlled in first resolution
Two grid lines that unit is disconnected, at least part of display control unit controlled in second resolution in same grid line group are led
Lead to two grid lines for connecing.
In the specific implementation, it is in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 1 b and Fig. 1 e, each aobvious
Show that the difference of control unit 300 can be connected with drive control unit 400 by one-to-one first control signal wire 510.
Or, as shown in Figure 1a, all of display control unit 300 can by same second control signal wire 520 with
Drive control unit 400 is connected.
Or, as shown in Fig. 1 c and Fig. 1 d, the part display control unit 300 in same grid line group 200 can be by same
One the 3rd control signal wire 530 is connected with drive control unit 400, and remainder display control unit 300 can be by one by one
Corresponding 4th control signal wire 540 is connected with drive control unit 400.
Or, the part display control unit in same grid line group can be controlled with driving by same 3rd control signal wire
Unit processed is connected, and remainder display control unit can be connected with drive control unit by same 5th control signal wire.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 1 a to Fig. 1 d, connection
Display control unit 300 between every adjacent two grid lines 100 in each grid line group 200 is one, and positioned at connection
Same one end of grid line 100.
Or, for further stability contorting, as shown in fig. le, every adjacent two be connected in each grid line group 200
Display control unit 300 between grid line 100 is two, and is located at the two ends of the grid line 100 of connection respectively.So can be every
A display control unit 300 between adjacent two grid lines 100 is damaged when not working, due to another display control unit
300 effect, can also realize the conducting function of two grid lines.
Two grid lines and the display control unit being connected between adjacent two grid lines are included with every grid line group below
As a example by for one, array base palte provided in an embodiment of the present invention is illustrated.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 2 a to Fig. 2 c, show
Control unit 300 can specifically include：Switching transistor M0；Wherein,
The grid of switching transistor M0 is used for the drive control signal for receiving the output of drive control unit 400, switchs crystal
The source electrode of pipe M0 is drained with which and be connected with corresponding adjacent two grid lines 100 respectively.Wherein, switching transistor M0 is corresponding adjacent
Two grid line 100 is respectively two grid lines 100 that the display control unit 300 at its place is connected.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Fig. 2 a to Fig. 2 c, switch
Transistor M0 can be N-type transistor, and in first resolution, drive control signal is the letter of the voltage with electronegative potential
Number, in second resolution, drive control signal is the voltage signal with high potential.Or, switching transistor can also be P
Transistor npn npn, and in first resolution, drive control signal is the voltage signal with high potential, in second resolution
When, drive control signal is the voltage signal with electronegative potential.In actual applications, the concrete structure of switching transistor needs root
Determine according to practical situations, be not limited thereto.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, switching transistor is in drive control
When in the conduction state under the control of signal, two grid lines of its source electrode and drain electrode connection can be turned on.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Figure 2 a, array base palte is also
Can include：Positioned at the gate driver circuit 600 of 100 one end of each grid line；
Gate driver circuit 600 includes multi-stage shift register cell S R (M) for cascading, and shift register cell at different levels
SR (M) is respectively M level shift register cells；Wherein, M is the integer more than or equal to 1, and shift register list at different levels
The outfan Output of first SR (M) connects one to one a grid line 100.
Or, as shown in Figure 2 b, array base palte can also include：Positioned at the gate driver circuit 600 at each grid line two ends；
Gate driver circuit 600 includes multi-stage shift register cell S R (M) for cascading, and shift register cell at different levels
SR (M) is respectively M level shift register cells；Wherein, M is the integer more than or equal to 1, and shift register list at different levels
The outfan Output of first SR (M) connects one to one a grid line 100.
Or, as shown in Figure 2 c, array base palte can also include：Respectively positioned at the raster data model electricity at 100 two ends of each grid line
Road 600；Wherein,
Gate driver circuit 600 positioned at 100 one end of each grid line includes：The multi-stage shift register cell S R (2N- of cascade
1), and shift register cell SR at different levels (2N-1) be respectively 2N-1 level shift register cells；It is another positioned at each grid line 100
The gate driver circuit 600 at end includes：Multi-stage shift register cell S R (2N) of cascade, and shift register cell SR at different levels
(2N) 2N level shift register cells are respectively；Wherein, N is the integer more than or equal to 1, and shift register list at different levels
The outfan Output of first SR (2N-1) connects one to one a grid line, and shift register cell SR's at different levels (2N) is defeated
Go out to hold Output to connect one to one a grid line.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, also include：Display driver chip；
In first resolution, display driver chip is sequentially output scanning letter for controlling all shift register cells
Number；
In second resolution, display driver chip is sequentially output for controlling kth N- (k-n) level shift register cell
Scanning signal；Wherein, k is the sum of grid line in each grid line group, and n is the integer less than or equal to k.For example, in each grid line group bag
When including two grid lines, the shift register cells at different levels of display driver chip control odd-numbered line are sequentially output scanning signal, or control
The shift register cells at different levels of even number line processed are sequentially output scanning signal.When each grid line group includes three grid lines, show and drive
The shift register cells at different levels of dynamic chip controls 3N row are sequentially output scanning signal, or the shift LDs at different levels of control 3N-1 rows
Device unit is sequentially output scanning signal, or the shift register cells at different levels of control 3N-2 rows are sequentially output scanning signal.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, drive control unit can also be
Drive control chip.And the drive control chip can be a chip with display driver chip, it is also possible to respectively independent
Chip.Also, drive control chip is same as the prior art with the concrete structure of display driver chip, it is the common of this area
Technical staff should be appreciated that what is had, and here is not detailed, and also should not be taken as limiting the invention.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, shift register
Unit can specifically include：First switch transistor M1, second switch transistor M2, the 3rd switching transistor M3, the 4th switch
Transistor M4, the 5th switching transistor M5, the 6th switching transistor M6, the 7th switching transistor M7, the 8th switching transistor M8,
First electric capacity C1 and the second electric capacity C2；Wherein,
The grid of first switch transistor M1 is connected with input signal end Input, source electrode and the first direct current signal end CN phases
Even, drain electrode is connected with primary nodal point A；
The grid of second switch transistor M2 is connected with reset signal end Reset, source electrode and the second direct current signal end CNB phases
Even, drain electrode is connected with primary nodal point A；
The grid of the 3rd switching transistor M3 is connected with primary nodal point A, and source electrode is connected with the first clock signal terminal CK, drain electrode
It is connected with the outfan Output of shift register cell；
The grid of the 4th switching transistor M4 is connected with secondary nodal point B, and source electrode is connected with reference signal end VGL, drain electrode with
Outfan Output is connected；
The grid of the 5th switching transistor M5 is connected with secondary nodal point B, and source electrode is connected with reference signal end VGL, drain electrode with
Primary nodal point A is connected；
The grid of the 6th switching transistor M6 is connected with primary nodal point A, and source electrode is connected with reference signal end VGL, drain electrode with
Secondary nodal point B is connected；
The grid of the 7th switching transistor M7 is connected with outfan Output, and source electrode is connected with reference signal end VGL, drain electrode
It is connected with secondary nodal point B；
The grid of the 8th switching transistor M8 is connected with second clock signal end with its source electrode, is drained and secondary nodal point B
It is connected；
First electric capacity C1 is connected between primary nodal point A and outfan Output；
Second electric capacity C2 is connected between secondary nodal point B and reference signal end VGL.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in figure 3, all switches are brilliant
Body pipe can be N-type transistor, and the effective impulse signal of input signal end Input is high potential, the first direct current signal end CN's
Current potential is high potential, and the current potential of the current potential and reference signal end VGL of the second direct current signal end CNB is electronegative potential.Or, institute
There is the switching transistor can also be for P-type transistor, the effective impulse signal at input signal end is electronegative potential, the first direct current signal end
Current potential be electronegative potential, the current potential at the second direct current signal end and the high electronegative potential of the current potential at reference signal end, here do not limit
It is fixed.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, electricity of the N-type transistor in high potential
Turn in the presence of pressure signal, end under the control of the voltage signal of electronegative potential.Voltage signal of the P-type transistor in electronegative potential
In the presence of turn on, under the control of the voltage signal of high potential end.
The above is only the tool for illustrating display control unit provided in an embodiment of the present invention and shift register cell
Body structure, in the specific implementation, the concrete structure of display control unit and shift register cell is not limited to enforcement of the present invention
Example provide said structure, can also be skilled person will appreciate that other structures, be not limited thereto.
Below by taking the structure of the shift register cell shown in Fig. 3 as an example, with reference to first resolution and second resolution
Input and output sequential chart is illustrated to the working condition that the present invention implements the shift register cell for providing.Wherein, first is straight
The current potential of stream signal end CN is high potential, and the current potential of the second direct current signal end CNB is electronegative potential, the current potential of reference signal end VGL
For electronegative potential.
In first resolution, the corresponding input and output sequential chart of shift register cell as shown in fig. 4 a, in odd-numbered line
Shift register cells at different levels operationally, its input signal end Input, the first clock signal terminal CK, second clock signal end
The signal of CKB and outfan Output is respectively input1, ck1, ckb1 and output1；Displacements at different levels in even number line are posted
Storage unit operationally, its input signal end Input, the first clock signal terminal CK, second clock signal end CKB and output
The signal of end Output is respectively input2, ck2, ckb2 and output2.And the specific works of the shift register cell
Process is same as the prior art, it will be apparent to an ordinarily skilled person in the art that having, here is not detailed.
In second resolution, when the shift register cells at different levels of odd-numbered line are operated, the shiftings at different levels of even number line
The current potential of all signal ends of bit register unit is electronegative potential.And the corresponding input of shift register cell of odd-numbered line
Output timing diagram as shown in Figure 4 b, when the shift register cells at different levels of odd-numbered line work, its input signal end Input, the
The signal of one clock signal terminal CK, second clock signal end CKB and outfan Output be respectively input, ck, ckb and
output.And the specific work process of the shift register cell is same as the prior art, it is the ordinary skill people of this area
Member should be appreciated that what is had, and here is not detailed.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display floater, including the embodiment of the present invention is carried
For any of the above-described kind of array base palte.The principle of the display floater solve problem is similar to aforementioned array substrate, therefore the display
The enforcement of panel may refer to the enforcement of above-mentioned array base palte, repeats part and will not be described here.
In the specific implementation, display floater provided in an embodiment of the present invention can be driven to grid using Smart View technologies
After galvanic electricity road carries out sequential export control, the conducting and disconnection of two grid lines of connection are controlled by display control unit, can
It is to save the amount of calculation that display driver chip is calculated to big data process, substantial amounts of such that it is able to avoid display driver chip from carrying out
Data processing and reduction power consumption.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention is carried
For above-mentioned display floater.The display device can be：Mobile phone, panel computer, television set, display, notebook computer, number
Any product with display function such as photo frame, navigator or part.For other requisite compositions of the display device
Part is it will be apparent to an ordinarily skilled person in the art that have, and be will not be described here, also be should not be used as to the present invention's
Limit.The enforcement of the display device may refer to the embodiment of above-mentioned array base palte, repeats part and repeats no more.
Array base palte provided in an embodiment of the present invention, display floater and display device, by every in each grid line group
Between adjacent two grid lines, display control unit is set, in first resolution, two disconnected by display control unit
Bar grid line, can make every grid line separate, such that it is able to make to have respective scanning signal on every grid line, and then make each
Data signal needed for the corresponding pixel input of grid line, to realize that each pixel shows respective grey scale pattern.Differentiate second
During rate, two grid lines of connection are turned on by least part of display control unit, can make that there is on the grid line of mutual conduction phase
Same scanning signal, so that the corresponding pixel of grid line with same scan signal is opened to be input into identical data letter simultaneously
Number, and then make the corresponding pixel of the grid line with same scan signal show identical grey scale pattern.Therefore differentiate using first
Rate carries out display and can realize that high-resolution high definition shows, carries out display using second resolution and can realize that low resolution shows
Show, such that it is able to realize that high-resolution shows the translation function shown with low resolution.And with low point is realized in prior art
Resolution shows to be compared, and array base palte provided in an embodiment of the present invention is in fit on display driver chip and gate driver circuit
Afterwards, as the grid line for turning on has identical scanning signal, therefore display driver chip can be without carrying out substantial amounts of data again
Process and scanning signal is exported to specific part grid line with precise control, you can realize the function that low resolution shows.And so
The structural design change of array substrate is less, can reduce technique and be conducive to saving cost of manufacture.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of array base palte, including：A plurality of grid line；Characterized in that, all grid lines are divided into into multiple grid line groups, each
The grid line group includes two at least adjacent grid lines；The array base palte also includes：It is connected in each grid line group
Display control unit between per adjacent two grid lines；
In first resolution, each display control unit is used for two grid lines for disconnecting；
In second resolution, at least part of display control unit in the same grid line group is used for two grid for turning on connection
Line；Wherein, the first resolution is more than the second resolution.
2. array base palte as claimed in claim 1, it is characterised in that also include：Drive control unit；
The drive control unit for controlling two grid that each display control unit is disconnected in the first resolution
Line, controls two of at least described part display control unit conducting connection in the same grid line group in second resolution
Grid line.
3. array base palte as claimed in claim 2, it is characterised in that each display control unit is respectively by corresponding
The first control signal wire be connected with the drive control unit；Or,
The all of display control unit is connected with the drive control unit by same second control signal wire；Or,
The part display control unit in the same grid line group drives control with described by same 3rd control signal wire
Unit processed is connected, and remainder display control unit is by one-to-one 4th control signal wire or same 5th control signal
Line is connected with the drive control unit.
4. array base palte as claimed in claim 1, it is characterised in that every adjacent two be connected in each grid line group
Display control unit between grid line is one, and same one end of the grid line positioned at connection；Or,
The display control unit being connected between every adjacent two grid lines in each grid line group is two, and is located at respectively
The two ends of the grid line of connection.
5. the array base palte as described in any one of claim 1-4, it is characterised in that the display control unit includes：Switch
Transistor；Wherein,
The grid of the switching transistor is used for the drive control signal for receiving drive control unit output, the switching transistor
Source electrode with its drain respectively with corresponding adjacent two grid lines be connected.
6. the array base palte as described in any one of claim 1-4, it is characterised in that in the second resolution, same institute
Stating the whole display control unit in grid line group is used to turn on two grid lines of connection.
7. array base palte as claimed in claim 6, it is characterised in that the array base palte also includes：It is located at least in each described
The gate driver circuit of grid line one end；
The gate driver circuit includes the multi-stage shift register unit for cascading, and the shift register cell difference at different levels
For M level shift register cells；Wherein, M is the integer more than or equal to 1, and the shift register cell at different levels
Outfan connects one to one a grid line；Or,
The array base palte also includes：Respectively positioned at the gate driver circuit at each grid line two ends；Wherein,
Gate driver circuit positioned at each described grid line one end includes：The multi-stage shift register unit of cascade, and it is at different levels described
Shift register cell is respectively 2N-1 level shift register cells；Positioned at the gate driver circuit of each grid line other end
Including：The multi-stage shift register unit of cascade, and the shift register cell at different levels is respectively 2N level shift registers
Unit；Wherein, N is the integer more than or equal to 1, and the outfan of the shift register cell at different levels connects one to one
One grid line.
8. array base palte as claimed in claim 7, it is characterised in that also include：Display driver chip；
In the first resolution, the display driver chip is sequentially output for controlling all shift register cells
Scanning signal；
In the second resolution, the display driver chip is used to control kth N- (k-n) level shift register cell successively
Output scanning signal；Wherein, k is the sum of grid line in each grid line group, and n is the integer less than or equal to k.
9. a kind of display floater, it is characterised in that include the array base palte as described in any one of claim 1-8.
10. a kind of display device, it is characterised in that including display floater as claimed in claim 9.
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| CN201710044158.2A CN106548745A (en) | 2017-01-19 | 2017-01-19 | A kind of array base palte, display floater and display device |
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| CN201710044158.2A CN106548745A (en) | 2017-01-19 | 2017-01-19 | A kind of array base palte, display floater and display device |
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Application publication date: 20170329 |