CN113808489B

CN113808489B - Display panel, driving method thereof and display device

Info

Publication number: CN113808489B
Application number: CN202111114940.XA
Authority: CN
Inventors: 王兰兰; 敦栋梁
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-09-23
Filing date: 2021-09-23
Publication date: 2023-09-08
Anticipated expiration: 2041-09-23
Also published as: CN113808489A

Abstract

The embodiment of the invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a plurality of first multipath selection circuits, a plurality of first pixel circuit groups arranged along the row direction and a plurality of data lines; the first pixel circuit group comprises at least two columns of sub-pixel circuits; along the row direction, a first data line and a second data line are sequentially arranged on two opposite sides of each column of sub-pixel circuits; two adjacent sub-pixel circuits in the same row and column are respectively connected with a first data line and a second data line; the first multiplexing circuit comprises a first selection module and a second selection module which are connected in an upper-lower stage, and is used for outputting the data signals received by the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing way under the control of row selection signals and column selection signals. The scheme can solve the problem of insufficient writing time of the data signals of the high-frequency and high-resolution display panel, reduce the number of data signal channels of the driving chip and save the cost.

Description

Display panel, driving method thereof and display device

Technical Field

The embodiment of the invention relates to a display technology, in particular to a display panel, a driving method thereof and a display device.

Background

Currently, display devices (such as mobile phones) are moving toward high resolution and high refresh frequency (high frequency) to meet market demands.

For the development of high-frequency and high-resolution products, firstly, the problem of uneven display caused by the shortages of scanning time of each row of sub-pixels and insufficient writing time of data signals is solved; secondly, the number of data signal channels of the driving chip with high resolution display requirement is increased, and the cost of the driving chip is increased, so how to reduce the number of data signal channels of the driving chip with product requirement, and reduce the cost are also the problems to be solved urgently.

Disclosure of Invention

The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for solving the problem of insufficient writing time of data signals of a high-frequency and high-resolution display panel, reducing the number of data signal channels of a driving chip and saving cost.

In a first aspect, an embodiment of the present invention provides a display panel, including: a plurality of first multiplexing circuits, a plurality of first pixel circuit groups arranged in a row direction, and a plurality of data lines;

the first pixel circuit group comprises at least two columns of sub-pixel circuits; the data line comprises a first data line and a second data line, the first data line is positioned on a first side of each column of sub-pixel circuits along the row direction, the second data line is positioned on a second side of each column of sub-pixel circuits, and the first side and the second side are opposite sides of the sub-pixel circuits; two adjacent sub-pixel circuits in the same row are respectively connected with a first data line and a second data line, and two adjacent sub-pixel circuits in the same column are respectively connected with the first data line and the second data line;

The first multiplexing circuits are arranged in one-to-one correspondence with the first pixel circuit groups; the first multi-path selection circuit comprises a first selection module and a second selection module, wherein the output end of the first selection module is correspondingly and electrically connected with the input end of the second selection module, and the output end of the second selection module is correspondingly and electrically connected with the data line corresponding to the first pixel circuit group;

the display panel further comprises a row selection control line and a column selection control line, and the first multi-path selection circuit is used for outputting the data signals received by the data signal input end of the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing manner under the control of the row selection signals output by the row selection control line and the column selection signals output by the column selection control line.

In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, for driving the display panel provided in the first aspect, including:

transmitting a data signal to a data signal input of a first selection module in the plurality of first multiplexing circuits;

the first multiplexing circuit outputs the data signals received by the data signal input end of the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing way under the control of row selection signals output by the row selection control lines and column selection signals output by the column selection control lines.

In a third aspect, an embodiment of the present invention further provides a display apparatus, including the display panel provided in the first aspect.

According to the technical scheme, the first data line and the second data line are respectively arranged on the two opposite sides of each row of sub-pixels, so that two adjacent sub-pixel circuits in the same row are respectively connected with the first data line and the second data line, and data writing of two adjacent rows of sub-pixel circuits is not affected, data writing can be continuously carried out on the x-1 row of sub-pixel circuits in the stage of data writing of the x-1 row of sub-pixel circuits, the writing duration of data signals is prolonged, the problem of uneven display of high-frequency and high-resolution products is solved, and the adjacent two sub-pixel circuits in the same row are respectively connected with the first data line and the second data line, so that the problem of cross lines in display can be avoided under the condition that loads on the first data line and the second data line are different, and the display effect is improved. Further, the first multi-path selection circuit comprises a first selection module and a second selection module which are connected in an upper-lower stage, so that data signals received by the data signal input end of the first selection module can be output to the data line corresponding to the first pixel circuit in a time-sharing manner under the control of row selection signals and column selection signals, and data writing of the sub-pixel circuits is realized.

Drawings

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 4 is a timing diagram of driving the display panel shown in FIG. 3;

FIG. 5 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a driving timing diagram of the display panel shown in FIG. 5;

fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another display panel according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another display panel according to an embodiment of the present invention;

fig. 12 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

fig. 13 is a flowchart of another driving method of a display panel according to an embodiment of the present invention;

fig. 14 is a flowchart of another driving method of a display panel according to an embodiment of the present invention;

Fig. 15 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all structures related to the present application are shown in the accompanying drawings, and the shapes and sizes of the elements in the drawings do not reflect the actual proportions thereof, for the purpose of illustrating the present application only.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.

The display panel comprises a plurality of rows and a plurality of columns of sub-pixel circuits, and each sub-pixel circuit drives a corresponding light-emitting element to emit light based on a data signal transmitted by a corresponding data line through scanning the sub-pixel circuits row by row, so that display is realized. When the refresh frequency is increased, the scanning time of a frame of picture is shortened, and the scanning time distributed to each row of sub-pixel circuits is also shortened, so that the data signal writing time of the sub-pixel circuits is insufficient, the problem of uneven display occurs, and when the resolution is increased, the number of rows and columns of the sub-pixel circuits is increased, and the phenomenon is more serious. In addition, when the number of sub-pixel columns increases, more data signal channels are required to be provided for the driving chip, so that the existing driving chip is not applicable and the cost is increased.

In order to solve the above problems, an embodiment of the present invention provides a display panel, including a plurality of first multiplexing circuits, a plurality of first pixel circuit groups arranged along a row direction, and a plurality of data lines; the first pixel circuit group comprises at least two columns of sub-pixel circuits; the data line comprises a first data line and a second data line, the first data line is positioned on a first side of each column of sub-pixel circuits along the row direction, the second data line is positioned on a second side of each column of sub-pixel circuits, and the first side and the second side are opposite sides of the sub-pixel circuits; two adjacent sub-pixel circuits in the same row are respectively connected with a first data line and a second data line, and two adjacent sub-pixel circuits in the same column are respectively connected with the first data line and the second data line; the first multiplexing circuits are arranged in one-to-one correspondence with the first pixel circuit groups; the first multi-path selection circuit comprises a first selection module and a second selection module, wherein the output end of the first selection module is correspondingly and electrically connected with the input end of the second selection module, and the output end of the second selection module is correspondingly and electrically connected with the data line corresponding to the first pixel circuit group; the display panel further comprises a row selection control line and a column selection control line, and the first multi-path selection circuit is used for outputting the data signals received by the data signal input end of the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing manner under the control of the row selection signals output by the row selection control line and the column selection signals output by the column selection control line.

According to the technical scheme, since each row of sub-pixels is correspondingly provided with two data lines, namely the first data line and the second data line, and two adjacent sub-pixel circuits in the same row are connected with different data lines (respectively connected with the first data line and the second data line), data writing of two adjacent rows of sub-pixel circuits is not affected, so that data writing can be continuously carried out on the x-1 row of sub-pixel circuits in the stage of data writing of the x-th row of sub-pixel circuits, writing time of data signals is prolonged, the problem of uneven display of high-frequency and high-resolution products is solved, and in addition, under the condition that loads (loading) on the first data line and the second data line are different, the problem of cross grain in display can be avoided, and the display effect is improved. Further, the first multi-path selection circuit comprises a first selection module and a second selection module which are connected in an upper-lower stage, so that data signals received by the data signal input end of the first selection module can be output to the data line corresponding to the first pixel circuit in a time-sharing manner under the control of row selection signals and column selection signals, and data writing of the sub-pixel circuits is realized.

The above is the core idea of the application, and based on the embodiments of the application, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, referring to fig. 1, the display panel according to the embodiment of the present application includes: a plurality of first multiplexing circuits 10, a plurality of first pixel circuit groups 20 arranged in the row direction, and a plurality of data lines; the first pixel circuit group 20 includes at least two columns of sub-pixel circuits P; the data lines comprise a first data line D1 and a second data line D2, the first data line D1 is positioned on a first side of each column of the sub-pixel circuits along the row direction, the second data line D2 is positioned on a second side of each column of the sub-pixel circuits, and the first side and the second side are opposite sides of the sub-pixel circuits P; two adjacent sub-pixel circuits P in the same row are respectively connected with the first data line D1 and the second data line D2, and two adjacent sub-pixel circuits P in the same column are respectively connected with the first data line D1 and the second data line D2; the first multiplexing circuits 10 are arranged in one-to-one correspondence with the first pixel circuit groups 20; the first multi-path selection circuit 10 comprises a first selection module 11 and a second selection module 12, wherein the output end of the first selection module 11 is electrically connected with the input end of the second selection module 12 in a one-to-one correspondence manner, and the output end of the second selection module 12 is electrically connected with the data line corresponding to the first pixel circuit group 20 in a one-to-one correspondence manner; the display panel further includes a row selection control line SW and a column selection control line MUX, and the first multiplexing circuit 10 is configured to output the data signal received by the data signal input terminal S of the first selection module 11 to the data line corresponding to the first pixel circuit group 20 in a time-sharing manner under the control of the row selection signal output by the row selection control line SW and the column selection signal output by the column selection control line MUX.

In fig. 1, the first pixel circuit group 20 includes two columns of sub-pixel circuits, and in other embodiments, the first pixel circuit group 20 includes at least two columns of sub-pixel circuits, which is not limited in the embodiment of the present invention. As shown in fig. 1, along the row direction, two opposite sides of each column of sub-pixel circuits are respectively provided with a data line, namely a first data line D1 and a second data line D2, two adjacent sub-pixel circuits P in the same row are connected with different data lines, namely the first data line D1 and the second data line D2, and two adjacent sub-pixel circuits P in the same column are connected with different data lines, namely the first data line D1 and the second data line D2.

Referring to fig. 1, the display panel includes a plurality of scan lines G ("numerals following G" indicate numbers only), each of which is electrically connected to a row of sub-pixel circuits, and data signals on respective data lines are written to the sub-pixel circuits P corresponding to the row in a stage in which the scan lines G transmit enable signals (scan signals). In this embodiment, since two adjacent sub-pixel circuits P in the same column are connected to different data lines, in the stage of writing data into the x-th row of sub-pixel circuits, data writing into the x-1-th row of sub-pixel circuits can be continued, so that the writing time of data signals can be increased, and the problem of uneven display of high-frequency and high-resolution products can be improved.

Further, when the arrangement modes of the sub-pixel circuits at two sides of each data line are different, the layout (layout) environments where the first data line D1 and the second data line D2 are located are different, so that the loads (loading) of the first data line D1 and the second data line D2 are different, and the loss amounts on the first data line D1 and the second data line D2 are different. At this time, if the same row of sub-pixel circuits are all connected to the first data line D1 or the second data line D2, for example, the odd row of sub-pixel circuits are all connected to the first data line D1, the even row of sub-pixel circuits are all connected to the second data line D2 (or the odd row of sub-pixel circuits are all connected to the second data line D2, and the even row of sub-pixel circuits are all connected to the first data line D1), the load of the first data line D1 and the load of the second data line D2 are different, so that the loss amount of the write data signals of the two adjacent rows of sub-pixel circuits is different, the display uniformity of the two adjacent rows of sub-pixels is poor, and the cross-stripe problem occurs in the display effect. In this embodiment, by setting two adjacent sub-pixel circuits P in the same row to connect the first data line D1 and the second data line D2 respectively, the loss of the data signals written in the two adjacent rows of sub-pixel circuits can be balanced, the display uniformity of the two adjacent rows of sub-pixels can be improved, and the cross stripe phenomenon can be weakened under the condition that the loads of the first data line D1 and the second data line D2 are different.

Further, the first multiplexing circuit 10 is disposed corresponding to the first pixel circuit group 20, and is configured to write data signals to the data lines corresponding to the first pixel circuit group 20 in a time-sharing manner under the control of the row selection signal outputted by the row selection control line SW and the column selection signal outputted by the column selection control line MUX. As shown in fig. 1, in the present embodiment, the first multiplexing circuit 10 includes a first selection module 11 and a second selection module 12 connected in an upper-lower stage, where a data signal input terminal S of the first selection module 11 is used for electrically connecting with one data signal channel of the driving chip to receive a data signal; the output end of the first selection module 11 is electrically connected with the input end of the second selection module 12 in a one-to-one correspondence manner, and the first selection module 11 can transmit a data signal to one of the input ends of the second selection module 12 under the control of a row selection signal (column selection signal); the output end of the second selection module 12 is electrically connected to the data line corresponding to the first pixel circuit group 20 in a one-to-one correspondence manner, the second selection module 12 can output the data signal received by the input end to one of the data lines corresponding to the input end under the control of the column selection signal (row selection signal), so that the first multiplexing selection circuit 10 can write the data signal into the data line corresponding to the first pixel circuit group 20 in a time sharing manner under the control of the row selection signal and the column selection signal, and the data signal on each data line can be written into the corresponding sub-pixel circuit P in the stage of outputting the enable signal by the scanning line G.

Because the first pixel circuit group 20 includes at least two columns of sub-pixel circuits, and one first pixel circuit group 20 corresponds to one data signal input terminal S, compared with a column of sub-pixel circuits corresponding to one data signal input terminal S, the technical scheme of the embodiment of the invention can greatly reduce the number of data signal channels of the driving chip and reduce the cost.

In the first multiplexing circuit 10, the first selection module 11 may be controlled by a row selection signal output by the row selection control line SW, the second selection module 12 may be controlled by a column selection signal output by the column selection control line MUX, the first selection module 11 may be controlled by a column selection signal output by the column selection control line MUX, the second selection module 12 may be controlled by a row selection signal output by the row selection control line SW, fig. 1 illustrates the structure of the first multiplexing circuit 10 by taking only the control of the first selection module 11 by the row selection signal output by the row selection control line SW, and the second selection module 12 is controlled by the column selection signal output by the column selection control line MUX as an example.

It should be noted that, for the multiple columns of sub-pixel circuits in the display panel, at least part of the sub-pixel circuits P may be divided into multiple first pixel circuit groups 20, and the first multiplexing circuits 10 may be correspondingly provided, which is not limited in the embodiment of the present invention. It should be noted that the display panel may further include a multiplexing circuit with other functions, for example, a multiplexing circuit for time-sharing transmission of touch signals, which is not limited in the embodiment of the present invention.

The structure of the first multiplexing circuit 10 will be described in further detail below on the basis of the above-described embodiments.

As one possible implementation manner, fig. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, referring to fig. 2, optionally, the first selection module 11 includes a first selection unit 111, and the second selection module 12 includes two second selection units 121; the display panel comprises two row selection control lines SW and n column selection control lines MUX; n is more than or equal to 2, and n is a positive integer; the first selection unit 111 is electrically connected to two row selection control lines SW and two second selection units 121; the first selection unit 111 is configured to output the data signal received at the data signal input terminal S to one of the two second selection units 121 under the control of the row selection signal output from one row selection control line SW; the second selecting unit 121 is electrically connected to n column selection control lines MUX and n data lines connected to n sub-pixel circuits P located in the same row in the first pixel circuit group 20; the second selecting unit 121 is used for outputting a data signal to one of the n data lines under the control of a column selection signal output from one column selection control line MUX.

In this embodiment, the first selection module 11 is controlled by a row selection signal output from the row selection control line SW, and the second selection module 12 is controlled by a column selection signal output from the column selection control line MUX.

The first selection unit 111 is electrically connected to the two row selection control lines SW and the two second selection units 121, and the first selection unit 111 can output the data signal received by the data signal input terminal S to one of the two second selection units 121 under the control of the row selection signal output by one row selection control line SW, so that the first selection unit 111 can output the data signal to the two second selection units 121 in a time-sharing manner by controlling the two row selection control lines SW to output the enable signal in a time-sharing manner. Specifically, the two row selection control lines SW may control the first selection unit 111 to perform data writing to the data lines connected to the odd-numbered row and the even-numbered row sub-pixel circuits, respectively.

The two second selecting units 121 in the second selecting module 12 may correspond to n data lines connected to the sub-pixel circuits in odd and even rows, each second selecting unit 121 is electrically connected to n column selecting control lines MUX and n data lines connected to n sub-pixel circuits P in the same row in the first pixel circuit group 20, the second selecting unit 121 receiving the data signals may output the data signals to one of the n data lines under the control of the column selecting signal outputted from one column selecting control line MUX, and the second selecting unit 121 may write the data signals to the n data lines connected to the n sub-pixel circuits P in the same row in a time sharing manner by controlling the n column selecting control lines MUX to output the enabling signal in a time sharing manner. Illustratively, fig. 2 illustrates that a row of sub-pixel circuits of the first pixel circuit group 20 includes two sub-pixel circuits P, and the number of column selection control lines MUX is 2 accordingly.

Fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 3, the first selection unit 111 includes two first transistors T1; the gate of the first transistor T1 is electrically connected to a row selection control line SW, and the first electrode of the first transistor T1 is electrically connected to the data signal input terminal S of the first selection module 11; the second selection unit 121 includes n second transistors T2; the grid electrode of each second transistor T2 is respectively and electrically connected with a column selection control line MUX, the first poles of n second transistors T2 are respectively and electrically connected with the second poles of the same first transistor T1, and the second poles of n second transistors T2 are respectively and electrically connected with n data lines connected with n sub-pixel circuits P in the same row in the first pixel circuit group 20 in a one-to-one correspondence manner.

For example, fig. 3 illustrates an example in which one row of sub-pixel circuits in the first pixel circuit group 20 includes two sub-pixel circuits P, and accordingly, the second selecting unit 121 includes two second transistors T2, and the number of column selecting control lines MUX is two.

In fig. 3, the sub-pixel circuit Pxy represents an x-th row and a y-th column sub-pixel circuit, for example, P21 represents a 2-th row and a 1-th column sub-pixel circuit; d1-n represents a first data line on the first side of the n-th column subpixel circuit, e.g., D1-2 represents a first data line on the first side of the 2-th column subpixel circuit; d2-n represents a second data line on a second side of the nth column subpixel circuit, e.g., D2-3 represents a second data line on a second side of the 3 rd column subpixel circuit; the Arabic numerals behind the scan line G, the column selection control line MUX, the row selection control line SW, the second selection unit 121, the first transistor T1, the second transistor T2, and the data signal input terminal S are only numbers, and have no substantial meaning, and the following reference numerals are the same and are not repeated.

As shown in fig. 3, the first poles of the first transistors T1-1 and T1-2 are electrically connected to the data signal writing terminal S1, the second transistors T2-1 and T2-4 form a second selecting unit 121-1, the first poles of the second transistors T2-1 and T2-4 are electrically connected to the second pole of the first transistor T1-1, the output terminal of the second transistor T2-1 is electrically connected to a first data line D1 (e.g., a first data line D1-1) connected to the first column sub-pixel circuits (e.g., sub-pixel circuits P11 and P31) of the odd row in the first pixel circuit group 20, the output terminal of the second transistor T2-4 is electrically connected to a second data line D2 (e.g., a second data line D2-2) connected to the second column sub-pixel circuits (e.g., sub-pixel circuits P12 and P32) of the odd row in the first pixel circuit group 20, and the second transistor T2-4 are respectively connected to the gate electrode of the second transistor T2-4 and the second data line MUX2; similarly, the second transistors T2-2 and T2-3 constitute another second selection unit 121-2, the first poles of the second transistors T2-2 and T2-3 are electrically connected to the second poles of the first transistors T1-2, the output ends of the second transistors T2-2 are electrically connected to the second data line D2 (e.g., the second data line D2-1) connected to the even-row first column sub-pixel circuits (e.g., the sub-pixel circuits P21 and P41) in the first pixel circuit group 20, the output ends of the second transistors T2-3 are electrically connected to the first data line D1 (e.g., the first data line D1-2) connected to the even-row second column sub-pixel circuits (e.g., the sub-pixel circuits P22 and P42) in the first pixel circuit group 20, and the gates of the first transistors T1-1 and T2 are respectively connected to the row selection control line SW1 and the row selection control line SW2.

Further, the first transistor T1 and the second transistor T2 may be P-type transistors or N-type transistors, which is not limited in the embodiment of the present invention, and fig. 3 only illustrates that the first transistor T1 and the second transistor T2 are P-type transistors.

Fig. 4 is a driving timing chart of the display panel shown in fig. 3, and in combination with fig. 3 and 4, the first transistor T1-1 is turned on at a stage when the row selection signal SW1 is at an enable level (low level) for the first time, the second transistor T2-1 and the second transistor T2-4 are turned on in turn by controlling the column selection signal MUX1 and the column selection signal MUX2 to be at an enable level in turn, so that the data signal received at the data signal input terminal S1 can be written into the first data line D1-1 when the first transistor T1-1 and the second transistor T2-1 are turned on, the data signal received at the data signal input terminal S1 is written into the second data line D2-2 when the first transistor T1-1 and the second transistor T2-4 are turned on, the scan line G1 connected to the first row sub-pixel circuit starts outputting the enable signal at any time when the row selection signal SW1 is at the enable level for the first time, and the data signal received at the first data line D1-1 can be written into the sub-pixel circuit P11, and the data signal received at the second sub-pixel circuit P2-P12. Next, in the stage that the row selection signal SW2 is at the enabling level for the first time, when the column selection signal MUX1 is at the enabling level, the data signal received by the data signal input terminal S1 is written into the second data line D2-1, when the column selection signal MUX2 is at the enabling level, the data signal received by the data signal input terminal S1 is written into the first data line D1-2, at any time when the row selection signal SW2 is at the enabling level for the first time, the scan line G2 connected to the second row of sub-pixel circuits starts outputting the enabling signal, the data signal on the second data line D2-1 is written into the sub-pixel circuit P21, the data signal on the first data line D1-2 is written into the sub-pixel circuit P22, and the data writing processes of the remaining rows of sub-pixel circuits can be analogized in sequence, which is not repeated here.

Referring to fig. 3 and 4, optionally, the row selection control lines SW include a first row selection control line (e.g., SW 1) for controlling data writing to the data lines connected to the odd-numbered row sub-pixel circuits and a second row selection control line (e.g., SW 2) for controlling data writing to the data lines connected to the even-numbered row sub-pixel circuits, and the plurality of scan lines G in the display panel may include first scan lines (G1, G3, G5, G7 … …) electrically connected to the sub-pixel circuits P located in the odd-numbered rows and second scan lines (G2, G4, G6, G8 … …) electrically connected to the sub-pixel circuits P located in the even-numbered rows; the enable signal of the ith first scan line at least partially overlaps with the ith enable signal of the first row selection control line (SW 1) and does not overlap with the (i+1) th enable signal of the first row selection control line (SW 1); the enable signal of the j-th second scan line at least partially overlaps the j-th enable signal of the second row selection control line (SW 2) and does not overlap the (j+1) -th enable signal of the second row selection control line (SW 2); wherein i is more than or equal to 1, j is more than or equal to 1, and both i and j are positive integers.

Specifically, one of the two row selection control lines (first row selection control line) is used for controlling data writing (charging) to the data line connected to the even row sub-pixel circuit, and the other row selection control line (second row selection control line) is used for controlling data writing (charging) to the data line connected to the even row sub-pixel circuit. It can be understood that the ith enable signal output by the first row selection control line is used for controlling data writing to the data line connected with the ith odd row sub-pixel circuit, and the enable signal output by the ith first scanning line is used for scanning the ith odd row sub-pixel circuit, so that the data signals on each data line can be written into the corresponding sub-pixel circuit. Similarly, by setting the enable signal of the j-th second scan line to at least partially overlap with the j-th enable signal of the second row selection control line, the sub-pixel circuits of the even-numbered rows can be charged in a combination of line charging and direct charging.

Further, since it is necessary to write a data signal to each data line to which the i+1 th odd-numbered row sub-pixel circuit is connected when the first row selection control line (SW 1) is output the i+1 th enable signal, and the i+1 th odd-numbered row sub-pixel circuit is connected to the same data line as the sub-pixel circuit in the same column of the i odd-numbered row sub-pixel circuit, it is necessary to stop the data writing to the i odd-numbered row sub-pixel circuit when (or before) the i+1 th enable signal is output from the first row selection control line (SW 1), that is, the end timing of the enable signal output from the i+1 th first scanning line is required to be before the start timing of the i+1 th enable signal output from the first row selection control line (SW 1), the enable signal of the i th first scanning line and the (i+1) th enable signal of the first row selection control line (SW 1) do not overlap. Similarly, the enable signal of the j-th second scan line and the (j+1) -th enable signal of the second row selection control line (SW 2) do not overlap.

For example, referring to fig. 3 and 4, the enable signal output from the scan line G1 partially overlaps the first enable signal output from the row selection control line SW1 and does not overlap the second enable signal output from the row selection control line SW1, and the enable signal output from the scan line G2 partially overlaps the first enable signal output from the row selection control line SW2 and does not overlap the second enable signal output from the row selection control line SW 2. Because the two adjacent rows of the same column sub-pixel circuits are connected with different data lines, the data writing phases of the two adjacent rows of the sub-pixel circuits are not affected, so that the data writing time of the sub-pixel circuit P can be increased, and the display effect is improved. As shown in fig. 4, the row selection control line SW2 outputs the enable signal for the first time, so that the data writing period of the first row sub-pixel circuit can be increased, and similarly, the data writing period of the subsequent rows of sub-pixel circuits can be increased, and the display effect can be improved.

It should be noted that, in this embodiment, only the overlap of the enable signal of the ith first scan line and the ith enable signal of the first row selection control line (SW 1) is illustrated as an example, and in other embodiments, the start time of the enable signal of the optional ith first scan line overlaps the start time of the ith enable signal of the first row selection control line (SW 1), and similarly, the start time of the enable signal of the optional jth second scan line overlaps the start time of the jth enable signal of the second row selection control line (SW 2), which is not limited in this embodiment of the present invention.

With continued reference to fig. 3, a first transistor T1 coupled to the same row of sub-pixel circuits is connected to the same row select control line SW. Illustratively, in FIG. 3, the first transistor T1-1 and the first transistor T1-3 are coupled to the same row (odd row) subpixel circuit P, both are coupled to the row select control line SW1, and the first transistor T1-2 and the first transistor T1-4 are coupled to the same row (even row) subpixel circuit P, both are coupled to the row select control line SW2. In this way, one row selection control line SW can simultaneously control the on-off states of the first transistors T1 coupled to the same row of sub-pixel circuits in different first selection units 111, so as to simplify the panel structure and reduce the frame width.

Referring to fig. 5, fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention, fig. 5 is a schematic diagram of an example in which the first pixel circuit group 20 includes three columns of sub-pixel circuits, and accordingly, each second selecting unit 121 includes three second transistors T2, and the number of column selecting control lines MUX is three. Fig. 6 is a timing chart of driving the display panel shown in fig. 5, and the driving process of the display panel shown in fig. 5 is substantially identical to that of the display panel shown in fig. 3, and will not be described again, particularly with reference to the explanation of fig. 3 and 4.

Fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 7, a second transistor T2 electrically connected to two adjacent data lines in two adjacent first pixel circuit groups 20 is optionally connected to the same column selection control line MUX.

In fig. 7, the second data line D2-2 and the first data line D1-3 are two adjacent data lines in two adjacent first pixel circuit groups 20, unlike the display panel shown in fig. 3, in this embodiment, the second transistor T2-4 electrically connected to the second data line D2-2 and the second transistor T2-5 electrically connected to the first data line D1-3 are connected to the same column selection control line MUX2, and according to the above explanation of the driving process, the arrangement is such that data writing can be performed on the adjacent second data line D2-2 and the first data line D1-3 at the same time, so that crosstalk between adjacent data lines can be reduced, accuracy of data signals can be improved, and display effect can be improved.

As another possible implementation manner, fig. 8 is a schematic structural diagram of another display panel provided by the embodiment of the present invention, referring to fig. 8, optionally, the first selection module 11 includes a first selection unit 111, and the second selection module 12 includes m second selection units 121; the display panel comprises m column selection control lines MUX and two row selection control lines SW; m is more than or equal to 2, and m is a positive integer; the first selection unit 111 is electrically connected to m column selection control lines MUX and m second selection units 121; the first selecting unit 111 is configured to output the data signal received at the data signal input terminal S to one of the m second selecting units 121 under the control of the column selection signal output by one column selection control line MUX; the second selection unit 121 is electrically connected to the two row selection control lines SW, and the first data line D1 and the second data line D2 to which the sub-pixel circuits P located in the same column in the first pixel circuit group 20 are connected; the second selection unit 121 is configured to output a data signal to the first data line D1 or the second data line D2 under control of a row selection signal output from one row selection control line SW.

In this embodiment, the first selection module 11 is controlled by a column selection signal outputted from a column selection control line MUX, and the second selection module 12 is controlled by a row selection signal outputted from a row selection control line SW.

The first selection unit 111 is electrically connected to the m column selection control lines MUX and the m second selection units 121, and the first selection unit 111 can output the data signal received by the data signal input terminal S to one of the m second selection units 121 under the control of the column selection signal output by one column selection control line MUX, so that the first selection unit 111 can output the data signal to the m second selection units 121 in a time-sharing manner by controlling the m column selection control lines MUX to output the enable signal in a time-sharing manner.

The second selecting unit 121 is electrically connected to the two row selection control lines SW and the first data line D1 and the second data line D2 connected to the sub-pixel circuits P in the same column in the first pixel circuit group 20, and the second selecting unit 121 receiving the data signal from the m second selecting units 121 may output the data signal to the first data line D1 or the second data line D2 connected to the sub-pixel circuits in the column under the control of the row selection signal output by the one row selection control line SW, so that the second selecting unit 121 may output the data signal to the first data line D1 and the second data line D2 connected to the x-th row sub-pixel circuit in the same column in a time-sharing manner by controlling the two row selection control lines SW, and further may write the data signal on the data line to the sub-pixel circuits P in the scanning state.

Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 9, optionally, the first selection unit 111 includes m first transistors T1; the grid electrode of each first transistor T1 is respectively and electrically connected with a column selection control line MUX, and the first poles of m first transistors T1 are electrically connected with the data signal input end S of the first selection module 11; the second selection unit 121 includes two second transistors T2, each of the second transistors T2 is electrically connected to one row selection control line SW, a first pole of the two second transistors T2 is electrically connected to a second pole of the same first transistor T1, and a second pole of the two second transistors T2 is electrically connected to a first data line D1 and a second data line D2 connected to the sub-pixel circuits P located in the same column in the first pixel circuit group 20, respectively.

In this embodiment, the first pixel circuit group 20 includes two columns of sub-pixel circuits, and correspondingly, the first selection unit 111 includes two first transistors T1, the second selection module 12 includes two second selection units 121, and the number of column selection control lines MUX is two.

As shown in fig. 9, the first poles of the first transistors T1-1 and T1-2 are electrically connected to the data signal writing terminal S1, the second transistors T2-1 and T2-2 form a second selecting unit 121-1, the first poles of the second transistors T2-1 and T2-2 are electrically connected to the second pole of the first transistor T1-1, the output terminal of the second transistor T2-1 is electrically connected to a first data line D1 (e.g., the first data line D1-1) connected to a first column sub-pixel circuit in the first pixel circuit group 20, the output terminal of the second transistor T2-2 is electrically connected to a second data line D2 (e.g., the second data line D2-1) connected to the column sub-pixel circuit, and the gates of the second transistors T2-1 and T2-2 are respectively connected to the row selecting control line SW1 and the row selecting control line SW2; similarly, the second transistors T2-3 and T2-4 constitute another second selection unit 121-2, the first poles of the second transistors T2-3 and T2-4 are electrically connected to the second pole of the first transistor T1-2, the output terminal of the second transistor T2-3 is electrically connected to the first data line D1 (e.g., the first data line D1-2) connected to the second column sub-pixel circuit in the first pixel circuit group 20, and the output terminal of the second transistor T2-4 is electrically connected to the second data line D2 (e.g., the second data line D2-2) connected to the sub-pixel circuit P, and the gates of the first transistors T1-1 and T1-2 are respectively connected to the column selection control line MUX1 and the column selection control line MUX2.

The driving timing shown in fig. 4 is equally applicable to the display panel shown in fig. 9. Referring to fig. 9 and 4, in a stage in which the row selection signal SW1 is at an enable level (low level) for the first time, the second transistors T2-1 and T2-4 are turned on, by controlling the column selection signal MUX1 and the column selection signal MUX2 to be at an enable level in sequence, the first transistors T1-1 and T1-2 can be turned on in sequence, so that the data signal received at the data signal input terminal S1 can be written to the first data line D1-1 when the first transistors T1-1 and T2-1 are turned on, the data signal received at the data signal input terminal S1 can be written to the second data line D2-2 when the first transistors T1-2 and T2-4 are turned on, the scan line G1 connected to the first row sub-pixel circuit starts outputting an enable signal at any time when the row selection signal SW1 is at the enable level for the first time, the data signal received at the first data line D1-1 can be written to the sub-pixel circuit P11, and the data signal received at the second data line D2-2 is written to the sub-pixel circuit P12. Next, in the stage that the row selection signal SW2 is at the enabling level for the first time, when the column selection signal MUX1 is at the enabling level, the data signal received by the data signal input terminal S1 is written into the second data line D2-1, when the column selection signal MUX2 is at the enabling level, the data signal received by the data signal input terminal S1 is written into the first data line D1-2, at any time when the row selection signal SW2 is at the enabling level for the first time, the scan line G2 connected to the second row of sub-pixel circuits starts outputting the enabling signal, the data signal on the second data line D2-1 is written into the sub-pixel circuit P21, the data signal on the first data line D1-2 is written into the sub-pixel circuit P22, and the data writing processes of the remaining rows of sub-pixel circuits can be analogized in sequence, which is not repeated here.

Similarly, since two adjacent sub-pixel circuits P in the same column are connected to different data lines, the data writing processes of the two adjacent rows of sub-pixel circuits do not affect each other, and thus the data writing stage of the first row of sub-pixel circuits (i.e., the enabling level stage of the scan line G1) can be continued until the initial time when the row selection control line SW1 outputs the enabling signal for the second time, thereby increasing the data writing time of the sub-pixel circuits P and improving the display effect. The data writing stage of the second row of sub-pixel circuits (i.e., the enabling level stage of the scan line G2) may be continued until the initial time of the second output of the enabling signal by the row selection control line SW2, so as to increase the data writing time of the sub-pixel circuits P and improve the display effect. The data writing stages of the other rows of sub-pixel circuits can be similar, and will not be described in detail herein.

With continued reference to fig. 9, optionally, a second transistor T2 coupled to the same row of sub-pixel circuits is connected to the same row select control line SW. Illustratively, in FIG. 9, the second transistor T2-1 and the second transistor T2-4 are coupled to the same row (odd row) subpixel circuit P, both are coupled to the row select control line SW1, and the second transistor T2-2 and the second transistor T2-3 are coupled to the same row (even row) subpixel circuit P, both are coupled to the row select control line SW2. In this way, one row selection control line SW can simultaneously control the on-off states of the second transistors T2 coupled to the same row of sub-pixel circuits in different second selection units 121, so as to simplify the panel structure and reduce the frame width.

Referring to fig. 10, fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention, fig. 10 illustrates that the first pixel circuit group 20 includes three columns of sub-pixels, and correspondingly, the second selecting module 12 includes three second selecting units 121, the first selecting unit 111 includes three first transistors T1, and the number of column selecting control lines MUX is three. The driving timing shown in fig. 6 is equally applicable to the display panel shown in fig. 10, and the driving process thereof can be understood with reference to the driving process of the display panel shown in fig. 9.

Fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the present invention, referring to fig. 11, optionally, the first transistors T1 coupled to two adjacent data lines in two adjacent first pixel circuit groups 20 are connected to the same column selection control line MUX.

In fig. 11, the second data line D2-2 and the first data line D1-3 are two adjacent data lines in two adjacent first pixel circuit groups 20, unlike the display panel shown in fig. 9, in this embodiment, the first transistor T1-2 electrically connected to the second data line D2 and the first transistor T1-3 electrically connected to the first data line D1-3 are connected to the same column selection control line MUX2, and according to the above explanation of the driving process, the arrangement can simultaneously write data into the adjacent second data line D2-2 and the first data line D1-3, so that crosstalk between adjacent data lines can be reduced, accuracy of data signals can be improved, and display effect can be improved.

In summary, the above embodiments provide two structures of the first multiplexing circuit, and a person skilled in the art can select the arrangement of the first multiplexing circuit according to the requirement.

Based on the same inventive concept, the embodiments of the present invention also provide a driving method of a display panel, which is used for driving the display panel provided in any of the foregoing embodiments, and the driving method can be understood in combination with the driving timing of the display panel provided in the foregoing embodiments. Fig. 12 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, referring to fig. 12, the driving method of the display panel includes the following steps:

s101, transmitting a data signal to a data signal input end of a first selection module in a plurality of first multiplexing circuits.

Specifically, each data signal channel of the driving chip transmits a data signal to each data signal input terminal.

S102, under the control of a row selection signal output by a row selection control line and a column selection signal output by a column selection control line, the first multi-path selection circuit outputs data signals received by a data signal input end of the first selection module to data lines corresponding to the first pixel circuit group in a time-sharing manner.

Specifically, when the data is written to the plurality of data lines corresponding to the first pixel circuit group in a time-sharing manner, the data signals sent by the driving chip to the data signal input end may be the same or different, and specifically, the data signals need to be determined according to the required light emitting brightness of the scanned sub-pixels. When data is written into a certain data line, the line conduction between the data line and the data signal input end is controlled by a row selection signal and a column selection signal, so that the data signal can be written into the data line. The line time-sharing conduction between the data signal input end and each data line can be controlled through the row selection signal and the column selection signal, so that the data signals received by the data signal input end are time-sharing output to each data line.

On the basis of the above embodiment, the selectable first selection module is controlled by a row selection signal output from a row selection control line, and the selectable second selection module is controlled by a column selection signal output from a column selection control line. At this time, the selectable first selection module includes a first selection unit, and the second selection module includes two second selection units; the display panel comprises two row selection control lines and n column selection control lines; n is more than or equal to 2, and n is a positive integer. Accordingly, fig. 13 is a schematic flow chart of another driving method of a display panel according to an embodiment of the present invention, referring to fig. 13, the driving method includes the following steps:

S201, transmitting a data signal to a data signal input end of a first selection module in a plurality of first multiplexing circuits.

S202, the first selection unit outputs the data signal received by the data signal input end to one of the two second selection units under the control of a row selection signal output by one row selection control line.

S203, the second selection unit outputs the data signal to one of n data lines connected to n sub-pixel circuits in the same row in the first pixel circuit group under the control of a column selection signal output by one column selection control line.

Specifically, under the control of a row selection signal output by one row selection control line, a column selection signal may be output in a time-sharing manner by different column selection control lines, so as to perform data writing on n data lines connected to n sub-pixel circuits in the same row in a time-sharing manner, and then under the control of a row selection signal output by another row selection control line, a column selection signal is output in a time-sharing manner by the column selection control line, so as to perform data writing on n data lines connected to n sub-pixel circuits in the next row in a time-sharing manner, and the specific driving process may be described with reference to fig. 3 and fig. 4.

In other embodiments, the first selection module is controlled by a column selection signal output from a column selection control line, and the second selection module is controlled by a row selection signal output from a row selection control line. At this time, the selectable first selection module includes one first selection unit, and the second selection module includes m second selection units; the display panel comprises m column selection control lines and two row selection control lines; m is more than or equal to 2, and m is a positive integer. Accordingly, fig. 14 is a schematic flow chart of another driving method of a display panel according to an embodiment of the present invention, referring to fig. 14, the driving method includes the following steps:

s301, transmitting a data signal to a data signal input end of a first selection module in a plurality of first multiplexing circuits.

S302, the first selection unit outputs the data signal received by the data signal input end to one of m second selection units under the control of a column selection signal output by one column selection control line.

S303, the second selection unit outputs the data signal to the first data line or the second data line connected with the sub-pixel circuits positioned in the same column in the first pixel circuit group under the control of the row selection signal output by one row selection control line.

Similarly, under the control of the row selection signal output by one row selection control line, the column selection signal can be output in a time-sharing manner by different column selection control lines, so as to perform data writing on n data lines connected to n sub-pixel circuits in the same row in a time-sharing manner, and then under the control of the row selection signal output by another row selection control line, the column selection signal is output in a time-sharing manner under the control of the column selection control, so as to perform data writing on n data lines connected to n sub-pixel circuits in the next row in a time-sharing manner, and the specific driving process can be described with reference to fig. 9 and fig. 4.

Referring to fig. 3 and 4, the selectable row selection control lines include a first row selection control line (SW 1) and a second row selection control line (SW 2); the display panel further includes a plurality of scan lines including first scan lines (G1, G3, G5, G7 … …) electrically connected to the sub-pixel circuits located in the odd-numbered rows and second scan lines (G2, G4, G6, G8 … …) electrically connected to the sub-pixel circuits located in the even-numbered rows; the enable signal of the ith first scan line at least partially overlaps with the ith enable signal of the first row selection control line and does not overlap with the (i+1) th enable signal of the first row selection control line; the enable signal of the j-th second scan line at least partially overlaps the j-th enable signal of the second row selection control line and does not overlap the (j+1) -th enable signal of the second row selection control line; wherein i is more than or equal to 1, j is more than or equal to 1, and both i and j are positive integers.

With reference to the description of the embodiments of the display panel, the arrangement may be such that the sub-pixel circuit is charged in a combination of line charging and direct charging, and the data writing time of the sub-pixel circuit may be increased, so as to improve the display effect, which is not described herein.

Based on the same inventive concept, the embodiment of the present invention further provides a display device, and fig. 15 is a schematic structural diagram of the display device provided by the embodiment of the present invention, where the display device 200 includes the display panel 100 provided by any one of the embodiments, so that the display device has the same beneficial effects as the display panel, and the same points can be referred to the description of the embodiment of the display panel and are not repeated herein. The display device 200 provided in the embodiment of the present invention may be a mobile phone shown in fig. 15, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A display panel, comprising: a plurality of first multiplexing circuits, a plurality of first pixel circuit groups arranged in a row direction, and a plurality of data lines;

the first pixel circuit group comprises at least two columns of sub-pixel circuits; the data lines comprise first data lines and second data lines, the first data lines are positioned on a first side of each column of the sub-pixel circuits along the row direction, the second data lines are positioned on a second side of each column of the sub-pixel circuits, and the first side and the second side are opposite sides of the sub-pixel circuits; two adjacent sub-pixel circuits in the same row are respectively connected with the first data line and the second data line, and two adjacent sub-pixel circuits in the same column are respectively connected with the first data line and the second data line;

the first multiplexing circuits are arranged in one-to-one correspondence with the first pixel circuit groups; the first multi-path selection circuit comprises a first selection module and a second selection module, the output end of the first selection module is correspondingly and electrically connected with the input end of the second selection module, and the output end of the second selection module is correspondingly and electrically connected with the data line corresponding to the first pixel circuit group;

The display panel further comprises a row selection control line and a column selection control line, and the first multi-path selection circuit is used for outputting the data signals received by the data signal input end of the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing manner under the control of the row selection signals output by the row selection control line and the column selection signals output by the column selection control line; wherein,

the first selection module comprises a first selection unit, and the second selection module comprises two second selection units; the display panel comprises two row selection control lines and n column selection control lines; n is more than or equal to 2, and n is a positive integer;

the first selection unit is electrically connected with the two row selection control lines and the two second selection units; the first selection unit is used for outputting the data signal received by the data signal input end to one of the two second selection units under the control of a row selection signal output by one row selection control line;

the second selection unit is electrically connected with n column selection control lines and n data lines connected with n sub-pixel circuits positioned in the same row in the first pixel circuit group; the second selection unit is used for outputting the data signal to one of the n data lines under the control of a column selection signal output by one column selection control line;

The first selection unit comprises two first transistors; the grid electrode of the first transistor is electrically connected with one row selection control line, and the first electrode of the first transistor is electrically connected with the data signal input end of the first selection module;

the second selection unit includes n second transistors; the grid electrode of each second transistor is electrically connected with one column selection control line, the first poles of n second transistors are electrically connected with the second poles of the same first transistor, and the second poles of n second transistors are electrically connected with n data lines connected with n sub-pixel circuits in the same row in the first pixel circuit group in a one-to-one correspondence manner;

the second transistors electrically connected with two adjacent data lines in two adjacent first pixel circuit groups are connected with the same column selection control line;

or ,

the first selection module comprises a first selection unit, and the second selection module comprises m second selection units; the display panel comprises m column selection control lines and two row selection control lines; m is more than or equal to 2, and m is a positive integer;

the first selection units are electrically connected with m column selection control lines and m second selection units; the first selection unit is used for outputting the data signal received by the data signal input end to one of m second selection units under the control of a column selection signal output by one column selection control line;

The second selection unit is electrically connected with the two row selection control lines, and the first data line and the second data line which are connected with the sub-pixel circuits positioned in the same column in the first pixel circuit group; the second selection unit is used for outputting the data signal to the first data line or the second data line under the control of a row selection signal output by one row selection control line;

the first selection unit includes m first transistors; the grid electrode of each first transistor is electrically connected with one column selection control line, and the first poles of m first transistors are electrically connected with the data signal input end of the first selection module;

the second selection unit comprises two second transistors, each second transistor is electrically connected with one row selection control line, a first pole of each second transistor is electrically connected with a second pole of the same first transistor, and a second pole of each second transistor is electrically connected with the first data line and the second data line which are connected with the sub-pixel circuits positioned in the same column in the first pixel circuit group;

The first transistors coupled to two adjacent data lines in two adjacent first pixel circuit groups are connected to the same column selection control line.

2. The display panel of claim 1, wherein the first selection unit is electrically connected to the row selection control line, and the second selection unit is electrically connected to the column selection control line while the first transistor coupled to the sub-pixel circuits of the same row is connected to the same row selection control line.

3. The display panel according to claim 1, wherein the first selection unit is electrically connected to the column selection control line, and the second selection unit is electrically connected to the row selection control line while the second transistor coupled to the sub-pixel circuits of the same row is connected to the same row selection control line.

4. A driving method of a display panel for driving the display panel according to any one of claims 1 to 3, characterized in that the driving method comprises:

the first multiplexing circuit outputs the data signals received by the data signal input end of the first selection module to the data lines corresponding to the first pixel circuit group in a time-sharing way under the control of row selection signals output by the row selection control lines and column selection signals output by the column selection control lines; wherein,

the first multiplexing circuit outputs the data signal received by the data signal input end of the first selection module to the data line corresponding to the first pixel circuit group in a time-sharing way under the control of the row selection signal output by the row selection control line and the column selection signal output by the column selection control line, and the method comprises the following steps:

the first selection unit outputs the data signal received by the data signal input end to one of the two second selection units under the control of a row selection signal output by one row selection control line;

the second selection unit outputs the data signal to one of n data lines connected with n sub-pixel circuits positioned in the same row in the first pixel circuit group under the control of a column selection signal output by one column selection control line;

or ,

the first selection unit outputs the data signal received by the data signal input end to one of m second selection units under the control of a column selection signal output by one column selection control line;

the second selection unit outputs the data signal to the first data line or the second data line connected to the sub-pixel circuits positioned in the same column in the first pixel circuit group under the control of a row selection signal output by one row selection control line.

5. The driving method according to claim 4, wherein the row selection control line includes a first row selection control line and a second row selection control line;

the display panel further comprises a plurality of scanning lines, wherein the scanning lines comprise first scanning lines and second scanning lines, the first scanning lines are electrically connected with the sub-pixel circuits positioned in the odd-numbered rows, and the second scanning lines are electrically connected with the sub-pixel circuits positioned in the even-numbered rows;

An enable signal of an ith one of the first scan lines at least partially overlaps an ith enable signal of the first row selection control line and does not overlap an (i+1) th enable signal of the first row selection control line;

the enable signal of the j-th second scanning line at least partially overlaps the j-th enable signal of the second row selection control line and does not overlap the (j+1) -th enable signal of the second row selection control line;

wherein i is more than or equal to 1, j is more than or equal to 1, and both i and j are positive integers.

6. A display device comprising the display panel of any one of claims 1-3.