CN108806586B

CN108806586B - Display panel, driving method thereof and display device

Info

Publication number: CN108806586B
Application number: CN201811003751.3A
Authority: CN
Inventors: 关琳燕; 杨康鹏; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2018-08-30
Filing date: 2018-08-30
Publication date: 2021-06-22
Anticipated expiration: 2038-08-30
Also published as: CN108806586A

Abstract

The invention discloses a display panel, a driving method thereof and a display device.A first multi-way gate is controlled by a first clock control signal to realize the control of a first data line in a first display area, a second multi-way gate is controlled by a second clock control signal to realize the control of a second data line in a second display area, and the first clock control signal is different from the second clock control signal, so that the charging conditions of the first data line and the second data line can be separately controlled, the voltage of the data signal input into the first data line and the second data line is correspondingly adjusted according to the actual detection brightness, and the display uniformity of the display panel is improved.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

With the development of display technology, the comprehensive screen has a larger screen occupation ratio and an ultra-narrow frame, and compared with a common display screen, the comprehensive screen can greatly improve the visual effect of a viewer, thereby receiving wide attention. At present, in a display device such as a mobile phone using a full-screen, in order to realize a self-timer and a call function, a front camera, a receiver, and the like are generally disposed on a front surface of the display device. In order to realize full-screen display, as shown in fig. 1, a hollow portion 110 for installing a front camera, a headphone, and other devices is generally disposed in the display panel. However, due to the existence of the hollow portion 110, the number of pixels in each column in the area 1 where the hollow portion 110 is located is less than the number of pixels in each column in the remaining area 2, so that a difference exists between loads (RC loading) of the data lines in the area 1 and the data lines in the remaining area 2, and thus, delays of the data lines in the area 1 and the area 2 during data signal transmission are different, so that voltage input to the data lines is not uniform, and a problem of non-uniform display of the display panel is caused.

Disclosure of Invention

The embodiment of the invention provides a display panel, a driving method thereof and a display device, which are used for solving the problem of uneven display in the prior art.

The embodiment of the invention provides a driving method of a display panel, wherein the display panel comprises an array substrate with at least one hollow part; the array substrate includes: a display area and a non-display area; the display area comprises a first display area and a second display area, the hollow part is located in the first display area, and the first display area comprises a plurality of first data lines; the second display area comprises a plurality of second data lines; the non-display area includes: the multi-channel clock comprises a plurality of first multi-channel gates, a plurality of second multi-channel gates, N first clock control lines, N second clock control lines and switch units which are in one-to-one correspondence with the first clock control lines; one first multiplexer is connected with M first data lines, and one second multiplexer is connected with M second data lines; all the first multi-way gates are electrically connected with the N first clock control lines; all the second multi-way gates are electrically connected with the N second clock control lines; each first clock control line is connected with a first control signal end through a corresponding switch unit, and the control end of each switch unit is connected with a second control signal end; n is more than or equal to M and more than or equal to 3 and is an integer;

the driving method includes:

in a data input stage within one frame of scanning time, loading a first control signal to the first control signal end, loading a second control signal to the second control signal end, controlling each switch unit to enable each first clock control line to load a first clock control signal, and enabling the first data line to input a corresponding data signal; loading a second clock control signal to each second clock control line simultaneously to enable the second data line to input a corresponding data signal; wherein the first clock control signal is different from the second clock control signal.

The embodiment of the invention also provides a display panel which is driven by the driving method provided by the embodiment of the invention.

An embodiment of the present invention further provides a display device, including: the driving device provided by the embodiment of the invention and the display panel provided by the embodiment of the invention.

The invention has the following beneficial effects:

the display panel, the driving method thereof and the display device provided by the embodiment of the invention control the first multi-way gate through the first clock control signal to realize the control of the first data line in the first display area, control the second multi-way gate through the second clock control signal to realize the control of the second data line in the second display area, and the first clock control signal is different from the second clock control signal, so that the charging conditions of the first data line and the second data line can be separately controlled, the voltage of the data signal input into the first data line and the second data line is correspondingly adjusted according to the actual detection brightness, and the display uniformity of the display panel is improved.

Drawings

FIG. 1 is a schematic diagram of a display panel in the prior art;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 3 is a second schematic structural diagram of a display panel according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 5 is a second schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 6 is a third schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 7 is a timing diagram of a circuit according to an embodiment of the present invention;

FIG. 8 is a second timing diagram of the circuit according to the second embodiment of the present invention;

FIG. 9 is a third timing diagram of the circuit according to the embodiment of the present invention;

FIG. 10 is a fourth timing diagram of the circuit according to the present invention;

FIG. 11 is a fifth timing diagram of the circuit according to the present invention;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a display panel, a driving method thereof and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the thickness and shape of the respective layers in the drawings do not reflect the true scale of the display panel, and are only for the purpose of schematically illustrating the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 2 and 3, the display panel according to the embodiment of the invention may include an array substrate 100 having at least one hollow portion 110. The array substrate 100 includes: a display area AA and a non-display area BB; the non-display area may surround the display area, and fig. 2 and 3 only illustrate the non-display area indicated by a dashed line BB as an example. The display area AA includes a first display area AA _1 and a second display area AA _2, the hollow portion 110 is located in the first display area AA _1, and the first display area AA _1 includes a plurality of first data lines D1; the second display area aa _2 includes a plurality of second data lines D2. The non-display area BB includes: a plurality of first multiplexers 210, a plurality of second multiplexers 220, N first clock control lines CK1_ N (N is more than or equal to 1 and less than or equal to N and is an integer), N second clock control lines CK2_ N, and switch units 230_ N corresponding to the first clock control lines CK1_ N one by one; wherein, a first multiplexer 210 is connected to the M first data lines D1, and a second multiplexer 220 is connected to the M second data lines D2; all the first multiplexers 210 are electrically connected to the N first clock control lines CK1 — N; all the second multiplexers 220 are electrically connected to the N second clock control lines CK2 — N; each first clock control line CK1_ n is connected to the first control signal terminal V1 through the corresponding switch unit 230_ n, and the control terminal of each switch unit 230_ n is connected to the second control signal terminal V2; n is not less than M is not less than 3 and is an integer.

In a specific implementation, in the embodiment of the present invention, as shown in fig. 2 to fig. 6, the display area AA may further include: a plurality of gate lines G _ K (K is an integer greater than or equal to 1 and less than or equal to K, where K is the total number of gate lines in the display panel, where K is 6 in fig. 2 to 5, and K is 3 in fig. 6). Also, the first and second display areas aa _1 and aa _2 may further include: a plurality of pixels PX arranged in an array; wherein each pixel PX may include: y different color sub-pixels arranged in sequence; y is not less than 3 and is an integer. The sub-pixels in the same row in the first display area aa _1 and the second display area aa _2 are controlled by the same row of gate lines G _ k. And one first data line D1 is connected to a column of sub-pixels in the first display area aa _1, and one second data line D2 is connected to a column of sub-pixels in the second display area aa _ 2.

Further, in implementation, as shown in fig. 4 and 5, Y may be set to 3, and the pixel PX may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B sequentially arranged along the first direction F1. Alternatively, as shown in fig. 6, Y may be set to 4, and the pixel PX may include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W, which are sequentially arranged along the first direction F1. Of course, Y may be set to other values, which need to be designed according to the actual application environment, and is not limited herein.

Various embodiments of the hollow portion 110 can be implemented, and the following description will explain the embodiment of the hollow portion 110 in the detailed implementation. In particular implementation, in some possible embodiments, as shown in fig. 2, the first display area aa _1 and the second display area aa _1 are arranged along a first direction F1; each of the first data lines D1 and each of the second data lines D2 extend along the second direction F2, i.e., each of the first data lines D1 and the second data lines D2 is a straight line extending along the second direction F2. The hollow portion 110 is disposed at an edge of one side of the first data line D1 deviating from the first multiplexer 210 in the array substrate 110; the first direction F1 is perpendicular to the second direction F2.

In other possible embodiments, in practical implementation, as shown in fig. 3, the first display area aa _1 and the second display area aa _2 are arranged along the first direction F1; the first display area aa _1 surrounds the hollow portion 110, and the first data line D1 may include: a regular part extending in the second direction F2 and an irregular part located within the first display area aa _1 around the hollowed-out part 110; wherein the regular and irregular parts of the same first data line D1 are electrically connected; each of the second data lines D2 extends in the second direction F2; the first direction F1 is perpendicular to the second direction F2. Also, the first direction F1 may be a row direction of the pixels PX, and the second direction F2 may be a column direction of the pixels PX; or conversely, the first direction F1 may be a column direction of the pixels PX, and the second direction F2 may be a row direction of the pixels PX. In practical applications, the first direction and the second direction may be determined according to practical application environments, and are not limited herein.

Since the hollow portion 110 is disposed in the first display area aa _1 such that the number of sub-pixels to which the first data line D1 is electrically connected is less than the number of sub-pixels to which the second data line D2 is electrically connected, the load of the first data line D1 is different from the load of the second data line D2, which causes a delay in transmitting a data signal by the first data line D1 to be different from a delay in transmitting a data signal by the second data line D2, and a pixel voltage input to a sub-pixel to which the first data line D1 is electrically connected is different from a pixel voltage input to a sub-pixel of the second data line D2, resulting in a problem of display non-uniformity. For example, the pixel voltage input to the sub-pixel to which the first data line D1 is electrically connected is greater than the pixel voltage input to the sub-pixel of the second data line D2, resulting in the luminance of the first display region being greater than the luminance of the second display region. Therefore, in order to improve the brightness uniformity of the first and second display areas aa _1 and aa _2, the embodiment of the invention provides a driving method for improving the display uniformity.

The driving method of the display panel provided by the embodiment of the invention can comprise the following steps: in the data input stage within one frame of scanning time, a first control signal is loaded to the first control signal terminal V1, a second control signal is loaded to the second control signal terminal V2, and each switch unit 230_ n is controlled to load a first clock control signal to each first clock control line CK1_ n, so that the corresponding data signal is input to the first data line D1; simultaneously, a second clock control signal is loaded to each second clock control line CK2_ n, so that a corresponding data signal is input to the second data line D2; wherein the first clock control signal is different from the second clock control signal. And, the first multiplexer may operate under the control of an active level of the first clock control signal to make the first data line input a corresponding data signal. The second multiplexer may operate under control of an active level of the second clock control signal to cause the second data line to input the corresponding data signal.

In the driving method of the display panel provided by the embodiment of the present invention, the first multi-way gate is controlled by the first clock control signal to control the first data line in the first display area, the second multi-way gate is controlled by the second clock control signal to control the second data line in the second display area, and the first clock control signal is different from the second clock control signal, so that the charging conditions of the first data line and the second data line can be separately controlled, and the voltages of the data signals input to the first data line and the second data line are correspondingly adjusted according to the actually detected brightness, thereby improving the display uniformity of the display panel.

In the embodiment of the present invention, the array substrate may further include a substrate on which the first data lines and the second data lines are disposed. The substrate may be a glass substrate, a flexible substrate, a silicon substrate, or the like, and is not limited thereto. When the display panel is applied to a display device, a camera, an earpiece, and the like are generally disposed, and therefore, in order to dispose the camera, the earpiece, and the like, the hollow portion may be a hollow region of the substrate. In an actual manufacturing process, a cutting mode is adopted to remove a region corresponding to the hollowed-out part in the substrate base plate to form the hollowed-out region, so that the display device is provided with a camera, a receiver and other devices. Alternatively, the substrate may be cut away, and the area corresponding to the hollow portion may be made transparent by avoiding the wiring on the substrate.

In specific implementation, in the embodiment of the present invention, as shown in fig. 2 to 6, the display panel may further include: a plurality of first source input lines S1_ I (I is an integer greater than or equal to 1 and less than or equal to I, I is the total number of the first source input lines in the display panel; where I is 2 in fig. 2 to 5, and I is 1 in fig. 6), and a plurality of second source input lines S2_ J (J is an integer greater than or equal to 1 and less than or equal to J, J is the total number of the second source input lines in the display panel; where J is 2 in fig. 2 to 5, and J is 1 in fig. 6); wherein, one first source input line S1 — i is connected to the M first data lines D1 through one first multiplexer 210; a second source input line S2_ j is connected to the M second data lines D2 through a second multiplexer 220.

Further, in implementation, in the embodiment of the present invention, M may be 3; one first multiplexer 210 may be electrically connected to the first data lines D1 corresponding to the red, green and blue sub-pixels R, G and B in one pixel PX, and one second multiplexer 220 may be electrically connected to the second data lines D2 corresponding to the red, green and blue sub-pixels R, G and B in one pixel PX. Alternatively, in practical implementation, as shown in fig. 4 and fig. 5, in the embodiment of the present invention, two adjacent first multiplexers 210 correspond to two adjacent pixels PX; one of the first multiplexers 210 is electrically connected to the first data lines D1 corresponding to the red sub-pixels R, the blue sub-pixels B, and the green sub-pixels G in the odd-numbered columns of the adjacent 2 pixels PX. Another first multiplexer 210 is electrically connected to the first data lines D1 corresponding to the red, blue and green sub-pixels R, B and G in the even-numbered columns of the adjacent 2 pixels PX. Two adjacent second multiplexers 220 correspond to two adjacent pixels PX; one of the second multiplexers 220 is electrically connected to the second data lines D2 corresponding to the red sub-pixels R, the blue sub-pixels B, and the green sub-pixels G in the odd-numbered columns of the adjacent 2 pixels PX. Another second multiplexer 220 is electrically connected to the second data lines D2 corresponding to the red, blue and green sub-pixels R, B and G in the even-numbered columns of the adjacent 2 pixels PX.

In practical implementation, in an embodiment of the present invention, the first multiplexer 210 may include: m first switching elements in one-to-one correspondence with the M first data lines D1, each first switching element including at least one third transistor M3; the first data line D1 is electrically connected to the corresponding first source input line S1_ i through the corresponding third transistor M3, and the gate of the third transistor M3 is electrically connected to one first clock control line. And, the second multiplexer 220 may include: m second switching elements in one-to-one correspondence with the M second data lines D2, each second switching element including at least one fourth transistor M4; the second data line D2 is electrically connected to the corresponding second source input line S2_ j through the corresponding fourth transistor M4, and the gate of the fourth transistor M4 is electrically connected to one second clock control line.

Further, in practical implementation, in the embodiment of the present invention, as shown in fig. 4 and fig. 5, the first switching element may include a third transistor M3, and the second switching element may include a fourth transistor M4, so that N ═ M, that is, one first clock control line may correspond to one first data line connected to each first multiplexer 210. One second clock control line corresponds to one second data line connected to each second multiplexer 220. Also, the third transistor M3 may be provided as an N-type transistor, and the fourth transistor M4 may be provided as an N-type transistor, which may be turned on under the control of a high-level signal and turned off under the control of a low-level signal, so that the active levels of the first and second clock control signals may be set to a high level. Alternatively, the third transistor M3 may be a P-type transistor, and the fourth transistor M4 may be a P-type transistor, which may be turned on by a low-level signal and turned off by a high-level signal, so that the active levels of the first and second clock control signals may be set to a low level.

Alternatively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6, the first switching element may include two third transistors M3. This makes it possible to make N2M so that the first multiplexer 210 is connected to 2M first clock control lines CK1 — N. One of the two third transistors M3, M3 may be an N-type transistor, and the other third transistor M3 may be a P-type transistor. The N-type third transistor M3 in the same first multiplexer 210 is connected to the first clock control lines CK1_1 to CK1_4, respectively, and the P-type third transistor M3 is connected to the first clock control lines CK1_5 to CK1_8, respectively. CK1_1 and CK1_5 have the same period and opposite phases; CK1_2 is the same period and opposite in phase to CK1_ 6; CK1_3 is the same period and opposite in phase as CK1_ 7; CK1_4 is the same period and opposite in phase as CK1_ 8. The second switching element may include two fourth transistors M4 to connect the second multiplexer 220 with the 2M second clock control lines CK2 — n. One of the two fourth transistors M4, M4 may be an N-type transistor, and the other one of the two fourth transistors M4 may be a P-type transistor. The N-type fourth transistor M4 in the same second multiplexer 220 is connected to the second clock control lines CK2_1 to CK2_4, respectively, and the P-type fourth transistor M4 is connected to the second clock control lines CK2_5 to CK2_8, respectively. CK2_1 and CK2_5 have the same period and opposite phases; CK2_2 is the same period and opposite in phase to CK2_ 6; CK2_3 is the same period and opposite in phase as CK2_ 7; CK2_4 is the same period and opposite in phase as CK2_ 8.

Further, in implementation, in the driving method provided by the embodiment of the present invention, the periods of the first clock control signal and the second clock control signal may be made the same. This enables the first multiplexer to operate under the control of the active level of the first clock control signal to transmit the data signal to the M first data lines to which it is connected. And operating the second multiplexer under the control of the active level of the second clock control signal to transmit the data signal to the M second data lines to which it is connected.

In practical implementation, in the embodiment of the invention, the voltage values of the active levels of the second clock control signals can be the same and the holding time durations can be the same within one frame scanning time. Further, as shown in fig. 7 and 8, the first clock control signal CK1_ n represents a signal applied to the first clock control line CK1_ n, and the second clock control signal CK2_ n represents a signal applied to the second clock control line CK2_ n.

In a specific implementation, as shown in fig. 7, the voltage value VGH1 of the active level of the first clock control signal ck1_ n may be made smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n. This makes it possible to make the degree of opening of the third transistor smaller than that of the fourth transistor, so that the pixel voltage input into the sub-pixel to which the first data line D1 is connected can be lowered, so that the luminance of the first display region as a whole can be lowered, and the luminance of the first display region and the second display region can be made uniform.

In particular, as shown in fig. 8, the duration t1 of the active level of the first clock control signal ck1_ n may be made shorter than the duration t2 of the active level of the second clock control signal ck2_ n. This makes it possible to make the on time of the third transistor shorter than that of the fourth transistor, so that the pixel voltage input to the sub-pixel to which the first data line D1 is connected can be lowered, which makes it possible to lower the luminance of the first display region as a whole, so that the luminance of the first display region and the second display region can be made uniform.

In particular, in the embodiment of the present invention, a frame scan time includes at least one data input stage; in the same data input stage, the voltage values of the effective levels of the first clock control signals are the same, and the maintaining time lengths are the same; and at least one of the voltage value and the duration of the active level of the same first clock control signal is different in different data input phases. Therefore, the brightness of the first display area is approximately the same as that of the second display area by adjusting at least one of the voltage value and the maintaining time length of the effective level of the first clock control signal, and the display uniformity is improved.

In particular, it is possible to make one frame scan time include one data input stage. In this way, in one frame of scanning time, the voltage values of the effective levels of the first clock control signals are the same and the maintaining time lengths are the same. Alternatively, in practical applications, the data signal output from the driving IC (Integrated Circuit) is sequentially input to the sub-pixels through the multiplexer and the data line, and the attenuation of the pixel voltage input to the sub-pixel closer to the first multiplexer is different from the attenuation of the pixel voltage input to the sub-pixel farther from the first multiplexer, so that the display luminance in the first display region may be non-uniform. In order to further improve the display uniformity of the first display region, in an implementation, the scanning time of one frame may include at least two data input stages. In the same data input stage, the voltage values of the effective levels of the first clock control signals are the same and the maintaining time lengths are the same; in different data input stages, at least one of a voltage value and a sustain period of an active level of the same first clock control signal is different. Wherein, a frame scanning time can comprise two, three or four data input stages. The specific number of the data input stages can be designed and determined according to the actual application environment, and is not limited herein. Therefore, the brightness uniformity of the first display area can be improved by adjusting the magnitude of at least one of the voltage value and the duration of the effective level of the same first clock control signal in different data input stages. Specifically, when the one-frame scanning time includes a plurality of consecutive data input phases, the voltage value of the active level of the first control signal may be made different in different data input phases. Of course, when the scanning time of one frame includes a plurality of consecutive data input phases, the duration of the active level of the second control signal in different data input phases may be different. This is determined by design according to the actual application environment, and is not limited herein.

The following description will be made by taking an example in which one frame scan time includes one data input stage.

In some possible embodiments, the description is made in conjunction with fig. 2 to 4 and fig. 7. In practical implementation, as shown in fig. 7, the voltage value VGH1 of the active level of the first clock control signal ck1_ n is smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n, so that the luminance of the first display area can be reduced, the luminance of the first display area is approximately the same as the luminance of the second display area, and the display uniformity is improved.

As shown in fig. 2 to 4 and fig. 7, the second control signal terminal V2 may include: and a second sub control signal terminal V2_ n in one-to-one correspondence with each switching element 230_ n. The switching unit 230_ n may include: a first transistor M1; the gate of the first transistor M1 is connected to the corresponding second sub-control signal terminal V2_ n, the first pole of the first transistor M1 is connected to the first control signal terminal V1, and the second pole of the first transistor M1 is connected to the corresponding first clock control signal terminal CK1_ n. Specifically, the first transistor M1 may be an N-type transistor, and the active level of the second sub control signal may be set to a high level. Alternatively, the first transistor may be a P-type transistor, and the active level of the second sub-control signal may be set to a low level.

In the driving method provided in the embodiment of the present invention, loading the second control signal to the second control signal terminal may specifically include:

loading a second sub control signal having the same signal timing as the second clock control signal to each second sub control signal terminal V2_ n; wherein a second sub-control signal corresponds to a signal timing of a second clock control signal.

Specifically, as shown in fig. 7, the second sub-control signal V2_ n loaded by the second sub-control signal terminal V2_ n corresponds to the signal timing of the second clock control signal ck2_ n. That is, the second sub-control signal v2_1 corresponds to the signal timing of the second clock control signal ck2_1, the second sub-control signal v2_2 corresponds to the signal timing of the second clock control signal ck2_2, and the second sub-control signal v2_3 corresponds to the signal timing of the second clock control signal ck2_ 3.

Specifically, as shown in fig. 7, the duration of the active level of the first control signal v1 is the same and not less than one line scanning time; and the voltage value VGH3 of the active level of the first control signal v1 is less than the voltage value VGH2 of the active level of the second clock control signal. This makes it possible to make the voltage value VGH1 of the active level of the first clock control signal ck1_ n smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n.

In addition, in the implementation, as shown in fig. 7, each of the second sub-control signals v2_ n may be the same as the corresponding second clock control signal ck2_ n. Further, as shown in fig. 4, a second sub control signal terminal V2_ n, which is the same as the load signal, may be electrically connected to the second clock control line CK2_ n. Therefore, signal ends and wiring can be saved, and the occupied space of the non-display area is reduced.

Generally, one frame of scanning time includes a plurality of one-line scanning times, and the driving method provided by the embodiment of the invention is described below with reference to fig. 4 and 7 by taking the gate-on signals G _1 to G _3 applied to the gate lines G _1 to G _3 as an example.

In the first row scanning time T _1, a gate-on signal G _1 is applied to the gate line G _1, so that the thin film transistors in the sub-pixels in the first row are all turned on. When the gate line G _1 is applied with the gate-on signal G _1, a voltage Vdata1 is applied to each of the first and second source input lines S1_ i and S2_ j, respectively, a first control signal V1 is applied to the first control signal terminal V1, and a second clock control signal CK2_ n is applied to the second clock control line CK2_ n, and only when the second clock control signal CK2_1 is at a high level, the first transistor M1 and the fourth transistor M4 connected to the second clock control line CK2_1 are controlled to be turned on, and the turned-on fourth transistor M4 supplies the data signal applied to the second source input line S2_ j to the pixel electrode in the first row of red subpixels R in the second display region, so that the red subpixels R are charged with the voltage Vdata 1. The turned-on first transistor M1 supplies the first control signal v1 to the first clock control line CK1_1, causing the first clock control line CK1_1 to load the first clock control signal CK1_ 1. The first clock control signal CK1_1 controls the third transistor M3 connected to the first clock control line CK1_1 to turn on to supply the data signal loaded on the first source input line S1_ i to the pixel electrode of the first row of red subpixels R in the first display region, so that the red subpixels R are charged with the voltage Vdata 2.

Similarly, only when the second clock control signal CK2_2 is at a high level, the first transistor M1 and the fourth transistor M4 connected to the second clock control line CK2_2 are controlled to be turned on, so that the voltage Vdata1 can be charged to the pixel electrode in the first row of green sub-pixels G in the second display region, and the voltage Vdata2 can be charged to the pixel electrode in the first row of green sub-pixels G in the first display region. And, only when the second clock control signal CK2_3 is at a high level, the first transistor M1 and the fourth transistor M4 controlling the connection of the second clock control line CK2_3 are turned on, so that the voltage Vdata1 may be charged to the pixel electrode in the first row of blue subpixels B in the second display region, and the voltage Vdata2 may be charged to the pixel electrode in the first row of blue subpixels B in the first display region.

Similarly, in the second row scanning time T _2, the gate line G _2 is loaded with the gate turn-on signal G _2, so that the thin film transistors in the sub-pixels in the second row are turned on, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the first display region are respectively charged with Vdata2, and the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the second display region are respectively charged with Vdata 1. And in the third row scanning time T _3, loading a gate turn-on signal G _3 to the gate line G _3 to turn on the thin film transistors in the sub-pixels in the third row, so that the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the first display region are respectively charged with Vdata2, and the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the second display region are respectively charged with Vdata 1.

Since the voltage value VGH1 of the effective level of the first clock control signal ck1_ n is less than the voltage value VGH2 of the effective level of the second clock control signal ck2_ n, Vdata2< Vdata1 can be provided, so that the brightness of the first display area can be reduced by adjusting the voltage of VGH1, the brightness of the first display area is approximately the same as that of the second display area, and the display uniformity is improved.

In other possible embodiments, the description is made with reference to fig. 5 and 8. In practical implementation, as shown in fig. 8, the duration t1 of the active level of the first clock control signal ck1_ n is shorter than the duration t2 of the active level of the second clock control signal ck2_ n, so that the luminance of the first display area is reduced, the luminance of the first display area is approximately the same as the luminance of the second display area, and the display uniformity is improved.

In practical implementation, in the embodiment of the present invention, as shown in fig. 5, the first control signal terminal V1 may include: the first sub control signal terminals V1_ n correspond to the respective switch units 230_ n one to one. The switching unit 230_ n may include: a second transistor M2; the gate of the second transistor M2 is connected to the second control signal terminal V2, the first pole of the second transistor M2 is connected to the corresponding first sub-control signal terminal V1_ n, and the second pole of the second transistor M2 is connected to the corresponding first clock control line CK1_ n. Specifically, the second transistor M2 may be an N-type transistor, and the active level of the second control signal may be set to a high level. Alternatively, the second transistor may be a P-type transistor, and the active level of the second control signal may be set to a low level.

In the driving method provided in the embodiment of the present invention, loading the second control signal to the first control signal terminal may specifically include:

loading a first sub-control signal V1_ n having the same signal timing as that of each second clock control signal to each first sub-control signal terminal V1_ n; wherein, a first sub-control signal v1_ n corresponds to the signal timing of a second clock control signal ck2_ n. Specifically, as shown in fig. 8, the first sub-control signal v1_1 corresponds to the signal timing of the second clock control signal ck2_1, the first sub-control signal v1_2 corresponds to the signal timing of the second clock control signal ck2_2, and the first sub-control signal v1_3 corresponds to the signal timing of the second clock control signal ck2_ 3.

In particular, as shown in fig. 8. The order of occurrence of the active levels of the second control signal V2 corresponds one-to-one to the order of occurrence of the active levels of all the second clock control signals ck2_ n. And the sustain duration t3 of the active level of the second control signal v2 is less than the sustain duration t2 of the active level of the second clock control signal ck2 — n.

Further, each of the first sub-control signals may be made identical to the corresponding second clock control signal. Further, as shown in fig. 5, the first sub-control signal terminal V1_ n, which is the same as the load signal, may be electrically connected to the first clock control signal line CK1_ n. Therefore, signal ends and wiring can be saved, and the occupied space of the non-display area is reduced.

Next, referring to fig. 5 and 8, a driving method provided by an embodiment of the invention will be described by taking an example of applying gate-on signals G _1 to G _3 to gate lines G _1 to G _ 3.

In the first row scanning time T _1, a gate-on signal G _1 is applied to the gate line G _1, so that the thin film transistors in the sub-pixels in the first row are all turned on. When the gate line G _1 is applied with the gate-on signal G _1, the first source input line S1_ i and the second source input line S2_ j are applied with a voltage Vdata1, respectively, and the first sub-control signal terminal V1_ n is applied with a first control signal V1_ n, respectively, the second control signal terminal V2 is applied with a second control signal V2, and the second clock control signal CK2_ n is applied with a second clock control signal CK2_ n, only when the second clock control signal CK2_1 is at a high level, the fourth transistor M4 connected to the second clock control line CK2_1 is controlled to be turned on, and the turned-on fourth transistor M4 supplies the data signal applied to the second input line source S2_ j to the pixel electrode in the first row of red subpixels R in the second display region, so that the red subpixels R are charged with the voltage Vdata 1. When the second control signal v2 is at a high level, the second transistor M2 is controlled to be turned on to provide the first sub-control signal v1_ n to the first clock control line CK1_ n, so that the first clock control line CK1_ n is loaded with the first clock control signal CK1_ n. The first clock control signal CK1_1 controls the third transistor M3 connected to the first clock control line CK1_1 to turn on to supply the data signal loaded on the first source input line S1_ i to the pixel electrode of the first row of red subpixels R in the first display region, so that the red subpixels R are charged with the voltage Vdata 2.

Similarly, the voltage Vdata1 is charged to the pixel electrode in the first row of green sub-pixels G in the second display region, and the voltage Vdata2 is charged to the pixel electrode in the first row of green sub-pixels G in the first display region. And charging voltage Vdata1 to the pixel electrode in the first row of blue subpixels B in the second display region, and charging voltage Vdata2 to the pixel electrode in the first row of blue subpixels B in the first display region.

Because the duration t1 of the effective level of the first clock control signal ck1_ n is shorter than the duration t2 of the effective level of the second clock control signal ck2_ n, Vdata2< Vdata1 can be provided, so that the brightness of the first display area can be reduced by adjusting the size of t1, the brightness of the first display area is approximately the same as that of the second display area, and the display uniformity is improved.

In other possible embodiments, in practical implementation, in the embodiment of the present invention, as shown in fig. 8, the duration t1 of the active level of the first clock control signal ck1_ n may be made smaller than the duration t2 of the active level of the second clock control signal ck2_ n, and the voltage value VGH4 of the active level of the first sub-control signal v1_ n may also be made smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n, so that the voltage value VGH1 of the active level of the first clock control signal ck1_ n is also made smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n. Therefore, the opening time of the third transistor is smaller than that of the fourth transistor, the opening degree of the third transistor is smaller than that of the fourth transistor, and the display uniformity is further improved. At this time, the first sub-control signal terminal V1_ n is not electrically connected to the second clock control line CK2_ n.

The following description will take an example in which one frame scan time includes at least two data input stages. Typically a data input phase may comprise one or two lines or three or four lines of scan time. In practical applications, the number of the scanning time of one line included in the data input stage may be determined according to practical application environments, and is not limited herein. The following description will be made by taking an example in which one data input stage includes one line scanning time.

In some possible embodiments, when the one-frame scanning time includes a plurality of consecutive data input phases, the voltage value of the active level of the first control signal may be different in different data input phases. For example, in two consecutive data input stages, the voltage value of the active level of the same first clock control signal may be increased or decreased in the next data input stage compared to the previous data input stage to improve the luminance uniformity of the first display region.

In the following description, the voltage value of the active level of each first clock control signal in the next data input stage is increased from the voltage value in the previous data input stage in the successive data input stages.

Specifically, as shown in fig. 9, the voltage value VGH11 of the active level of the first clock control signal ck1_ n in the first one-row scanning time T _1, the voltage value VGH12 of the active level of the first clock control signal ck1_ n in the second one-row scanning time T _2, and the voltage value VGH13 of the active level of the first clock control signal ck1_ n in the third one-row scanning time T _3 sequentially increase. When the brightness of the first display area in the direction from the hollow part to the first multi-path gate is detected to be reduced in sequence, the voltage of the data signal on the first data line is increased in the next data input stage compared with the voltage of the data signal in the previous data input stage, so that the pixel voltage of the sub-pixel in the first display area in the direction from the hollow part to the first multi-path gate is increased in sequence, the brightness of the first display area can be compensated, and the display uniformity of the first display area is improved.

In a specific implementation, as shown in fig. 3 and 4, the second control signal terminal V2 may include: and a second sub control signal terminal V2_ n in one-to-one correspondence with each switching element 230_ n. The switching unit 230_ n may include: a first transistor M1; the detailed connection method is not described herein.

In the driving method provided in the embodiment of the present invention, loading the second control signal to the second control signal terminal may specifically include: loading a second sub control signal having the same signal timing as the second clock control signal to each second sub control signal terminal V2_ n; wherein a second sub-control signal corresponds to a signal timing of a second clock control signal.

Specifically, as shown in fig. 9, the second sub-control signal V2_ n loaded by the second sub-control signal terminal V2_ n corresponds to the signal timing of the second clock control signal ck2_ n. That is, the second sub-control signal v2_1 corresponds to the signal timing of the second clock control signal ck2_1, the second sub-control signal v2_2 corresponds to the signal timing of the second clock control signal ck2_2, and the second sub-control signal v2_3 corresponds to the signal timing of the second clock control signal ck2_ 3.

Further, in practical implementation, as shown in fig. 9, when a frame scanning time includes a plurality of consecutive data input phases, in each data input phase, the duration of the active level of the first control signal v1 is the same and is not less than a row scanning time T _ k; in the successive data input stages, the voltage value of the active level of the first control signal v1 increases in the next data input stage compared with the previous data input stage, and the voltage value of the active level of each first clock control signal ck1 — n increases. That is, the voltage value VGH11 of the active level of the first control signal v1 in the first one-line scan time T _1, the voltage value VGH12 of the active level of the first control signal v1 in the second one-line scan time T _2, and the voltage value VGH13 of the active level of the first control signal v1 in the third one-line scan time T _3 sequentially increase.

Further, in order to make the brightness in the first display region uniformly changeable, in the embodiment of the present invention, in the continuous data input stage, the voltage value of the active level of the first control signal, and the like, may be increased. This makes it possible to uniformly change the luminance in the first display region, further improving the display uniformity.

Next, referring to fig. 4 and 9, a driving method provided by an embodiment of the invention will be described by taking an example of applying the gate-on signals G _1 to G _3 to the gate lines G _1 to G _ 3.

In the first row scanning time T _1, a gate-on signal G _1 is applied to the gate line G _1, so that the thin film transistors in the sub-pixels in the first row are all turned on. When the gate line G _1 is applied with the gate-on signal G _1, the first and second source input lines S1_ i and S2_ j are applied with the voltage Vdata1, respectively, the first control signal terminal V1 is applied with the first control signal V1, and the second clock control signal CK2_ n is applied with the second clock control signal CK2_ n only when the second clock control signal CK2_1 is at a high level. The first transistor M1 and the fourth transistor M4, which control the connection of the second clock control line CK2_1, are turned on, and the turned-on fourth transistor M4 supplies the data signal loaded on the second source input line S2_ j to the pixel electrode in the first row of red subpixels R in the second display region, so that the red subpixels R are charged with the voltage Vdata 1. The turned-on first transistor M1 supplies the first control signal v1 to the first clock control line CK1_1, causing the first clock control line CK1_1 to load the first clock control signal CK1_ 1. The first clock control signal CK1_1 controls the third transistor M3 connected to the first clock control line CK1_1 to turn on to supply the data signal loaded on the first source input line S1_ i to the pixel electrode of the first row of red subpixels R in the first display region, so that the red subpixels R are charged with the voltage Vdata 2.

Similarly, only when the second clock control signal CK2_2 is at a high level, the first transistor M1 and the fourth transistor M4 connected to the second clock control line CK2_2 are controlled to be turned on, so that the voltage Vdata1 can be charged to the pixel electrode in the first row of green sub-pixels G in the second display region, and the voltage Vdata2 can be charged to the pixel electrode in the first row of green sub-pixels G in the first display region.

And, only when the second clock control signal CK2_3 is at a high level, the first transistor M1 and the fourth transistor M4 controlling the connection of the second clock control line CK2_3 are turned on, so that the voltage Vdata1 may be charged to the pixel electrode in the first row of blue subpixels B in the second display region, and the voltage Vdata2 may be charged to the pixel electrode in the first row of blue subpixels B in the first display region. Since the voltage value VGH11 of the active level of the first clock control signal ck1_ n is smaller than the voltage value VGH2 of the active level of the second clock control signal ck2_ n, there may be Vdata2< Vdata 1.

Similarly, in the second row scanning time T _2, the gate line G _2 is loaded with the gate turn-on signal G _2, so that the thin film transistors in the sub-pixels in the second row are turned on, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the first display region are respectively charged with Vdata3, and the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the second display region are respectively charged with Vdata 1. Since the voltage value VGH12 of the active level of the first clock control signal ck1_ n is greater than the voltage value VGH11 thereof in the first row scan time T _1, there may be Vdata3> Vdata 2. And in the third row scanning time T _3, loading a gate turn-on signal G _3 to the gate line G _3 to turn on the thin film transistors in the sub-pixels in the third row, so that the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the first display region are respectively charged with Vdata4, and the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the second display region are respectively charged with Vdata 1. Since the voltage value VGH13 of the active level of the first clock control signal ck1_ n is greater than the voltage value VGH12 thereof in the second one-line scan time T _2, there may be Vdata4> Vdata 3.

Since the voltage value of the effective level of the first clock control signal ck1_ n is not greater than the voltage value VGH2 of the effective level of the second clock control signal ck2_ n, Vdata4< Vdata1 is available, so that the uniformity of the brightness of the first display area can be improved by adjusting the voltage value of the effective level of the first clock control signal ck1_ n, the brightness of the first display area is approximately the same as that of the second display area, and the display uniformity is improved.

In other possible embodiments, when the one-frame scanning time includes a plurality of consecutive data input phases, the active level of the second control signal is maintained for different durations in different data input phases. For example, the next data input stage may be increased or decreased in comparison with the previous data input stage in two consecutive data input stages, so as to increase the brightness uniformity of the first display region.

In the following description, the following description will be given taking as an example that the sustain period of the active level of each first clock control signal is increased in the next data input stage compared with the previous data input stage in the successive data input stages.

Specifically, as shown in fig. 10, the sustain period T11 of the active level of the first clock control signal ck1_ n in the first one-line scanning time T _1, the sustain period T12 of the active level of the first clock control signal ck1_ n in the second one-line scanning time T _2, and the sustain period T13 of the active level of the first clock control signal ck1_ n in the third one-line scanning time T _3 increase in order. When the brightness of the first display area in the direction from the hollow part to the first multi-path gate is detected to be reduced in sequence, the voltage of the data signals on the first data line is increased in sequence compared with the voltage of the data signals in the previous data input stage in the next data input stage, so that the pixel voltage of the sub-pixels in the first display area in the direction from the hollow part to the first multi-path gate is increased in sequence, the brightness of the first display area can be compensated, and the display uniformity of the first display area is improved.

loading a first sub-control signal V1_ n having the same signal timing as that of each second clock control signal to each first sub-control signal terminal V1_ n; wherein, a first sub-control signal v1_ n corresponds to the signal timing of a second clock control signal ck2_ n. Specifically, as shown in fig. 10, the first sub-control signal v1_1 corresponds to the signal timing of the second clock control signal ck2_1, the first sub-control signal v2_2 corresponds to the signal timing of the second clock control signal ck2_2, and the first sub-control signal v2_3 corresponds to the signal timing of the second clock control signal ck2_ 3.

In practical implementation, when one frame scan time includes a plurality of consecutive data input phases, as shown in fig. 10, in each data input phase, the occurrence order of the active levels of the second control signal v2 corresponds to the occurrence order of the active levels of all the second clock control signals one-to-one; also, in the successive data input stages, the sustain period of the active level of the second control signal v2 is increased in the next data input stage compared to the previous data input stage, so that the sustain period of the active level of each first clock control signal can be increased.

Further, in the successive data input stages, the value of the sustain period or the like of the active level of the second control signal may be increased. This makes it possible to uniformly change the luminance in the first display region, further improving the display uniformity.

Next, referring to fig. 5 and fig. 10, a driving method provided by an embodiment of the present invention will be described by taking an example of applying gate-on signals G _1 to G _3 to gate lines G _1 to G _ 3.

In the first row scanning time T _1, a gate-on signal G _1 is applied to the gate line G _1, so that the thin film transistors in the sub-pixels in the first row are all turned on. When the gate line G _1 is applied with the gate-on signal G _1, the first source input line S1_ i and the second source input line S2_ j are applied with a voltage Vdata1, respectively, and the first sub-control signal terminal V1_ n is applied with a first control signal V1_ n, respectively, the second control signal terminal V2 is applied with a second control signal V2, and the second clock control signal CK2_ n is applied with a second clock control signal CK2_ n, only when the second clock control signal CK2_1 is at a high level, the fourth transistor M4 connected to the second clock control line CK2_1 is controlled to be turned on, and the turned-on fourth transistor M4 supplies the data signal applied to the second input line source S2_ j to the pixel electrode in the first row of red subpixels R in the second display region, so that the red subpixels R are charged with the voltage Vdata 1. When the second control signal v is at a high level, the second transistor M2 is controlled to be turned on to provide the first sub-control signal v1_ n to the first clock control line CK1_ n, so that the first clock control line CK1_ n is loaded with the first clock control signal CK1_ n. The first clock control signal CK1_1 controls the third transistor M3 connected to the first clock control line CK1_1 to turn on to supply the data signal loaded on the first source input line S1_ i to the pixel electrode of the first row of red subpixels R in the first display region, so that the red subpixels R are charged with the voltage Vdata 2.

Similarly, the voltage Vdata1 is charged to the pixel electrode in the first row of green sub-pixels G in the second display region, and the voltage Vdata2 is charged to the pixel electrode in the first row of green sub-pixels G in the first display region. And charging voltage Vdata1 to the pixel electrode in the first row of blue subpixels B in the second display region, and charging voltage Vdata2 to the pixel electrode in the first row of blue subpixels B in the first display region. Since the sustain duration t11 of the active level of the first clock control signal ck1_ n is less than the sustain duration t12 of the active level of the second clock control signal ck2_ n, there may be Vdata2< Vdata 1.

Similarly, in the second row scanning time T _2, the gate line G _2 is loaded with the gate turn-on signal G _2, so that the thin film transistors in the sub-pixels in the second row are turned on, the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the first display region are respectively charged with Vdata2, and the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second row in the second display region are respectively charged with Vdata 3. Since the sustain duration T12 of the active level of the first clock control signal ck1_ n is longer than the sustain duration T11 thereof in the first row scan time T _1, there may be Vdata3> Vdata 2. And in the third row scanning time T _3, loading a gate turn-on signal G _3 to the gate line G _3 to turn on the thin film transistors in the sub-pixels in the third row, so that the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the first display region are respectively charged with Vdata2, and the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B in the third row in the second display region are respectively charged with Vdata 4. Since the sustain duration T13 of the active level of the first clock control signal ck1_ n is longer than the sustain duration T12 in the second one-line scan time T _2, there may be Vdata4> Vdata 3.

Because the duration of the effective level of the first clock control signal ck1_ n is not longer than the duration of the effective level of the second clock control signal ck2_ n, Vdata4< Vdata1 can be provided, so that the uniformity of the brightness of the first display area can be improved by adjusting the duration of the effective level of the first clock control signal ck1_ n, the brightness of the first display area is approximately the same as that of the second display area, and the display uniformity is improved.

Further, in the embodiment of the present invention, as shown in fig. 10 and fig. 11, in the consecutive data input phases, the duration of the active level of the second control signal v2 is increased compared with the duration of the active level of the previous data input phase in the next data input phase, and the duration of the active level of each first clock control signal ck1_ n is increased. And the voltage value of the active level of each first sub-control signal v1_ n may be increased in the next data input stage compared to the previous data input stage in the successive data input stages. In this way, in the next data input stage, compared with the previous data input stage, the turn-on time of the third transistor can be sequentially increased, and the turn-on degree of the third transistor can be sequentially increased, so that the display uniformity is further improved. At this time, the first sub-control signal terminal V1_ n is not electrically connected to the second clock control line CK2_ n.

Further, the voltage value of the active level of the first clock control signal may be made not greater than the voltage value of the active level of the second clock control signal. This can reduce the luminance of the first display region as a whole, and can make the luminance of the first display region and the second display region tend to be uniform.

Based on the same inventive concept, embodiments of the present invention provide a display panel, which is driven by the driving method of the display panel provided by the embodiments of the present invention.

In specific implementation, in the embodiment of the present invention, since the principle of solving the problem of the display panel is similar to the driving method of the display panel, the implementation of the display panel may refer to the implementation of the driving method, and repeated details are not repeated.

Based on the same inventive concept, an embodiment of the present invention provides a display device, as shown in fig. 12, including the display panel provided by the embodiment of the present invention. In specific implementation, the principle of the display device to solve the problem is similar to that of the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In practical implementation, in an embodiment of the present invention, the display device provided in the embodiment of the present invention may further include a driver IC, where the driver IC is configured to implement any of the steps of the method for driving the display panel provided in the embodiment of the present invention.

In specific implementation, in the embodiment of the present invention, the driver IC provided in the embodiment of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects, which is not limited herein.

In general, when a driver IC is designed, its output terminal is designed according to a function to be realized. However, in practical applications, the functions that the driver IC needs to implement are different for different application environments, and therefore, in order to meet the requirements of most application environments, a plurality of vacant output terminals may be preset to increase the functions of the driver IC. In practical implementation, in the embodiment of the present invention, the driving IC may include a plurality of idle output terminals, and the first control signal terminal and the second control signal terminal are electrically connected to one of the idle output terminals in a one-to-one correspondence manner. Therefore, the first control signal and the second control signal can be provided by the vacant output end in the driving chip, so that the vacant output end reserved in the driving IC can be adopted to output signals, and the process preparation difficulty is reduced. Thus, when one frame scanning time includes a plurality of data input stages, the setting can be made according to the number of the vacant output terminals of the driving IC. For example, when the number of idle outputs is 24, one frame scan time may include 24 data input stages. Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided by the embodiment of the present invention and the driving device provided by the embodiment of the present invention.

In specific implementation, the display device provided in the embodiment of the present invention may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. The driving method of a display panel, wherein the display panel includes the array base plate with at least one hollow-out part; the array substrate includes: a display area and a non-display area; the display area comprises a first display area and a second display area, the hollow part is located in the first display area, and the first display area comprises a plurality of first data lines; the second display area comprises a plurality of second data lines; the non-display area includes: the multi-channel clock comprises a plurality of first multi-channel gates, a plurality of second multi-channel gates, N first clock control lines, N second clock control lines and switch units which are in one-to-one correspondence with the first clock control lines; one first multiplexer is connected with M first data lines, and one second multiplexer is connected with M second data lines; all the first multi-way gates are electrically connected with the N first clock control lines; all the second multi-way gates are electrically connected with the N second clock control lines; each first clock control line is connected with a first control signal end through a corresponding switch unit, and the control end of each switch unit is connected with a second control signal end; n is more than or equal to M and more than or equal to 3 and is an integer;

the driving method includes:

2. The driving method of claim 1, wherein a voltage value of an active level of the first clock control signal is smaller than a voltage value of an active level of the second clock control signal.

3. The driving method according to claim 1, wherein a sustain period of an active level of the first clock control signal is shorter than a sustain period of an active level of the second clock control signal.

4. The driving method according to claim 2 or 3, wherein the one-frame scanning time includes at least one data input phase; in the same data input stage, the voltage values of the effective levels of the first clock control signals are the same, and the maintaining time lengths are the same;

in different data input stages, at least one of a voltage value and a duration of an active level of the same first clock control signal is different.

5. The driving method of claim 4, wherein when the voltage value of the active level of the first clock control signal is less than the voltage value of the active level of the second clock control signal, the second control signal terminal includes: the second sub control signal ends correspond to the switch units one by one; the loading of the second control signal to the second control signal terminal specifically includes:

loading a second sub-control signal with the same signal timing as the second clock control signal to each second sub-control signal terminal; wherein a signal timing of one of the second sub control signals corresponds to a signal timing of one of the second clock control signals.

6. The driving method according to claim 5, wherein the active levels of the first control signals are maintained for the same duration not less than a line scanning time; and a voltage value of an active level of the first control signal is smaller than a voltage value of an active level of the second clock control signal.

7. The driving method as claimed in claim 6, wherein when the one-frame scanning time includes a plurality of data input phases in succession, a voltage value of the active level of the first control signal is different in different ones of the data input phases.

8. The driving method according to claim 5, wherein each of the second sub control signals is respectively identical to the corresponding second clock control signal.

9. The driving method of claim 8, wherein the second sub control signal terminal is electrically connected to the second clock control line.

10. The driving method according to claim 5, wherein the switching unit includes: a first transistor;

the grid electrode of the first transistor is connected with the corresponding second sub-control signal end, the first pole of the first transistor is connected with the first control signal end, and the second pole of the first transistor is connected with the corresponding first clock control line.

11. The driving method according to claim 4, wherein when a sustain duration of an active level of the first clock control signal is shorter than a sustain duration of an active level of the second clock control signal, the first control signal terminal includes: the first sub control signal ends correspond to the switch units one by one; the loading of the first control signal to the first control signal terminal specifically includes:

loading first sub-control signals with the same signal time sequence as the second clock control signals to the first sub-control signal ends; wherein a signal timing of one of the first sub-control signals corresponds to a signal timing of one of the second clock control signals.

12. The driving method according to claim 11, wherein an appearance order of the active levels of the second control signals corresponds one-to-one to an appearance order of the active levels of all the second clock control signals; and a sustain duration of the active level of the second control signal is less than a sustain duration of the active level of the second clock control signal.

13. The driving method as claimed in claim 12, wherein when the one-frame scanning time includes a plurality of data input phases in succession, the on-duration of the active level of the second control signal is different in different ones of the data input phases.

14. The driving method according to claim 11, wherein when a sustain period of an active level of the first clock control signal is shorter than a sustain period of an active level of the second clock control signal, each of the first sub control signals is respectively identical to the corresponding second clock control signal.

15. The driving method of claim 14, wherein the first sub control signal terminal is electrically connected to the second clock control line.

16. The driving method according to claim 11, wherein the switching unit includes: a second transistor;

the grid electrode of the second transistor is connected with the second control signal end, the first pole of the second transistor is connected with the corresponding first sub-control signal end, and the second pole of the second transistor is connected with the corresponding first clock control line.

17. A display panel driven by the driving method according to any one of claims 1 to 16.

18. A display device comprising the display panel according to claim 17.