CN105679272A - Display device and driving circuit thereof - Google Patents
Display device and driving circuit thereof Download PDFInfo
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- CN105679272A CN105679272A CN201610227162.8A CN201610227162A CN105679272A CN 105679272 A CN105679272 A CN 105679272A CN 201610227162 A CN201610227162 A CN 201610227162A CN 105679272 A CN105679272 A CN 105679272A
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- 230000004913 activation Effects 0.000 claims description 50
- 238000006243 chemical reaction Methods 0.000 claims description 23
- 238000010586 diagram Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 6
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 description 4
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 4
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 description 4
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 210000001367 artery Anatomy 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
The invention discloses a display device and a driving circuit thereof. The driving circuit comprises a plurality of first control lines, a plurality of second control lines, a plurality of first switches and a plurality of second switches. The first control line is used for transmitting a plurality of first control signals. The second control line is used for transmitting a plurality of second control signals. A control terminal of the first switch is used for receiving a corresponding one of the first control signals. A control terminal of the second switch is used for receiving a corresponding one of the second control signals. The first control signal is switched between a first enable voltage and a first disable voltage to turn on the first switch. The second control signal is switched between a second enabling voltage and a second disabling voltage to conduct the second switch. The second enabling voltage is different from the first enabling voltage, and the second forbidden voltage is different from the first forbidden voltage.
Description
Technical field
Content of the present invention is about a kind of display unit. Specifically, content of the present invention is about a kind of active matrix display device.
Background technology
In recent years, along with the fast development of large scale liquid crystal display panel, multiplexer is used in the middle of driving circuit, to reduce source drive element number required in large scale liquid crystal display panel.
But, the element characteristic being limited in multiplexer, can reduce along with process of charging gradually to the charging current of data line so that display panel undercharge or need the long period just can complete charging, and then affect panel entirety homogeneity. Therefore, how to improve the driving circuit in display panel, to improve multiplexer to the charging quality of data line, it is research theme important in this area in fact.
Summary of the invention
For solving the problem, an aspect of content of the present invention is a kind of driving circuit. Driving circuit comprises many articles of the first control lines, many articles of the 2nd control lines, multiple first switch and multiple 2nd switch. First control line is in order to transmit multiple first control signal. 2nd control line is in order to transmit multiple 2nd control signal. One control end of the first switch is in order to receive one corresponding in the first control signal. One control end of the 2nd switch is in order to receive one corresponding in the 2nd control signal. First control signal switches between the first activation voltage and the first forbidden energy voltage, with conducting first switch. 2nd control signal switches between the 2nd activation voltage and the 2nd forbidden energy voltage, with conducting the 2nd switch. 2nd activation voltage is different from the first activation voltage, and the 2nd forbidden energy voltage is different from the first forbidden energy voltage.
Another aspect of content of the present invention is a kind of display unit. Display unit comprises multi-strip scanning line, a plurality of data lines, pel array and switch circuit. Data line comprises many articles of the first data lines being spaced arrangement and many articles of the 2nd data lines. Pel array comprises multiple pixel. Pixel is electrically connected at the corresponding one of sweep trace and the corresponding one of data line. Switch circuit is electrically connected at data line, in order to receive the first data voltage and the 2nd data voltage, and the voltage quasi position according to multiple first control signal and multiple 2nd control signal in the respective polarity switching switch circuit of the first data voltage and the 2nd data voltage.
In sum, the voltage quasi position of the control signal that content of the present invention receives through corresponding switching multiplexer in different picture frame, the power needed for driving circuit can be saved, and in maintenance, to using when pixel charging efficiency, one-transistor makes multiplexer, reduces the holistic cost of driving circuit.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the display unit illustrated according to content part embodiment of the present invention.
Fig. 2 is the schematic diagram of the multiplexer module in the Fig. 1 illustrated according to content part embodiment of the present invention.
Fig. 3 is the signal waveform graph of a relation of the sweep voltage signal, the first control signal and the 2nd control signal that illustrate according to content part embodiment of the present invention.
Fig. 4 is the schematic diagram of the control module in the Fig. 1 illustrated according to content part embodiment of the present invention.
Fig. 5 is the schematic diagram of the multiplexer module in the Fig. 1 illustrated according to other part embodiments of content of the present invention.
Fig. 6 is the schematic diagram of the multiplexer module in the Fig. 1 illustrated according to other part embodiments of content of the present invention.
Wherein, Reference numeral:
100 display unit
120 pel arrays
130 source electrode drivers
140 switch circuits
142 multiplexer modules
144 control modules
150 gate drivers
160 sequential control devices
R1, G1, B1, R2, G2, B2 pixel
DL1～DLm data line
SL1～SLn sweep trace
Vdata1～Vdatam data voltage signal
VSL1～VSLn sweep voltage signal
CS switch controlling signal
CTR scan control signal
CS1_R, CS1_G, CS1_B first control signal
CS2_R, CS2_G, CS2_B the 2nd control signal
Clk1～Clkn exports clock signal
Data data signal
S1～S6 data voltage
SW1_R, SW1_G, SW1_B first switch
SW2_R, SW2_G, SW2_B the 2nd switch
F1, F2 picture frame
During D1～Dn
P1, P2, P3 period
LS11, LS12, LS21, LS22 current potential conversion unit
SW11, SW12, SW21, SW22 control switch unit
DS1～DS4 signal
POL polarity inversion signal
VGH1, VGH2, VGL1, VGL2 reference voltage
CS_11, CS_12, CS_21, CS_22 control signal
SW_R11, SW_G11, SW_B11, SW_R12, SW_G12, SW_B12, SW_R21, SW_G21, SW_B21, SW_R22, SW_G22, SW_B22 switch
Embodiment
Hereafter accompanying drawing is coordinated to do explanation in detail for embodiment, to understand the aspect of content of the present invention better, but the embodiment provided also is not used to the scope that restriction the present invention is contained, and the description of structure operation is not used to limit its order performed, any structure again combined by element, produced the device with impartial effect, it is all the scope that the present invention is contained. In addition, according to the standard of industry and usual way, graphic only for the purpose of aid illustration, not according to life size mapping, the size of in fact various feature can increase arbitrarily or reduce so that explanation. In following explanation, similar elements is described with identical symbology so that understanding.
In the word (terms) that full section specification sheets and claim book protection domain use, outside indicating especially, usually have each word use in this area, in content disclosed herein with the usual meaning in special content. Some in order to the word that describes the present invention by lower or discuss in the other places of this specification sheets, with the guiding providing those skilled in the art extra in description for the present invention.
In addition, in word used herein " comprising ", " comprising ", " having ", " containing " etc., it is open term, namely mean " including but not limited to ". In addition, used herein " and/or ", comprise any one and its all combination of one or more project in associated listed items.
In herein, when element is called as " connection " or " coupling ", can refer to " electric connection " or " electric property coupling ". " connection " or " coupling " also can in order to represent mutual collocation operation or interactive between two or multiple element. In addition, although using the term such as " first ", " the 2nd " to describe different elements herein, this term is only the element or operation that describe with constructed term in order to difference. Indicate unless context is clear, otherwise this term is not censured especially or implied order or cis-position, is also not used to limit the present invention.
Please refer to Fig. 1. Fig. 1 is the schematic diagram of the display unit 100 illustrated according to content part embodiment of the present invention. As shown in Figure 1, display unit 100 comprises sweep trace SL1～SLn, data line DL1～DLm, pel array 120, switch circuit 140, source electrode driver 130, gate drivers 150 and sequential control device 160.
In some embodiments, pel array 120 is included between data line DL1～DLm and sweep trace SL1～SLn to be arranged as multiple pixel R1, G1, B1, R2, G2, B2 of array. Each pixel is electrically connected at one corresponding in one corresponding in sweep trace SL1～SLn and data line DL1～DLm respectively. It is noted that the distributing style of pixel R1～B2 is only the use of illustration in Fig. 1, it does not mean to limit content of the present invention. Various different pixels distributing style is also within the limit of consideration of content of the present invention.
In some embodiments, pixel R1, G1, B1 and pixel R2, each self-contained switch of G2, B2 and storage capacitors. The first end of switch is electrically connected at corresponding data line DL1～DLm, in order to receive data voltage signal Vdata1～Vdatam, 2nd end of switch is electrically connected at the first end of storage capacitors, the control end of switch is electrically connected at corresponding sweep trace SL1～SLn, in order to receive sweep voltage signal VSL1～VSLn so that switch is according to sweep voltage signal VSL1～VSLn optionally conducting. 2nd end of storage capacitors is electrically connected to a reference voltage. Thus, when the switch that sweep voltage signal VSL1 conducting is electrically connected in the pixel R1～B2 of sweep trace SL1, storage capacitors in pixel R1 just can be charged by the data voltage signal Vdata1 on data line DL1, storage capacitors in pixel G1 just can be charged by the data voltage signal Vdata2 on data line DL2, storage capacitors in pixel B 1 just can be charged by the data voltage signal Vdata3 on data line DL3, analogizes with this.
As Fig. 1 illustrate, pixel R1 is electrically connected at data line DL1, pixel G1 is electrically connected at data line DL2, pixel B 1 is electrically connected at data line DL3, pixel R2 is electrically connected at data line DL5, pixel G2 is electrically connected at data line DL5, pixel B 2 is electrically connected at data line DL6. In some embodiments, pixel R1, R2 can be red pixel, and pixel G1, G2 can be green pixel, and pixel B 1, B2 can be blue pixel. Adjacent red pixel, green pixel and blue pixel form a display unit.
In some embodiments, pel array 120 adopts row conversion (Columninversion).Data voltage signal Vdata1～Vdatam the opposite polarity of both transmission adjacent in data line DL1～DLm. In other words, when data line DL1, DL3, DL5 transmit straight polarity data voltage respectively to corresponding pixel R1, G2, B1, data line DL2, DL4, DL6 transmit negative polarity data voltage respectively to corresponding pixel R2, G1, B2. On the other hand, when data line DL1, DL3, DL5 transmit negative polarity data voltage respectively to corresponding pixel R1, G2, B1, data line DL2, DL4, DL6 transmit straight polarity data voltage respectively to corresponding pixel R2, G1, B2. That is, in each picture frame (frame), pixel R1, G2, B1 and pixel R2, G1, B2 are in dissimilar polarity respectively.
In some embodiments, source electrode driver 130 exports multiple data voltage S1, S2 to switch circuit 140. It is noted that for ease of illustrating, Fig. 1 only shows two data voltages, but content of the present invention is not limited with these quantity.
In some embodiments, gate drivers 150 exports sweep voltage signal VSL1～VSLn and exports corresponding sweep trace SL1～SLn to, and then the switch in conducting respective pixel R1～B2. Citing, during the activation of sweep voltage signal VSL1, the switch being electrically connected in the pixel R1～B2 of sweep trace SL1 by conducting, and during the activation of sweep voltage signal VSL2, the switch being electrically connected in the pixel R1～B2 of sweep trace SL2, by conducting, is analogized with this.
In some embodiments, sequential control device 160 electric property coupling source electrode driver 130, switch circuit 140 and gate drivers 150, to control the running of source electrode driver 130, switch circuit 140 and gate drivers 150.
Specifically, in some embodiments, sequential control device 160 export at least for the moment arteries and veins signal Clk1～Clkn and data signal Data to source electrode driver 130 so that source electrode driver 130 according to clock signal Clk1～Clkn and data signal Data output data voltage S1, S2 to switch circuit 140.
In some embodiments, switch circuit 140 comprises multiplexer module 142 and control module 144. Multiplexer module 142 is electrically connected at source electrode driver 130 and data line DL1～DLm, in order to provide data voltage signal Vdata1～Vdatam to drive the pixel R1 in pel array 120～B2. Specifically, multiplexer module 142 receives data voltage S1, S2 from source electrode driver 130, and according to multiple control signal CS1_R～CS2_B, data voltage S1, S2 optionally transfers to corresponding data line DL1～DLm.
Control module 144 is electrically connected at sequential control device 160, in order to receive switch controlling signal CS from sequential control device 160, and export multiple first control signal CS1_R, CS1_G, CS1_B and multiple 2nd control signal CS2_R, CS2_G, CS2_B to multiplexer module 142 according to switch controlling signal CS, to control the operation of multiplexer module 142. , in some embodiments, in addition control module 144 more in order to export scan control signal CTR to gate drivers 150, exports sweep voltage signal VSL1～VSLn with control gate driving mechanism 150.
In content part embodiment of the present invention, the voltage quasi position of the first control signal CS1_R that switch circuit 140 exports according to control module 144 in the respective polarity switching switch circuit 140 of data voltage S1 and data voltage S2, the voltage quasi position of CS1_G, CS1_B and the 2nd control signal CS2_R, CS2_G, CS2_B.For the purpose of illustrating, collocation Fig. 2 and Fig. 3 is described by the operating method that the concrete structure of multiplexer module 142 and the first control signal CS1_R, CS1_G, CS1_B and the 2nd control signal CS2_R, CS2_G, CS2_B control multiplexer module 142. Please refer to Fig. 2. Fig. 2 is the schematic diagram of the multiplexer module 142 in the Fig. 1 illustrated according to content part embodiment of the present invention. As shown in Figure 2, in some embodiments, multiplexer module 142 comprises many first control lines CL1_R, CL1_G, CL1_B, many articles the 2nd control lines CL2_R, CL2_G, CL2_B, multiple first switch S W1_R, SW1_G, SW1_B, multiple 2nd switch S W2_R, SW2_G, SW2_B.
As in Fig. 2 illustrate, first control line CL1_R, CL1_G, CL1_B is respectively in order to transmit the first control signal CS1_R, CS1_G, CS1_B. 2nd control line CL2_R, CL2_G, CL2_B is respectively in order to transmit the 2nd control signal CS2_R, CS2_G, CS2_B.
The control end of the first switch S W1_R, SW1_G, SW1_B is electrically connected at first control line CL1_R, CL1_G, CL1_B respectively, to receive the first control signal CS1_R, CS1_G, CS1_B. Similarly, the control end of the 2nd switch S W2_R, SW2_G, SW2_B is electrically connected at the 2nd control line CL2_R, CL2_G, CL2_B respectively, to receive the 2nd control signal CS2_R, CS2_G, CS2_B.
Thus, the first switch S W1_R, SW1_G, SW1_B just according to the first control signal CS1_R, CS1_G, CS1_B optionally conducting, can drive one corresponding in electric current to data line DL1, DL3, DL5 to provide. Similarly, the 2nd switch S W2_R, SW2_G, SW2_B just according to the 2nd control signal CS2_R, CS2_G, CS2_B optionally conducting, can drive one corresponding in electric current to data line DL2, DL4, DL6 to provide. In some embodiments, data voltage S1, S2 is the data voltage of dissimilar polarities in same picture frame (frame). In other words, when data voltage S1 is straight polarity, data voltage S2 is negative polarity, and when data voltage S1 is negative polarity, data voltage S2 is straight polarity. Thus, pel array 120 just can realize row conversion so that the pixel on adjacent two data lines is in dissimilar polarity respectively.
Please refer to Fig. 3. Fig. 3 is the signal waveform graph of a relation of sweep voltage signal VSL1～VSLn, the first control signal CS1_R～CS1_B and the 2nd control signal CS2_R～CS2_B illustrated according to content part embodiment of the present invention.
As shown in Figure 3. First control signal CS1_R, CS1_G, CS1_B switch between the first activation voltage and the first forbidden energy voltage, with conducting first switch S W1_R, SW1_G, SW1_B. Similarly, 2nd control signal CS2_R, CS2_G, CS2_B switch between the 2nd activation voltage and the 2nd forbidden energy voltage, with conducting the 2nd switch S W2_R, SW2_G, SW2_B, wherein the 2nd activation voltage is different from the first activation voltage, and the 2nd forbidden energy voltage is different from the first forbidden energy voltage.
Specifically, in the embodiment that Fig. 3 illustrates, in picture frame F1, the sweep voltage signal VSL1～VSLn on sweep trace SL1～SLn is during period, D1～Dn was in activation, and then makes the switch conducting in the pixel of respective column. For example, within period D1, corresponding pixel R1, G1, B1, R2, G2, B2 on sweep voltage signal VSL1 conducting sweep trace SL1.
As shown in Figure 3, in period D1, the first control signal CS1_R, CS1_G, CS1_B are respectively at secondary period P1, P2, P3 conducting. Similarly, the 2nd control signal CS2_R, CS2_G, CS2_B be also respectively at secondary period P1, P2, P3 conducting. In other words, the phase place of the first control signal CS1_R, CS1_G, CS1_B is different, and the phase place of the 2nd control signal CS2_R, CS2_G, CS2_B is different.
Specifically, when time period P1 of period D1, the switch S W1_R in multiplexer module 142, SW2_R conducting so that multiplexer module 142 respectively according to data voltage S1, S2 output driving current to the pixel R1 on data line DL1, DL4, R2. Then, when time period P2 of period D1, the switch S W1_G in multiplexer module 142, SW2_G conducting so that multiplexer module 142 respectively according to data voltage S1, S2 output driving current to the pixel G2 on data line DL5, DL2, G1. Then, when time period P3 of period D1, the switch S W1_B in multiplexer module 142, SW2_B conducting so that multiplexer module 142 respectively according to data voltage S1, S2 output driving current to the pixel B 1 on data line DL3, DL6, B2.
Similarly, during sweep trace SL2～SLn conducting in D2～Dn, the first control signal CS1_R, CS1_G, CS1_B and the 2nd control signal CS2_R, CS2_G, CS2_B also respectively at different time period P1, P2, P3 conductings.
It is noted that in picture frame F1, it is provided that the data voltage S1 to pixel R1, G2, B1 is negative polarity, be provided to pixel R2, the data voltage S2 of G1, B2 is straight polarity. Therefore, control module 144 can export respectively according to the difference of data voltage S1, S2 polarity of voltage there is different high levle the first activation voltage, the 2nd activation voltage, and the first forbidden energy voltage of different low level and the 2nd forbidden energy voltage. For example, in some embodiments, in picture frame F1, the upper corresponding pixel of data line DL2, DL4, DL6 is in straight polarity, and the 2nd activation voltage has the first level (as: 14.5V), and the 2nd forbidden energy voltage has the 2nd level (as:-1.5V).
In addition, in picture frame F1, the upper corresponding pixel of data line DL1, DL3, DL5 is in negative polarity, first activation voltage has the 3rd level (as: 8V) being different from the first level, and the first forbidden energy voltage has the 4th level (as:-8V) being different from the 2nd level.
Relatively, in next picture frame F2, due to row conversion, it is provided that the data voltage S1 to pixel R1, G2, B1 is converted to straight polarity from negative polarity, is provided to pixel R2, the data voltage S2 of G1, B2 is converted to negative polarity from straight polarity. Now, the upper corresponding pixel of data line DL1, DL3, DL5 is in straight polarity, and the first activation voltage has the first level (as: 14.5V), and the first forbidden energy voltage has the 2nd level (as:-1.5V).
In addition, in picture frame F2, the upper corresponding pixel of data line DL2, DL4, DL6 is in negative polarity, and the 2nd activation voltage has the 3rd level (as: 8V), and the 2nd forbidden energy voltage has the 4th level (as:-8V).
Along with the difference of data voltage polarity, flow through the first switch S W1_R in multiplexer module 142, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B operating voltage not identical. Therefore, it is provided that activation voltage to the first switch S W1_R of different voltage quasi position, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B, can balance multiplexer module 142 to the efficiency charged on difference data line DL1～DLm.
For example, in some embodiments, when voltage range exports data line DL1, DL3, DL5 in straight polarity data voltage between 0V of about 5V～about to via the first switch S W1_R, SW1_B, SW1_G, in during the activation of the first switch S W1_R, SW1_B, SW1_G conducting, grid voltage is about 14.5V. Therefore, gate-source voltage maximum value can be about 14.5V, and minimum is about 9.5V. Now, the negative polarity data voltage of voltage range between 0V～-5V exports data line DL2, DL4, DL6 to via the 2nd switch S W2_R, SW2_B, SW2_G, in during the activation of the 2nd switch S W2_R, SW2_B, SW2_G conducting, grid voltage is about 8V. Therefore, gate-source voltage maximum value can be about 13V, and minimum is about 8V. Thus, the driving electric current that multiplexer module 142 provides just can roughly maintain close level, and then data line DL1～DLm is charged by balance ground.
Specifically, in content part embodiment of the present invention, control module 144 arranges the first level higher than the 3rd level, and the 2nd level is higher than the 4th level. Thus, for the pixel of the data voltage providing high polarity, control module 144 can provide higher voltage quasi position. By this, within the shorter signal conduction time (that is: secondary period P1～P3), still can guarantee to be provided to the size of the driving electric current of data line DL1～DLm according to data voltage S1, S2, with shorten multiplexer module 142 provide data voltage signal Vdata1～Vdatam each pixel in pel array 120 charged needed for time, it is to increase the drive efficiency of display unit 100. Relatively, for the pixel of the data voltage providing negative polarity, control module 144 can provide the control signal of relatively low level, to reduce the watt consumption of switch circuit 140.
It is noted that the quantity of the first control signal illustrated in Fig. 3 and the 2nd control signal and phase place are only example. In different embodiments, control module 144 can coordinate the quantity arranging adjustment the first control signal and the 2nd control signal and the phase place of multiplexer module.
In addition, mentioned in previous embodiment voltage value is only example, it does not mean to limit content of the present invention. In different embodiments, the numerical values recited of the first level, the 2nd level, the 3rd level and the 4th level all can adjust according to actual demand. For example, in some embodiments, the first level can be about 8V, and the 2nd level can be about 1V, and the 3rd level can be 3V, and the 4th level can be about-6V. Thus, for the data voltage of about 5V～about-5V, no matter data line DL1～DLm is in straight polarity or negative polarity, grid voltage between source electrodes can maintain about more than 3V during activation, can maintain about-1V during forbidden energy, to maintain the normal running of switch.
Please refer to Fig. 4. Fig. 4 is the schematic diagram of the control module 144 in the Fig. 1 illustrated according to content part embodiment of the present invention. As shown in Figure 4, control module 144 is electrically connected at first control line CL1_R, CL1_G, CL1_B and the 2nd control line CL2_R, CL2_G, CL2_B, in order to export the first control signal CS1_R, CS1_G, CS1_B and the 2nd control signal CS2_R, CS2_G, CS2_B according to polarity inversion signal POL.
Specifically, in some embodiments, control module 144 comprises current potential conversion unit LS11, LS12, LS21, LS22 and control switch unit SW11, SW12, SW21, SW22.Specifically, current potential conversion unit LS11～LS22 can pass through various level shifter (level-shifter) and multiplexer (MUX) realizes, and control switch unit SW11～SW22 can be realized by various transistor switch.
As shown in Figure 4, current potential conversion unit LS11～LS22 is electrically connected at sequential control device 160, and wherein current potential conversion unit LS11 is in order to receive reference voltage VGH1, reference voltage VGL1 and switch controlling signal CS and corresponding output signal DS1. Signal DS1 has the first activation voltage of the first level and has the first forbidden energy voltage of the 2nd level. Current potential conversion unit LS12 is in order to receive reference voltage VGH2, reference voltage VGL2 and switch controlling signal CS and corresponding output signal DS2. Signal DS2 has the first activation voltage of the 3rd level and has the first forbidden energy voltage of the 4th level. In some embodiments, current potential changes unit LS11～LS22, and any one can receive reference voltage VGH1, VGH2 and reference voltage VGL1, VGL2 simultaneously, and exports scan control signal CTR according to this.
Control switch unit SW11 is electrically connected between current potential conversion unit LS11 and first control line CL1_R, CL1_G, CL1_B, and the control end of control switch unit SW11 receives polarity inversion signal POL. Control switch unit SW12 is electrically connected between current potential conversion unit LS12 and first control line CL1_R, CL1_G, CL1_B, and the control end of control switch unit SW12 receives the polarity inversion signal with polarity inversion signal POL complementation. By this, control module 144 can according to the keying of polarity inversion signal POL control switch unit SW11, SW12 to export the first control signal CS1_R, CS1_G, CS1_B.
Similarly, current potential conversion unit LS21 is also in order to receive reference voltage VGH1, reference voltage VGL1 and switch controlling signal CS and corresponding output signal DS3. Signal DS3 has the 2nd activation voltage of the first level and has the 2nd forbidden energy voltage of the 2nd level. Current potential conversion unit LS22 is in order to receive reference voltage VGH2, reference voltage VGL2 and switch controlling signal CS and corresponding output signal DS4. Signal DS4 has the 2nd activation voltage of the 3rd level and has the 2nd forbidden energy voltage of the 4th level.
Control switch unit SW21 is electrically connected between current potential conversion unit LS21 and the 2nd control line CL2_R, CL2_G, CL2_B, and the control end of control switch unit SW21 receives the polarity inversion signal with polarity inversion signal POL complementation. Control switch unit SW22 is electrically connected between current potential conversion unit LS22 and the 2nd control line CL2_R, CL2_G, CL2_B, and the control end of control switch unit SW22 receives polarity inversion signal POL. By this, control module 144 can according to the keying of polarity inversion signal POL control switch unit SW21, SW22 to export the 2nd control signal CS2_R, CS2_G, CS2_B.
Specifically, it is straight polarity data voltage when polarity inversion signal POL represents data voltage S1, when data voltage S2 is negative polarity data voltage, control switch unit SW11 conducting, control switch unit SW12 turn off so that control module 144 exports to be had the first activation voltage of the first level (as: 14.5V) and has signal DS1 to the first control line CL1_R, CL1_G, CL1_B of the first forbidden energy voltage of the 2nd level (as:-1.5V). In addition, control switch unit SW22 conducting, control switch unit SW21 turn off so that the 2nd activation voltage that control module 144 output has the 3rd level (as: 8V) and there is the 2nd forbidden energy voltage of the 4th level (as:-8V) signal DS4 to the 2nd control line CL2_R, CL2_G, CL2_B.
On the other hand, it is negative polarity data voltage when polarity inversion signal POL represents data voltage S1, when data voltage S2 is straight polarity data voltage, control switch unit SW11 turns off, control switch unit SW12 conducting so that control module 144 exports to be had the first activation voltage of the 3rd level (as: 8V) and has signal DS2 to the first control line CL1_R, CL1_G, CL1_B of the first forbidden energy voltage of the 4th level (as:-8V). Control switch unit SW22 turns off, control switch unit SW21 conducting so that control module 144 exports the 2nd activation voltage with the first level (as: 14.5V) and the signal DS3 with the 2nd forbidden energy voltage of the 2nd level (as:-1.5V) to the 2nd control line CL2_R, CL2_G, CL2_B.
Thus, control module 144 just exportable the first control signal CS1_R, CS1_G, CS1_B and the 2nd control signal CS2_R, CS2_G, CS2_B shown as depicted in fig. 3 to multiplexer module 142, to control the keying of the first switch S W1_R in multiplexer module 142, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B, it is achieved the operation of switch circuit 140. By this, display unit 100 just can pass through each pixel in the co-operating driving pel array 120 of sequential control device 160, source electrode driver 130, gate drivers 150 and switch circuit 140.
It is noted that the multiplexer module 142 shown in Fig. 2 is only one of possible enforcement mode of content of the present invention, it does not mean to limit content of the present invention. Please refer to Fig. 5. Fig. 5 is the schematic diagram of the multiplexer module 142 illustrated according to other part embodiments of content of the present invention. Compared with Fig. 2, in the multiplexer module 124 that Fig. 5 illustrates, in order to receive control signal CS_11, to control, it opens and closes the control end of switch S W_R11, SW_G11, SW_B11, in order to receive control signal CS_12, to control, it opens and closes the control end of switch S W_R12, SW_G12, SW_B12, in order to receive control signal CS_21, to control, it opens and closes the control end of switch S W_R21, SW_G21, SW_B21, and in order to receive control signal CS_22, to control, it opens and closes the control end of switch S W_R22, SW_G22, SW_B22. Data voltage S1 optionally provides according to the keying of switch S W_R11, SW_B12 and drives electric current to data line DL1, DL3, and data voltage S2 optionally provides according to the keying of switch S W_G21, SW_R22 and drives electric current to data line DL2, DL4.
Similarly, data voltage S3 optionally provides according to the keying of switch S W_G11, SW_R12 and drives electric current to data line DL5, DL7, and data voltage S4 optionally provides according to the keying of switch S W_B21, SW_G22 and drives electric current to data line DL6, DL8. Data voltage S5 optionally provides according to the keying of switch S W_B11, SW_G12 and drives electric current to data line DL9, DL11, and data voltage S6 optionally provides according to the keying of switch S W_R21, SW_B22 and drives electric current to data line DL10, DL12. When data voltage S1, S3, S5 are in straight polarity, data voltage S2, S4, S6 are in negative polarity. When data voltage S1, S3, S5 are in negative polarity, data voltage S2, S4, S6 are in straight polarity.
Thus, the multiplexer module 142 that Fig. 5 illustrates, can be dispensed to 12 data line DL1～DL12 by the driving electric current that six groups of data voltage S1～S6 provide. In other words, in the different embodiment of content of the present invention, can freely adjust within period D1～Dn, to be split how many periods.In the multiplexer module 142 shown in Fig. 2, a period is divided into three periods, and the blocked operation according to six control signals exports the driving electric current that data voltage S1 provides to data line DL1, DL3, DL5 respectively, the driving electric current that data voltage S2 provides exports data line DL2, DL4, DL6 respectively to, analogizes with this. On the other hand, in the multiplexer module 142 shown in Fig. 5, a period is divided into two periods, and the blocked operation according to four control signals exports the driving electric current that data voltage S1 provides to data line DL1, DL3 respectively, the driving electric current that data voltage S2 provides exports data line DL2, DL4 respectively to, analogizes with this.
Please refer to Fig. 6. Fig. 6 is the schematic diagram of the multiplexer module 142 illustrated according to the other part embodiment of content of the present invention. Compared with Fig. 2, in the multiplexer module 124 that Fig. 5 illustrates, the first switch S W1_R, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B are all realized by P type metal oxide semiconductor transistor (PMOS). Relatively, in the embodiment that Fig. 2 illustrates, the first switch S W1_R, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B are all by N-type MOS (metal-oxide-semiconductor) transistor (NMOS) implementation.
In some embodiments, in other words, the first switch S W1_R of multiplexer module 142, SW1_G, SW1_B and the 2nd switch S W2_R, SW2_G, SW2_B are with the N-type of homotype or P type metal oxide semiconductor transistor implementation. Due to each embodiment breaker in middle circuit 140 of content of the present invention between picture frame and picture frame, carry out dipole inversion time, through the voltage quasi position maintenance charging efficiency of adjustment activation voltage and forbidden energy voltage. By this, in content of the present invention, the switch in multiplexer module 142 can replace CMOS (CMOS) with N-type or P type metal oxide semiconductor transistor, reduces the processing procedure cost of multiplexer when not sacrificing charging efficiency.
In sum, content of the present invention is through application above-described embodiment, the voltage quasi position of the control signal that corresponding switching multiplexer receives in different picture frame, the power needed for driving circuit can be saved, and in maintenance to the processing procedure simplifying multiplexer when pixel charging efficiency, reduce the holistic cost of driving circuit.
Although content of the present invention is to implement mode openly as above; but it also is not used to limit content of the present invention; the technician of any this area; in the spirit and scope not departing from content of the present invention; when making various changes or modifications, therefore the protection domain of content of the present invention is when being as the criterion depending on the accompanying claims person of being defined.
Claims (10)
1. a driving circuit, it is characterised in that, comprise:
Many the first control lines, in order to transmit multiple first control signal;
Many articles of the 2nd control lines, in order to transmit multiple 2nd control signal;
Multiple first switch, a control end of those the first switches is in order to receive one corresponding in those first control signals; And
Multiple 2nd switch, a control end of those the 2nd switches is in order to receive one corresponding in those the 2nd control signals;
Wherein those first control signals switch between one first activation voltage and one first forbidden energy voltage, with those first switches of conducting, those the 2nd control signals switch between one the 2nd activation voltage and one the 2nd forbidden energy voltage, with those the 2nd switches of conducting, 2nd activation voltage is different from this first activation voltage, and the 2nd forbidden energy voltage is different from this first forbidden energy voltage.
2. driving circuit as claimed in claim 1, it is characterized in that, this driving circuit is in order to drive the multiple pixels in a pel array, wherein a first end of those the first switches is electrically connected to each other, of those the first switches the 2nd end is electrically connected at one corresponding in many articles of the first data lines respectively, when those pixels corresponding on those first data lines are in straight polarity, this the first activation voltage has one first level, this the first forbidden energy voltage has one the 2nd level, when those pixels corresponding on those first data lines are in negative polarity, this the first activation voltage has one the 3rd level being different from this first level, this the first forbidden energy voltage has one the 4th level being different from the 2nd level.
3. driving circuit as claimed in claim 2, it is characterized in that, one first end of those the 2nd switches is electrically connected to each other, one the 2nd end of those the 2nd switches is electrically connected at one corresponding in multiple 2nd data line respectively, when those pixels corresponding on those the 2nd data lines are in straight polarity, 2nd activation voltage has this first level, 2nd forbidden energy voltage has the 2nd level, when those pixels corresponding on those the 2nd data lines are in negative polarity, 2nd activation voltage has and is different from the 3rd level, 2nd forbidden energy voltage has the 4th level.
4. driving circuit as claimed in claim 1, it is characterised in that, also comprise:
One control module, comprises:
One first current potential conversion unit, in order to receive one first reference voltage, one the 2nd reference voltage and a switch controlling signal, and corresponding output has this first activation voltage of this first level and has this first forbidden energy voltage of the 2nd level;
One the 2nd current potential conversion unit, in order to receive one the 3rd reference voltage, one the 4th reference voltage and this switch controlling signal and corresponding output has this first activation voltage of the 3rd level and has this first forbidden energy voltage of the 4th level;
One first control switch unit, is electrically connected between this first current potential conversion unit and those the first control lines; And
One the 2nd control switch unit, is electrically connected between the 2nd current potential conversion unit and those the first control lines;
Wherein this control module according to a polarity inversion signal control this first control switch unit with the 2nd control switch unit keying to export those the first control signals.
5. a display unit, it is characterised in that, comprise:
Multi-strip scanning line;
A plurality of data lines, those data lines comprise many articles of the first data lines being spaced arrangement and many articles of the 2nd data lines;
One pel array, comprises multiple pixel, and those pixels are electrically connected at the corresponding one of those sweep traces and the corresponding one of those data lines; And
One switch circuit, it is electrically connected at those data lines, in order to receive one first data voltage and one the 2nd data voltage, and switch the voltage quasi position of multiple first control signal and multiple 2nd control signal in this switch circuit according to this first data voltage and the 2nd data voltage polarity separately.
6. display unit as claimed in claim 5, it is characterised in that, this switch circuit comprises:
Many the first control lines, in order to transmit those the first control signals;
Many articles of the 2nd control lines, in order to transmit those the 2nd control signals;
Multiple first switch, those first switches in order to according to those the first control signal optionally conductings, to provide one corresponding in this first data voltage to those first data lines; And
Multiple 2nd switch, those the 2nd switches are in order to according to those the 2nd control signal optionally conductings, and to provide one corresponding in the 2nd data voltage to those the 2nd data lines, wherein the 2nd data voltage and this first data voltage polarity are different;
Wherein those first control signals switch between one first activation voltage and one first forbidden energy voltage, with those first switches of conducting, those the 2nd control signals switch between one the 2nd activation voltage and one the 2nd forbidden energy voltage, with those the 2nd switches of conducting, 2nd activation voltage is different from this first activation voltage, and the 2nd forbidden energy voltage is different from this first forbidden energy voltage.
7. display unit as claimed in claim 6, it is characterised in that, this switch circuit also comprises:
One control module, is electrically connected at those first control lines and those the 2nd control lines, in order to export those first control signals and those the 2nd control signals according to a polarity inversion signal;
Wherein when to represent this first data voltage be straight polarity data voltage to this polarity inversion signal, this control module exports this first activation voltage with one first level and this first forbidden energy voltage with one the 2nd level to those the first control lines, and exports the 2nd forbidden energy voltage having the 2nd activation voltage of one the 3rd level being different from this first level and having one the 4th level being different from the 2nd level to those the 2nd control lines.
8. display unit as claimed in claim 7, it is characterized in that, when to represent the 2nd data voltage be straight polarity data voltage to this polarity inversion signal, this control module exports this first activation voltage with the 3rd level and this first forbidden energy voltage with the 4th level to those the first control lines, and the 2nd forbidden energy voltage exporting the 2nd activation voltage with this first level and having the 2nd level is to those the 2nd control lines.
9. display unit as claimed in claim 7, it is characterised in that, also comprise time schedule controller, in order to export a switch controlling signal to this switch circuit;
Wherein this control module comprises:
One first current potential conversion unit, in order to receive one first reference voltage, one the 2nd reference voltage and this switch controlling signal and corresponding output has this first activation voltage of this first level and has this first forbidden energy voltage of the 2nd level;
One the 2nd current potential conversion unit, in order to receive one the 3rd reference voltage, one the 4th reference voltage and this switch controlling signal and corresponding output has this first activation voltage of the 3rd level and has this first forbidden energy voltage of the 4th level;
One first control switch unit, is electrically connected between this first current potential conversion unit and those the first control lines; And
One the 2nd control switch unit, is electrically connected between the 2nd current potential conversion unit and those the first control lines;
This control module according to this polarity inversion signal control this first control switch unit with the 2nd control switch unit keying to export those the first control signals.
10. display unit as claimed in claim 7, it is characterized in that, the phase place of those the first control signals is different, to provide this first data voltage to those the first data lines, the phase place of those the 2nd control signals is different, to provide the 2nd data voltage to those the 2nd data lines.
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| TW105105146A TWI579823B (en) | 2016-02-22 | 2016-02-22 | Display device and driving circuit thereof |
| TW105105146 | 2016-02-22 |
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Also Published As
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| TWI579823B (en) | 2017-04-21 |
| TW201730869A (en) | 2017-09-01 |
| CN105679272B (en) | 2017-12-22 |
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