CN108806586A - Display panel, its driving method and display device - Google Patents

Display panel, its driving method and display device Download PDF

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Publication number
CN108806586A
CN108806586A CN201811003751.3A CN201811003751A CN108806586A CN 108806586 A CN108806586 A CN 108806586A CN 201811003751 A CN201811003751 A CN 201811003751A CN 108806586 A CN108806586 A CN 108806586A
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China
Prior art keywords
control signal
clock control
clock
line
sub
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CN201811003751.3A
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CN108806586B (en
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关琳燕
杨康鹏
许育民
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Xiamen Tianma Microelectronics Co Ltd
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Xiamen Tianma Microelectronics Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a kind of display panels, its driving method and display device, the first multi-channel gating device is controlled to realize the control to the first data line in the first viewing area by the first clock control signal, signal, which is controlled, by second clock controls the second multi-channel gating device to realize the control to the second data line in the second viewing area, and the first clock control signal is different with second clock control signal, so as to which the charging situation of the first data line and the second data line is separately controlled, so that the voltage of the data-signal of the first data line of input and the second data line, it is adjusted accordingly according to actually detected brightness, to make the display homogeneity of display panel improve.

Description

Display panel, its driving method and display device
Technical field
The present invention relates to display technology field, more particularly to a kind of display panel, its driving method and display device.
Background technology
With the development of display technology, screen is with its frame with larger screen accounting, ultra-narrow comprehensively, with common display Screen is compared, and the visual effect of viewer can be greatly improved, to have received widespread attention.Currently, shield comprehensively in use In the display device of such as mobile phone, in order to realize self-timer and call function, usually it can all be arranged in the front of display device preposition Camera, receiver etc..In order to realize that full frameization is shown, the planar structure schematic diagram of display panel as shown in Figure 1, in display surface The hollow-out parts 110 for the devices such as front camera, receiver to be arranged are typically provided in plate.However, depositing due to hollow-out parts 110 Causing the quantity of each column pixel in 110 region 1 of hollow-out parts less than the quantity of each column pixel in remaining region 2, to lead It causes the load (RC loading) of data line and the data line in remaining region 2 in region 1 to have differences, leads to region in this way 1 with the data line in region 2 in transmission data signal it is existing delay will be different, lead to the voltage of input data line not Uniformly, the non-uniform problem of display of display panel is in turn resulted in.
Invention content
A kind of display panel of offer of the embodiment of the present invention, its driving method and display device, to solve in the prior art The existing non-uniform problem of display.
A kind of driving method of display panel provided in an embodiment of the present invention, the display panel include at least one The array substrate of hollow-out parts；The array substrate includes：Viewing area and non-display area；The viewing area include the first viewing area and Second viewing area, the hollow-out parts are located at first viewing area, and first viewing area includes a plurality of first data line；It is described Second viewing area includes a plurality of second data line；The non-display area includes：Multiple first multi-channel gating devices, multiple second multichannels It gate, the first clock control of N items line, N second clock control line and is corresponded with each first clock control line Switch unit；Wherein, first multi-channel gating device is connect with the first data line described in M items, one more than described second Road gate is connect with the second data line described in M items；All first multi-channel gating devices and the first clock control of N items line Electrical connection；All second multi-channel gating devices are electrically connected with the N second clock control line；Each first clock control Line is connect by corresponding switch unit with first control signal end, the control terminal and second control signal of each switch unit End connection；N >=M >=3 and be integer；
The driving method includes：
In data input phase in a vertical interval, to first control signal end load the first control letter Number, second control signal is loaded to the second control signal end, controls clock when each switch unit makes each described first Line processed loads the first clock control signal, and first data line is made to input corresponding data-signal；Simultaneously to each described second Clock control line loads second clock and controls signal, and second data line is made to input corresponding data-signal；Wherein, described One clock control signal is different from the second clock control signal of signal.
The embodiment of the present invention additionally provides a kind of display panel, is driven using driving method provided in an embodiment of the present invention.
The embodiment of the present invention additionally provides a kind of display device, including：Driving device provided in an embodiment of the present invention and sheet The display panel that inventive embodiments provide.
The present invention has the beneficial effect that：
Display panel, its driving method and display device provided in an embodiment of the present invention, pass through the first clock control signal The first multi-channel gating device is controlled to realize to the control of the first data line in the first viewing area, signal is controlled by second clock The second multi-channel gating device is controlled to realize the control to the second data line in the second viewing area, and the first clock control signal It is different with second clock control signal, so as to which the charging situation of the first data line and the second data line is separately controlled, so that The voltage for inputting the data-signal of the first data line and the second data line, adjusts accordingly according to actually detected brightness, to The display homogeneity of display panel is set to improve.
Description of the drawings
Fig. 1 is the structural schematic diagram of display panel in the prior art；
Fig. 2 is one of the structural schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 3 is the second structural representation of display panel provided in an embodiment of the present invention；
Fig. 4 is one of the concrete structure schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 5 is one of circuit timing diagram provided in an embodiment of the present invention；
Fig. 6 is the two of the concrete structure schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 7 is the two of circuit timing diagram provided in an embodiment of the present invention；
Fig. 8 is the three of the concrete structure schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 9 is the three of circuit timing diagram provided in an embodiment of the present invention；
Figure 10 is the four of circuit timing diagram provided in an embodiment of the present invention；
Figure 11 is the five of circuit timing diagram provided in an embodiment of the present invention；
Figure 12 is the structural schematic diagram of display device provided in an embodiment of the present invention.
Specific implementation mode
In order to make the purpose of the present invention, technical solution and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention The specific implementation mode of the display panel of offer, its driving method and display device is described in detail.It should be appreciated that following Described preferred embodiment is only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.And in the feelings not conflicted Under condition, the features in the embodiments and the embodiments of the present application can be combined with each other.
It should be noted that each layer film thickness and shape do not reflect the actual proportions of display panel in attached drawing, purpose is only It is schematically illustrate the content of present invention.And same or similar label indicates same or similar element or has phase from beginning to end Same or similar functions elements.
As shown in Figure 2 and Figure 3, display panel provided in an embodiment of the present invention may include having at least one hollow-out parts 110 array substrate 100.Array substrate 100 includes：Viewing area AA and non-display area BB；Wherein, non-display area can surround aobvious Show that area, Fig. 2 and Fig. 3 are only illustrated by taking the non-display area of dotted line frame BB marks as an example.Viewing area AA includes the first viewing area aa_ The 1 and second viewing area aa_2, hollow-out parts 110 are located at the first viewing area aa_1, and the first viewing area aa_1 includes a plurality of first data Line D1；Second viewing area aa_2 includes a plurality of second data line D2.Non-display area BB includes：Multiple first multi-channel gating devices 210, Multiple second multi-channel gating devices 220, N items the first clock control line CK1_n (1≤n≤N and be integer), N second clock control Line CK2_n and with each one-to-one switch unit 230_n of first clock control line CK1_n；Wherein, first multichannel Gate 210 is connect with the first data line of M items D1, and second multi-channel gating device 220 is connect with the second data line of M items D2；Institute There is the first multi-channel gating device 210 to be electrically connected with N items the first clock control line CK1_n；All second multi-channel gating devices 220 and N items The CK2_n electrical connections of second clock control line；Each first clock control line CK1_n passes through corresponding switch unit 230_n and first The control terminal of control signal end V1 connections, each switch unit 230_n is connect with second control signal end V2；N >=M >=3 and to be whole Number.
In the specific implementation, in embodiments of the present invention, as shown in Figures 2 to 6, viewing area AA can also include：It is a plurality of (k is the integer more than or equal to 1 and less than or equal to K to grid line G_k, and K is the sum of grid line in display panel；Wherein Fig. 2 extremely schemes 5 by taking K=6 as an example, and Fig. 6 is by taking K=3 as an example).Also, the first viewing area aa_1 and the second viewing area aa_2 can also include：Array Multiple pixel PX of arrangement；Wherein, each pixel PX may include：Y different colours sub-pixel being arranged in order；Y >=3 and to be whole Number.It is controlled by same a line grid line G_k with a line sub-pixel in first viewing area aa_1 and the second viewing area aa_2.And one article One data line D1 is correspondingly connected with the row sub-pixel in the first viewing area aa_1, and it is aobvious that a second data line D2 is correspondingly connected with second Show the row sub-pixel in area aa_2.
Further, in the specific implementation, as shown in Figure 4 and Figure 5, Y could be provided as 3, and pixel PX may include along Red sub-pixel R that one direction F1 is arranged in order, green sub-pixels G, blue subpixels B.Alternatively, as shown in fig. 6, Y can also 4 are set as, pixel PX may include red sub-pixel R, green sub-pixels G, the sub- picture of blue being arranged in order along first direction F1 Plain B, white sub-pixels W.Certainly, Y may be set to be other numerical value, this needs to design determination according to actual application environment, It is not limited thereto.
Realize hollow-out parts 110 embodiment can there are many, below by implementation to hollow-out parts 110 when specific implementation Mode illustrates.In the specific implementation, in some possible embodiments, as shown in Fig. 2, the first viewing area aa_1 and Two viewing area aa_1 are arranged along first direction F1；F2 prolongs each first data line D1 and each second data line D2 in a second direction respectively It stretches, i.e. the first data line D1 and the second data line D2 are the straight line that F2 extends in a second direction respectively.Hollow-out parts 110 are set to battle array The first data line D1 in row substrate 110 deviates from the edge of 210 side of the first multi-channel gating device；Wherein, first direction F1 and Two direction F2 are vertical.
In other possible embodiments, in the specific implementation, as shown in figure 3, the first viewing area aa_1 and second Viewing area aa_2 is arranged along first direction F1；First viewing area aa_1 surrounds hollow-out parts 110, and the first data line D1 may include： Unconventional branch in the conventional branch that F2 extends in a second direction and the first viewing area aa_1 around hollow-out parts 110； Wherein, conventional branch and unconventional the branch electrical connection of same first data line D1；Each second data line D2 is in a second direction F2 extends；Wherein, first direction F1 is vertical with second direction F2.Also, first direction F1 can be the line direction of pixel PX, the Two direction F2 can be the column direction of pixel PX；Or conversely, first direction F1 can be the column direction of pixel PX, second direction F2 can be the line direction of pixel PX.In practical applications, first direction and second direction can according to actual application environment come Design determines, is not limited thereto.
Since hollow-out parts 110 are arranged in the first viewing area aa_1 so that of the sub-pixel of the first data line D1 electrical connections Number is less than the number of the sub-pixel of the second data line D2 electrical connections, so as to cause load and the second data line of the first data line D1 The load of D2 is different, and the first data line D1 existing delays in transmission data signal is caused to be passed with the second data line D2 in this way Existing delay is different when transmission of data signal, and then leads to the pixel voltage for being input to the sub-pixel of the first data line D1 electrical connections It is different from the pixel voltage of sub-pixel for being input to the second data line D2, it causes to show non-uniform problem.Such as it is input to The pixel voltage of the sub-pixel of one data line D1 electrical connections is more than the pixel voltage for the sub-pixel for being input to the second data line D2, leads The brightness of the first viewing area is caused to be more than the brightness of the second viewing area.Therefore, in order to make the first viewing area aa_1 and the second viewing area The brightness homogeneity of aa_2 improves, and an embodiment of the present invention provides a kind of driving methods, to improve display homogeneity.
The driving method of display panel provided in an embodiment of the present invention may include：Data in a vertical interval are defeated Enter in the stage, first control signal is loaded to first control signal end V1, to second control signal end V2 loads the second control letter Number, controlling each switch unit 230_n makes each first clock control line CK1_n load the first clock control signal, makes the first data Line D1 inputs corresponding data-signal；Signal is controlled to each second clock control line CK2_n load second clocks simultaneously, makes second Data line D2 inputs corresponding data-signal；Wherein, the first clock control signal is different from the second clock control signal of signal. Also, the first multi-channel gating device can work under the control of the significant level of the first clock control signal, so that the first data Line inputs corresponding data-signal.Second multi-channel gating device can second clock control signal significant level control under work Make, so that the second data line inputs corresponding data-signal.
The driving method of above-mentioned display panel provided in an embodiment of the present invention controls first by the first clock control signal Multi-channel gating device controls signal control second to realize the control to the first data line in the first viewing area, by second clock Multi-channel gating device is to realize the control to the second data line in the second viewing area, and the first clock control signal and when second Clock signal is different, so as to which the charging situation of the first data line and the second data line is separately controlled, so that input first The voltage of the data-signal of data line and the second data line, adjusts accordingly according to actually detected brightness, to make display surface The display homogeneity of plate improves.
In embodiments of the present invention, array substrate can also include the lining that each first data line, each second data line is arranged Substrate.The underlay substrate can be glass substrate, flexible base board, silicon substrate etc., be not limited thereto.In display panel applications When in display device, the devices such as camera, receiver generally can be also set, therefore in order to which the devices such as camera, receiver are arranged, engrave Empty portion can be the void region of underlay substrate.I.e. in actual fabrication process, by using the mode of cutting by underlay substrate The region removal of middle corresponding hollow-out parts becomes void region, for the devices such as camera, receiver are arranged in a display device Part.Alternatively, underlay substrate can not also be cut, but by making the circuit on underlay substrate be avoided, so that right It is transparent region to answer the region of hollow-out parts.
In the specific implementation, in embodiments of the present invention, as shown in Figures 2 to 6, display panel can also include：It is a plurality of (i is the integer more than or equal to 1 and less than or equal to I to first source electrode input line S1_i, and I is that the first source electrode is defeated in display panel Enter the sum of line；Wherein Fig. 2 to Fig. 5 is by taking I=2 as an example, and Fig. 6 is by taking I=1 as an example) (j is with a plurality of second source electrode input line S2_j Integer more than or equal to 1 and less than or equal to J, J are the sum of the second source electrode input line in display panel；Wherein Fig. 2 to Fig. 5 By taking J=2 as an example, Fig. 6 is by taking J=1 as an example)；Wherein, a first source electrode input line S1_i passes through first multi-channel gating device 210 connect with the first data line of M items D1；One the second source electrode input line S2_j passes through second multi-channel gating device 220 and M items Second data line D2 connects.
Further, in the specific implementation, in embodiments of the present invention, M=3 can be made；Wherein, the first multichannel choosing Logical device 210 can the first data corresponding with red sub-pixel R, green sub-pixels G, blue subpixels B in a pixel PX Line D1 electrical connection, second multi-channel gating device 220 can in a pixel PX red sub-pixel R, green sub-pixels G, The corresponding second data line D2 electrical connections of blue subpixels B.Alternatively, in the specific implementation, as shown in figs. 4 and 5, in the present invention In embodiment, two neighboring first multi-channel gating device 210 corresponds to two neighboring pixel PX；One of them first multi-channel gating device 210 corresponding with red sub-pixel R, the blue subpixels B of odd column in 2 adjacent pixel PX and green sub-pixels G One data line D1 electrical connections.The red sub-pixel of another first multi-channel gating device 210 and even column in 2 adjacent pixel PX R, the corresponding first data line D1 electrical connections of blue subpixels B and green sub-pixels G.Two neighboring second multi-channel gating device 220 correspond to two neighboring pixel PX；One of them second multi-channel gating device 220 in 2 adjacent pixel PX odd column it is red Sub-pixels R, blue subpixels B and the corresponding second data line D2 electrical connections of green sub-pixels G.Another second multichannel is selected Logical device 220 is corresponding with red sub-pixel R, the blue subpixels B of even column and green sub-pixels G in 2 adjacent pixel PX The second data line D2 electrical connection.
In the specific implementation, in embodiments of the present invention, the first multi-channel gating device 210 may include：With the first data of M items The one-to-one M first switching element of line D1, each first switching element include at least one third transistor M3；Wherein, First data line D1 is electrically connected by corresponding third transistor M3 with corresponding first source electrode input line S1_i, third transistor The grid of M3 is electrically connected with a first clock control line.Also, the second multi-channel gating device 220 may include：It is counted with M items second According to the one-to-one M second switch elements of line D2, each second switch element includes at least one 4th transistor M4；Its In, the second data line D2 is electrically connected by corresponding 4th transistor M4 with corresponding second source electrode input line S2_j, and the 4th is brilliant The grid of body pipe M4 is electrically connected with a second clock control line.
Further, in the specific implementation, in embodiments of the present invention, as shown in figs. 4 and 5, first switching element can To include a third transistor M3, second switch element may include a 4th transistor M4, therefore can make N=M, i.e., One first clock control line is corresponding with first data line that each first multi-channel gating device 210 connects.One second clock Control line is corresponding with second data line that each second multi-channel gating device 220 connects.Also, third transistor M3 can be arranged For N-type transistor, the 4th transistor M4 could be provided as N-type transistor, can be connected under the control of high level signal, End under the control of low level signal, therefore the significant level of the first clock control signal and second clock control the effective of signal Level could be provided as high level.Alternatively, third transistor M3 may be set to be P-type transistor, the 4th transistor M4 also may be used To be set as P-type transistor, it can be connected under the control of low level signal, end under the control of high level signal, because The significant level of significant level and second clock the control signal of this first clock control signal could be provided as low level.
Alternatively, in the specific implementation, in embodiments of the present invention, as shown in fig. 6, first switching element may include two Third transistor M3.It can make N=2M in this way, so that the first multi-channel gating device 210 connects with 2M items the first clock control line CK1_n It connects.Wherein, a third transistor M3 in the two third transistor M3 can be N-type transistor, another third crystal Pipe M3 can be P-type transistor.N-type third transistor M3 in same first multi-channel gating device 210 respectively with the first clock Control line CK1_1~CK1_4 connections, p-type third transistor M3 are connect with first clock control line CK1_5~CK1_8 respectively.Its In, CK1_1 and CK1_5 cycle phases with and opposite in phase；CK1_2 and CK1_6 cycle phases with and opposite in phase；CK1_3 and CK1_7 Cycle phase with and opposite in phase；CK1_4 and CK1_8 cycle phases with and opposite in phase.Second switch element may include two Four transistor M4, so that the second multi-channel gating device 220 is connect with 2M second clock control line CK2_n.Wherein, the two the 4th A the 4th transistor M4 in transistor M4 can be N-type transistor, another the 4th transistor M4 can be P-type crystal Pipe.The 4th transistor M4 of N-type in same second multi-channel gating device 220 respectively with second clock control line CK2_1~CK2_4 Connection, the 4th transistor M4 of p-type are connect with second clock control line CK2_5~CK2_8 respectively.Wherein, CK2_1 with CK2_5 weeks Phase is identical and opposite in phase；CK2_2 and CK2_6 cycle phases with and opposite in phase；CK2_3 and CK2_7 cycle phases with and phase phase Instead；CK2_4 and CK2_8 cycle phases with and opposite in phase.
Further, in the specific implementation, in driving method provided in an embodiment of the present invention, clock when can make first The cycle phase of signal and second clock control signal processed is same.The first multi-channel gating device can be made in the first clock control signal in this way Significant level control under work, will data signal transmission to its connection the first data line of M items on.And make more than second Road gate works under the control of the significant level of second clock control signal, by data signal transmission to the M of its connection On the second data line of item.
In the specific implementation, in embodiments of the present invention, in a vertical interval, each second clock control letter can be made Number significant level voltage value it is identical and maintain duration it is identical.Further, as illustrated in figs. 7 and 8, the first clock control is believed Number ck1_n represents the signal being loaded on the first clock control line CK1_n, and second clock control signal ck2_n representatives are loaded into Signal on second clock control line CK2_n.
In the specific implementation, as shown in fig. 7, the voltage value of the significant level of the first clock control signal ck1_n can be made VGH1 is less than the voltage value VGH2 of the significant level of second clock control signal ck2_n.It can make beating for third transistor in this way The opening degree that degree is less than the 4th transistor is opened, so as to so as to be input to the picture in the sub-pixel of the first data line D1 connections Plain voltage reduces, and the brightness of the first viewing area can be made integrally to reduce in this way, so as to so that the first viewing area and the second display The brightness in area tends to be uniform.
In the specific implementation, as shown in figure 8, when can make the maintenance of the significant level of the first clock control signal ck1_n Long t1 is less than the maintenance duration t2 of the significant level of second clock control signal ck2_n.It can make beating for third transistor in this way ETAD expected time of arrival and departure is less than the opening time of the 4th transistor, so as to so as to be input to the picture in the sub-pixel of the first data line D1 connections Plain voltage reduces, and the brightness of the first viewing area can be made integrally to reduce in this way, so as to so that the first viewing area and the second display The brightness in area tends to be uniform.
In the specific implementation, in embodiments of the present invention, a vertical interval includes at least one data input phase；Its In, in same data input phase, the voltage value of the significant level of each first clock control signal is identical and maintains duration identical； And in different data input phase, in the voltage value and maintenance duration of the significant level of same first clock control signal at least One difference.To at least one in the voltage value and maintenance duration of the significant level by adjusting the first clock control signal Size, the brightness and the brightness of the second viewing area to make the first viewing area are approximately the same, and then improve and show homogeneity.
Specifically, it includes a data input phase that can make a vertical interval.In this way in a vertical interval, respectively The voltage value of the significant level of first clock control signal is identical and maintains duration identical.Alternatively, in practical applications, driving IC The data-signal of (Integrated Circuit, integrated circuit) output passes sequentially through multi-channel gating device and data line is input to son In pixel, due to the pixel voltage that is input to the closer sub-pixel of the first multi-channel gating device of distance decaying and be input to distance the The decaying of the pixel voltage of the sub-pixel of one multi-channel gating device farther out is different, consequently, it is possible to the first viewing area is caused to there is display The case where brightness irregularities.In order to further increase the display homogeneity of the first viewing area, in the specific implementation, a frame can be made Sweep time may include at least two data input phases.So that in same data input phase, each first clock control letter Number significant level voltage value it is identical and maintain duration it is identical；In different data input phase, same first clock control letter Number significant level voltage value and maintain duration at least one difference.Wherein, a vertical interval may include two, three A, four data input phases.The particular number of the data input phase can design determination according to actual application environment, This is not construed as limiting.In this way by adjusting the electricity of the significant level of same first clock control signal in different data input phase At least one size, can improve the brightness uniformity of the first viewing area in pressure value and maintenance duration.Specifically, it is swept in a frame When retouching the time including continuous multiple data input phases, it can make in different data input phase, first control signal has The voltage value for imitating level is different.It is of course also possible to when a vertical interval includes continuous multiple data input phases, make not With in data input phase, the maintenance duration of the significant level of second control signal is different.This is needed according to actual application environment Determination is designed, is not limited thereto.
It is illustrated so that a vertical interval includes a data input phase as an example below.
In some possible embodiments, it is illustrated in conjunction with such as Fig. 2 to Fig. 4 and Fig. 7.In the specific implementation, such as Shown in Fig. 7, signal is controlled by making the voltage value VGH1 of the significant level of the first clock control signal ck1_n be less than second clock The voltage value VGH2 of the significant level of ck2_n can be such that the brightness of the first viewing area reduces, to make the brightness of the first viewing area It is approximately the same with the brightness of the second viewing area, and then improve and show homogeneity.
In conjunction with as shown in Fig. 2 to Fig. 4 and Fig. 7, second control signal end V2 may include：With each switch unit 230_n One-to-one second sub-control signal end V2_n.Switch unit 230_n may include：The first transistor M1；Wherein, first is brilliant The grid of body pipe M1 is connected with corresponding second sub-control signal end V2_n, and the first pole of the first transistor M1 is believed with the first control Number end V1 connections, the second pole of the first transistor M1 are connected with corresponding first clock control signal end CK1_n.Specifically, One transistor M1 can be N-type transistor, then the significant level of the second sub-control signal could be provided as high level.Alternatively, the One transistor may be P-type transistor, then the significant level of the second sub-control signal could be provided as low level.
In driving method provided in an embodiment of the present invention, second control signal is loaded to second control signal end, specifically May include：
To each second sub-control signal end V2_n loads the second son identical with the second clock control signal sequence of signal Control signal；Wherein, second sub-control signal is corresponding with a second clock control signal sequence for signal.
Specifically, as shown in fig. 7, the second sub-control signal end V2_n load the second sub-control signal v2_n and second when The signal sequence of clock signal ck2_n corresponds to.That is, the second sub-control signal v2_1 is with second clock control signal ck2_1's Signal sequence corresponds to, and the second sub-control signal v2_2 is corresponding with the signal sequence of second clock control signal ck2_2, the second son control Signal v2_3 processed is corresponding with the signal sequence of second clock control signal ck2_3.
Specifically, as shown in fig. 7, the maintenance duration of the significant level of first control signal v1 is identical and swept not less than a line Retouch the time；And the voltage value VGH3 of the significant level of first control signal v1 is less than the significant level of second clock control signal Voltage value VGH2.When the voltage value VGH1 of the significant level of the first clock control signal ck1_n can be made to be less than second in this way The voltage value VGH2 of the significant level of clock signal ck2_n.
Further, in the specific implementation, as shown in fig. 7, can make each second sub-control signal v2_n respectively with it is corresponding Second clock control signal ck2_n it is identical.Further, as shown in figure 4, the identical second son control of load signal can be made Signal end V2_n is electrically connected with second clock control line CK2_n.Signal end and cabling can be saved in this way, reduce non-display area Occupied space.
A general vertical interval includes multiple horizontal-scanning intervals, with reference to Fig. 4 and Fig. 7, with to grid line G_1~G_ For 3 load grid open signal g_1~g_3, driving method provided in an embodiment of the present invention is illustrated.
In first horizontal-scanning interval T_1, to grid line G_1 load grid open signals g_1 so that each son of the first row Thin film transistor (TFT) in pixel is both turned on.When grid line G_1 loads grid open signal g_1, to each first source electrode input line S1_ I and each second source electrode input line S2_j distinguishes on-load voltage Vdata1, and to the first control of first control signal end V1 loads Signal v1, and signal ck2_n is controlled to second clock control line CK2_n load second clocks, it only controls and believes in second clock When number ck2_1 is high level, the first transistor M1 and the 4th transistor M4 of control second clock control line CK2_1 connections are led Logical, the 4th transistor M4 of conducting will load on the data-signal on the second source electrode input line S2_j, be supplied to the second viewing area In the first row red sub-pixel R in pixel electrode so that red sub-pixel R is filled with voltage Vdata1.The first of conducting First control signal v1 is supplied to the first clock control line CK1_1 by transistor M1, makes the first clock control line CK1_1 load the One clock control signal ck1_1.First clock control signal ck1_1 controls the third being connect with the first clock control line CK1_1 Transistor M3 conducting, will load on the data-signal on the first source electrode input line S1_i, the be supplied in the first viewing area Pixel electrode in a line red sub-pixel R, so that red sub-pixel R is filled with voltage Vdata2.
Similarly, the CK2_2 connections of second clock control line only are controlled when second clock control signal ck2_2 is high level The first transistor M1 and the 4th transistor M4 conductings, the picture in the first row green sub-pixels G in the second viewing area can be made Plain electrode is filled with voltage Vdata1, and the pixel electrode in the first row green sub-pixels G in the first viewing area is made to be filled with voltage Vdata2.And only when second clock control signal ck2_3 is high level, control second clock control line CK2_3 connections The first transistor M1 and the 4th transistor M4 conductings, can make the pixel in the first row blue subpixels B in the second viewing area Electrode is filled with voltage Vdata1, and the pixel electrode in the first row blue subpixels B in the first viewing area is made to be filled with voltage Vdata2。
Similarly, in second horizontal-scanning interval T_2, to grid line G_2 load grid open signals g_2 so that second Thin film transistor (TFT) in each sub-pixel of row is both turned on, so that the red sub-pixel R of the second row, the sub- picture of green in the first viewing area Plain G and blue subpixels B is filled with Vdata2 respectively, red sub-pixel R, the green sub-pixels G of the second row in the second viewing area And blue subpixels B is filled with Vdata1 respectively.And in a third horizontal-scanning interval T_3, grid is loaded to grid line G_3 Open signal g_3 so that the thin film transistor (TFT) in each sub-pixel of the third line is both turned on, so that the third line in the first viewing area Red sub-pixel R, green sub-pixels G and blue subpixels B are filled with Vdata2 respectively, the red of the third line in the second viewing area Sub-pixel R, green sub-pixels G and blue subpixels B are filled with Vdata1 respectively.
Signal is controlled since the voltage value VGH1 of the significant level of the first clock control signal ck1_n is less than second clock The voltage value VGH2 of the significant level of ck2_n, therefore can have Vdata2<Vdata1, to big by adjusting the voltage of VGH1 It is small, the brightness of the first viewing area can be made to reduce, to make the brightness of the first viewing area phase approximate with the brightness of the second viewing area Together, and then display homogeneity is improved.
In other possible embodiments, illustrated in conjunction with Fig. 5 and Fig. 8.In the specific implementation, as shown in figure 8, Control signal ck2_n's by making the maintenance duration t1 of the significant level of the first clock control signal ck1_n be less than second clock The maintenance duration t2 of significant level can be such that the brightness of the first viewing area reduces, to make the brightness and second of the first viewing area The brightness of viewing area is approximately the same, and then improves and show homogeneity.
In the specific implementation, in embodiments of the present invention, as shown in figure 5, first control signal end V1 may include：With it is each Switch unit 230_n one-to-one first sub-control signals end V1_n.Switch unit 230_n may include：Second transistor M2；Wherein, the grid of second transistor M2 is connected with second control signal end V2, the first pole of second transistor M2 with it is corresponding First sub-control signal end V1_n connections, the second pole of second transistor M2 are connected with corresponding first clock control line CK1_n. Specifically, second transistor M2 can be N-type transistor, then the significant level of second control signal could be provided as high level. Alternatively, second transistor may be P-type transistor, then the significant level of second control signal could be provided as low level.
In driving method provided in an embodiment of the present invention, second control signal is loaded to first control signal end, specifically May include：
To the end V1_n loads of each first sub-control signal the signal sequence of signal identical first is controlled with each second clock Sub-control signal v1_n；Wherein, when the signal of a first sub-control signal v1_n and a second clock control signal ck2_n Ordered pair is answered.Specifically, as shown in fig. 7, the signal sequence pair of the first sub-control signal v1_1 and second clock control signal ck2_1 It answers, the first sub-control signal v2_2 is corresponding with the signal sequence of second clock control signal ck2_2, the first sub-control signal v2_3 It is corresponding with the signal sequence of second clock control signal ck2_3.
In the specific implementation, as shown in Figure 8.When the appearance order of the significant level of second control signal V2 is with all second The appearance order of the significant level of clock signal ck2_n corresponds.And the dimension of the significant level of second control signal v2 Hold maintenance duration t2s of the duration t3 less than the significant level of second clock control signal ck2_n.
It is possible to further keep each first sub-control signal identical as corresponding second clock control signal respectively.Into one Step ground, as shown in figure 5, load signal identical first sub-control signal end V1_n and the first clock control signal line can be made CK1_n is electrically connected.Signal end and cabling can be saved in this way, reduce the occupied space of non-display area.
With reference to Fig. 5 and Fig. 8, for grid line G_1~G_3 load grid open signals g_1~g_3, to this hair The driving method that bright embodiment provides illustrates.
In first horizontal-scanning interval T_1, to grid line G_1 load grid open signals g_1 so that each son of the first row Thin film transistor (TFT) in pixel is both turned on.When grid line G_1 loads grid open signal g_1, to each first source electrode input line S1_ I and each second source electrode input line S2_j distinguishes on-load voltage Vdata1, and is loaded respectively to the first sub-control signal end V1_n First control signal v1_n loads second control signal v2 to second control signal end V2, and to second clock control line CK2_n loads second clock and controls signal ck2_n, only when second clock control signal ck2_1 is high level, when controlling second 4th transistor M4 conductings of clock control line CK2_1 connections, the 4th transistor M4 of conducting will load on the second source electrode input line Data-signal on S2_j, the pixel electrode being supplied in the first row red sub-pixel R in the second viewing area, so that the red Sub-pixel R is filled with voltage Vdata1.The control second transistor M2 conductings when second control signal v2 is high level, by first Sub-control signal v1_n is supplied to the first clock control line CK1_n, and the first clock control line CK1_n is made to load the first clock control Signal ck1_n.First clock control signal ck1_1 controls are led with the first clock control line CK1_1 third transistor M3 connecting It is logical, the data-signal on the first source electrode input line S1_i will be loaded on, the red son of the first row in the first viewing area is supplied to Pixel electrode in pixel R, so that red sub-pixel R is filled with voltage Vdata2.
Similarly, so that the pixel electrode in the first row green sub-pixels G in the second viewing area is filled with voltage Vdata1, make The pixel electrode in the first row green sub-pixels G in one viewing area is filled with voltage Vdata2.And make in the second viewing area Pixel electrode in the first row blue subpixels B is filled with voltage Vdata1, makes the first row blue subpixels B in the first viewing area In pixel electrode be filled with voltage Vdata2.
Similarly, in second horizontal-scanning interval T_2, to grid line G_2 load grid open signals g_2 so that second Thin film transistor (TFT) in each sub-pixel of row is both turned on, so that the red sub-pixel R of the second row, the sub- picture of green in the first viewing area Plain G and blue subpixels B is filled with Vdata2 respectively, red sub-pixel R, the green sub-pixels G of the second row in the second viewing area And blue subpixels B is filled with Vdata1 respectively.And in a third horizontal-scanning interval T_3, grid is loaded to grid line G_3 Open signal g_3 so that the thin film transistor (TFT) in each sub-pixel of the third line is both turned on, so that the third line in the first viewing area Red sub-pixel R, green sub-pixels G and blue subpixels B are filled with Vdata2 respectively, the red of the third line in the second viewing area Sub-pixel R, green sub-pixels G and blue subpixels B are filled with Vdata1 respectively.
Signal is controlled since the maintenance duration t1 of the significant level of the first clock control signal ck1_n is less than second clock The maintenance duration t2 of the significant level of ck2_n, therefore can have Vdata2<Vdata1 can be with to the size by adjusting t1 The brightness of the first viewing area is set to reduce, the brightness and the brightness of the second viewing area to make the first viewing area are approximately the same, in turn It improves and shows homogeneity.
In other possible embodiments, in the specific implementation, in embodiments of the present invention, as shown in fig. 7, can be with Make the significant level of the first clock control signal ck1_n maintains duration t1 to be less than the effective of second clock control signal ck2_n The maintenance duration t2 of level, and the voltage value VGH4 of the significant level of the first sub-control signal v1_n can also be made to be less than second The voltage value VGH2 of the significant level of clock control signal ck2_n, to also make effective electricity of the first clock control signal ck1_n Flat voltage value VGH1 is less than the voltage value VGH2 of the significant level of second clock control signal ck2_n.It not only can make The opening time of third transistor is less than the opening time of the 4th transistor, and the opening degree of third transistor can also be made to be less than The opening degree of 4th transistor further increases display homogeneity.At this point, when the first sub-control signal end V1_n is not with second The CK2_n electrical connections of clock control line.
It is illustrated so that a vertical interval includes at least two data input phases as an example below.A general data are defeated It may include a line or two rows or three rows or four horizontal-scanning intervals to enter the stage.In practical applications, data input phase includes The quantity of one horizontal-scanning interval can design determination according to actual application environment, be not limited thereto.Below with a number According to input phase including being illustrated for a horizontal-scanning interval.
It in some possible embodiments, can when a vertical interval includes continuous multiple data input phases So that in different data input phase, the voltage value of the significant level of first control signal is different.For example, can be continuous two In a data input phase, next data input phase is made to compare a upper data input phase, clock when making same first The voltage value of the significant level of signal processed increaseds or decreases, to improve the brightness homogeneity of the first viewing area.
Below in continuous data input phase, next data input phase compares a upper data input phase, It is illustrated for the voltage value increase of the significant level of each first clock control signal.
Specifically, as shown in figure 9, the first clock control signal ck1_n's in first horizontal-scanning interval T_1 is effective The significant level of the voltage value VGH11 of level, the first clock control signal ck1_n in second horizontal-scanning interval T_2 The voltage value of the significant level of the first clock control signal ck1_n in voltage value VGH12, third a horizontal-scanning interval T_3 VGH13 is successively increased.In this way in detecting the first viewing area the brightness on the first multi-channel gating device direction is directed toward by hollow-out parts When being sequentially reduced, by making next data input phase compare a upper data input phase, the data on the first data line The voltage of signal increases, so as to be directed toward the son on the first multi-channel gating device direction by hollow-out parts so as to be filled in the first viewing area The pixel voltage of pixel successively increases, and then can compensate the brightness of the first viewing area, and the display for improving the first viewing area is uniform Property.
In the specific implementation, as shown in Figure 3 and Figure 4, second control signal end V2 may include：With each switch unit 230_ N one-to-one second sub-control signals end V2_n.Switch unit 230_n may include：The first transistor M1；It is specifically connected Therefore not to repeat here for mode.
In driving method provided in an embodiment of the present invention, second control signal is loaded to second control signal end, specifically May include：To each second sub-control signal end V2_n loads the second son identical with the second clock control signal sequence of signal Control signal；Wherein, second sub-control signal is corresponding with a second clock control signal sequence for signal.
Specifically, as shown in figure 9, the second sub-control signal end V2_n load the second sub-control signal v2_n and second when The signal sequence of clock signal ck2_n corresponds to.That is, the second sub-control signal v2_1 is with second clock control signal ck2_1's Signal sequence corresponds to, and the second sub-control signal v2_2 is corresponding with the signal sequence of second clock control signal ck2_2, the second son control Signal v2_3 processed is corresponding with the signal sequence of second clock control signal ck2_3.
Further, in the specific implementation, as shown in figure 9, including continuous multiple data inputs in a vertical interval When the stage, in each data input phase, the maintenance duration of the significant level of first control signal v1 is identical and is not less than a line Sweep time T_k；Also, in continuous data input phase, next data input phase is inputted compared to a upper data The voltage value in stage, the significant level of first control signal v1 increases, and makes the significant level of each first clock control signal ck1_n Voltage value increase.That is the voltage value of the significant level of the first control signal v1 in first horizontal-scanning interval T_1 The voltage value VGH12 of the significant level of VGH11, first control signal v1 in second horizontal-scanning interval T_2, third one The voltage value VGH13 of the significant level of first control signal v1 in horizontal-scanning interval T_3 is successively increased.
Further, in order to make brightness in the first viewing area can be with even variation, in the specific implementation, of the invention real It applies in example, in continuous data input phase, the numerical value such as the voltage value of the significant level of first control signal can be made to increase. It can make the brightness in the first viewing area that can further increase display homogeneity with even variation in this way.
With reference to Fig. 4 and Fig. 9, for grid line G_1~G_3 load grid open signals g_1~g_3, to this hair The driving method that bright embodiment provides illustrates.
In first horizontal-scanning interval T_1, to grid line G_1 load grid open signals g_1 so that each son of the first row Thin film transistor (TFT) in pixel is both turned on.When grid line G_1 loads grid open signal g_1, to each first source electrode input line S1_ I and each second source electrode input line S2_j distinguishes on-load voltage Vdata1, and to the first control of first control signal end V1 loads Signal v1, and signal ck2_n is controlled to second clock control line CK2_n load second clocks, it only controls and believes in second clock When number ck2_1 is high level.The first transistor M1 and the 4th transistor M4 of control second clock control line CK2_1 connections are led Logical, the 4th transistor M4 of conducting will load on the data-signal on the second source electrode input line S2_j, be supplied to the second viewing area In the first row red sub-pixel R in pixel electrode so that red sub-pixel R is filled with voltage Vdata1.The first of conducting First control signal v1 is supplied to the first clock control line CK1_1 by transistor M1, makes the first clock control line CK1_1 load the One clock control signal ck1_1.First clock control signal ck1_1 controls the third being connect with the first clock control line CK1_1 Transistor M3 conducting, will load on the data-signal on the first source electrode input line S1_i, the be supplied in the first viewing area Pixel electrode in a line red sub-pixel R, so that red sub-pixel R is filled with voltage Vdata2.
Similarly, the CK2_2 connections of second clock control line only are controlled when second clock control signal ck2_2 is high level The first transistor M1 and the 4th transistor M4 conductings, the picture in the first row green sub-pixels G in the second viewing area can be made Plain electrode is filled with voltage Vdata1, and the pixel electrode in the first row green sub-pixels G in the first viewing area is made to be filled with voltage Vdata2。
And only the CK2_3 connections of second clock control line are controlled when second clock control signal ck2_3 is high level The first transistor M1 and the 4th transistor M4 conductings, the picture in the first row blue subpixels B in the second viewing area can be made Plain electrode is filled with voltage Vdata1, and the pixel electrode in the first row blue subpixels B in the first viewing area is made to be filled with voltage Vdata2.Signal is controlled since the voltage value VGH11 of the significant level of the first clock control signal ck1_n is less than second clock The voltage value VGH2 of the significant level of ck2_n, therefore can have Vdata2<Vdata1.
Similarly, in second horizontal-scanning interval T_2, to grid line G_2 load grid open signals g_2 so that second Thin film transistor (TFT) in each sub-pixel of row is both turned on, so that the red sub-pixel R of the second row, the sub- picture of green in the first viewing area Plain G and blue subpixels B is filled with Vdata3 respectively, red sub-pixel R, the green sub-pixels G of the second row in the second viewing area And blue subpixels B is filled with Vdata1 respectively.Due to the voltage value of the significant level of the first clock control signal ck1_n VGH12 is more than its voltage value VGH11 in first horizontal-scanning interval T_1, therefore can have Vdata3>Vdata2.With And in a third horizontal-scanning interval T_3, to grid line G_3 load grid open signals g_3 so that in each sub-pixel of the third line Thin film transistor (TFT) be both turned on so that the red sub-pixel R of the third line, green sub-pixels G and blue in the first viewing area Sub-pixel B is filled with Vdata4 respectively, the red sub-pixel R, green sub-pixels G of the third line and the sub- picture of blue in the second viewing area Plain B is filled with Vdata1 respectively.Since the voltage value VGH13 of the significant level of the first clock control signal ck1_n is more than it the Voltage value VGH12 in two horizontal-scanning interval T_2, therefore can have Vdata4>Vdata3.
Since the voltage value of the significant level of the first clock control signal ck1_n controls signal ck2_ no more than second clock The voltage value VGH2 of the significant level of n, therefore can have Vdata4<Vdata1, to by adjusting the first clock control signal The size of the voltage value of the significant level of ck1_n can improve the homogeneity of the brightness of the first viewing area, to make the first display The brightness in area and the brightness of the second viewing area are approximately the same, and then improve and show homogeneity.
In other possible embodiments, when a vertical interval includes continuous multiple data input phases, In different data input phase, the maintenance duration of the significant level of second control signal is different.For example, can be at continuous two In data input phase, so that next data input phase is compared a upper data input phase, make same first clock control The maintenance duration of the significant level of signal increaseds or decreases, to improve the brightness homogeneity of the first viewing area.
Below in continuous data input phase, next data input phase compares a upper data input phase, It is illustrated for the maintenance duration increase of the significant level of each first clock control signal.
Specifically, as shown in Figure 10, the first clock control signal ck1_n's in first horizontal-scanning interval T_1 has The significant level of the maintenance duration t11 of effect level, the first clock control signal ck1_n in second horizontal-scanning interval T_2 The significant level for maintaining the first clock control signal ck1_n in duration t12, third a horizontal-scanning interval T_3 maintenance Duration t13 is successively increased.By bright on the first multi-channel gating device direction of hollow-out parts direction in this way in detecting the first viewing area When degree is sequentially reduced, by making next data input phase compare a upper data input phase, the number on the first data line It is believed that number voltage successively increase, so as to so that be filled in the first viewing area by hollow-out parts be directed toward the first multi-channel gating device direction On the pixel voltage of sub-pixel successively increase, and then the brightness of the first viewing area can be compensated, improve the aobvious of the first viewing area Show homogeneity.
In the specific implementation, in embodiments of the present invention, as shown in figure 5, first control signal end V1 may include：With it is each Switch unit 230_n one-to-one first sub-control signals end V1_n.Switch unit 230_n may include：Second transistor M2；Wherein, the grid of second transistor M2 is connected with second control signal end V2, the first pole of second transistor M2 with it is corresponding First sub-control signal end V1_n connections, the second pole of second transistor M2 are connected with corresponding first clock control line CK1_n. Specifically, second transistor M2 can be N-type transistor, then the significant level of second control signal could be provided as high level. Alternatively, second transistor may be P-type transistor, then the significant level of second control signal could be provided as low level.
In driving method provided in an embodiment of the present invention, second control signal is loaded to first control signal end, specifically May include：
To the end V1_n loads of each first sub-control signal the signal sequence of signal identical first is controlled with each second clock Sub-control signal v1_n；Wherein, when the signal of a first sub-control signal v1_n and a second clock control signal ck2_n Ordered pair is answered.Specifically, as shown in Figure 10, the signal sequence of the first sub-control signal v1_1 and second clock control signal ck2_1 Corresponding, the first sub-control signal v2_2 is corresponding with the signal sequence of second clock control signal ck2_2, the first sub-control signal V2_3 is corresponding with the signal sequence of second clock control signal ck2_3.
In the specific implementation, when a vertical interval includes continuous multiple data input phases, as shown in Figure 10, often In one data input phase, appearance order and all second clocks of the significant level of second control signal v2 control having for signal The appearance order for imitating level corresponds；Also, in continuous data input phase, next data input phase is compared to upper The maintenance duration of one data input phase, the significant level of second control signal v2 increases, and can make each first clock in this way The maintenance duration for controlling the significant level of signal increases.
Further, in continuous data input phase, when can make the maintenance of the significant level of second control signal The numerical value such as long increase.It can make the brightness in the first viewing area that can further increase display homogeneity with even variation in this way.
It is possible to further keep each first sub-control signal identical as corresponding second clock control signal respectively.Into one Step ground, as shown in figure 5, load signal identical first sub-control signal end V1_n and the first clock control signal line can be made CK1_n is electrically connected.Signal end and cabling can be saved in this way, reduce the occupied space of non-display area.
With reference to Fig. 5 and Figure 10, for grid line G_1~G_3 load grid open signals g_1~g_3, to this hair The driving method that bright embodiment provides illustrates.
In first horizontal-scanning interval T_1, to grid line G_1 load grid open signals g_1 so that each son of the first row Thin film transistor (TFT) in pixel is both turned on.When grid line G_1 loads grid open signal g_1, to each first source electrode input line S1_ I and each second source electrode input line S2_j distinguishes on-load voltage Vdata1, and is loaded respectively to the first sub-control signal end V1_n First control signal v1_n loads second control signal v2 to second control signal end V2, and to second clock control line CK2_n loads second clock and controls signal ck2_n, only when second clock control signal ck2_1 is high level, when controlling second 4th transistor M4 conductings of clock control line CK2_1 connections, the 4th transistor M4 of conducting will load on the second source electrode input line Data-signal on S2_j, the pixel electrode being supplied in the first row red sub-pixel R in the second viewing area, so that the red Sub-pixel R is filled with voltage Vdata1.The control second transistor M2 conductings when second control signal v is high level, by first Sub-control signal v1_n is supplied to the first clock control line CK1_n, and the first clock control line CK1_n is made to load the first clock control Signal ck1_n.First clock control signal ck1_1 controls are led with the first clock control line CK1_1 third transistor M3 connecting It is logical, the data-signal on the first source electrode input line S1_i will be loaded on, the red son of the first row in the first viewing area is supplied to Pixel electrode in pixel R, so that red sub-pixel R is filled with voltage Vdata2.
Similarly, so that the pixel electrode in the first row green sub-pixels G in the second viewing area is filled with voltage Vdata1, make The pixel electrode in the first row green sub-pixels G in one viewing area is filled with voltage Vdata2.And make in the second viewing area Pixel electrode in the first row blue subpixels B is filled with voltage Vdata1, makes the first row blue subpixels B in the first viewing area In pixel electrode be filled with voltage Vdata2.Since the maintenance duration t11 of the significant level of the first clock control signal ck1_n is small In the maintenance duration t12 of the significant level of second clock control signal ck2_n, therefore there can be Vdata2<Vdata1.
Similarly, in second horizontal-scanning interval T_2, to grid line G_2 load grid open signals g_2 so that second Thin film transistor (TFT) in each sub-pixel of row is both turned on, so that the red sub-pixel R of the second row, the sub- picture of green in the first viewing area Plain G and blue subpixels B is filled with Vdata2 respectively, red sub-pixel R, the green sub-pixels G of the second row in the second viewing area And blue subpixels B is filled with Vdata3 respectively.Due to the maintenance duration of the significant level of the first clock control signal ck1_n T12 is more than its maintenance duration t11 in first horizontal-scanning interval T_1, therefore can have Vdata3>Vdata2.And In a third horizontal-scanning interval T_3, to grid line G_3 load grid open signals g_3 so that in each sub-pixel of the third line Thin film transistor (TFT) is both turned on, so that the red sub-pixel R of the third line, green sub-pixels G and blue in the first viewing area Pixel B is filled with Vdata2 respectively, the red sub-pixel R, green sub-pixels G and blue subpixels of the third line in the second viewing area B is filled with Vdata4 respectively.Since the maintenance duration t13 of the significant level of the first clock control signal ck1_n is more than it second Maintenance duration t12 in a horizontal-scanning interval T_2, therefore can have Vdata4>Vdata3.
Since the maintenance duration of the significant level of the first clock control signal ck1_n controls signal no more than second clock The maintenance duration of the significant level of ck2_n, therefore can have Vdata4<Vdata1, to believe by adjusting the first clock control The size of the maintenance duration of the significant level of number ck1_n, can improve the homogeneity of the brightness of the first viewing area, to make first The brightness of viewing area and the brightness of the second viewing area are approximately the same, and then improve and show homogeneity.
Further, in the specific implementation, in embodiments of the present invention, as shown in Figure 10 and Figure 11, can make continuous Data input phase in, next data input phase compare a upper data input phase, second control signal v2's has The maintenance duration for imitating level increases, and the maintenance duration of the significant level of each first clock control signal ck1_n is made to increase.And also Can make in continuous data input phase, next data input phase compare a upper data input phase, each first The voltage value of the significant level of sub-control signal v1_n increases.It is defeated compared to a upper data in next data input phase in this way Enter the stage, not only the opening time of third transistor can be made to successively increase, can also make the opening degree of third transistor according to Secondary increase further increases display homogeneity.At this point, the first sub-control signal end V1_n not with second clock control line CK2_n Electrical connection.
It is possible to further make the voltage value of the significant level of the first clock control signal believe no more than second clock control Number significant level voltage value.The brightness of the first viewing area can be made integrally to reduce in this way, so as to so that the first viewing area Brightness with the second viewing area tends to be uniform.
Based on same inventive concept, the embodiment of the present invention provides a kind of display panel, and use is provided in an embodiment of the present invention The driving method of above-mentioned display panel is driven.
In the specific implementation, in embodiments of the present invention, the principle solved the problems, such as due to display panel and aforementioned display surface The driving method of plate is similar, therefore the implementation of the display panel may refer to the implementation of driving method, and overlaps will not be repeated.
Based on same inventive concept, the embodiment of the present invention provides a kind of display device, and as shown in figure 12, including the present invention is real The above-mentioned display panel of example offer is provided.In the specific implementation, the principle which solves the problems, such as and aforementioned display panel phase Seemingly, therefore the implementation of the display device may refer to the implementation of aforementioned display panel, and repeating place, details are not described herein.
In the specific implementation, in embodiments of the present invention, display device provided in an embodiment of the present invention can also include driving Dynamic IC, driving IC for realizing any of the above-described kind of display panel provided in an embodiment of the present invention driving method the step of.
In the specific implementation, in embodiments of the present invention, complete hardware can be used in driving IC provided in an embodiment of the present invention The form of embodiment, complete software embodiment or embodiment combining software and hardware aspects, is not limited thereto.
Generally when driving IC to be designed, Functional Design its output end that can achieve as needed.However in reality In the application of border, the function that driving IC is realized required for different application environment is also different, therefore in order to meet most of application environments Demand, multiple vacant output ends can be pre-set out, for making the function of driving IC increase.In the specific implementation, In embodiments of the present invention, driving IC may include multiple vacant output ends, first control signal end and second control signal end One vacant output end of electrical connection is corresponded respectively.First control signal and second control signal can be made by driving core in this way Vacant output end in piece provides, so as to using the vacant output end output signal reserved in IC is driven, reduce technique system Standby difficulty.It, can be according to the vacant output end of driving IC in this way when a vertical interval includes multiple data input phases Number is configured.For example, when the number of vacant output end is 24, a vertical interval may include 24 data inputs Stage.Based on same inventive concept, the embodiment of the present invention also provides a kind of display device, including it is provided in an embodiment of the present invention on State display panel and driving device provided in an embodiment of the present invention.
In the specific implementation, display device provided in an embodiment of the present invention can be：Mobile phone, television set, is shown tablet computer Show any product or component with display function such as device, laptop, Digital Frame, navigator.For the display device Other essential component parts be it will be apparent to an ordinarily skilled person in the art that having, this will not be repeated here, Also it should not be taken as limiting the invention.
Display panel, its driving method and display device provided in an embodiment of the present invention, pass through the first clock control signal The first multi-channel gating device is controlled to realize to the control of the first data line in the first viewing area, signal is controlled by second clock The second multi-channel gating device is controlled to realize the control to the second data line in the second viewing area, and the first clock control signal It is different with second clock control signal, so as to which the charging situation of the first data line and the second data line is separately controlled, so that The voltage for inputting the data-signal of the first data line and the second data line, adjusts accordingly according to actually detected brightness, to The display homogeneity of display panel is set to improve.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to include these modifications and variations.

Claims (18)

1. a kind of driving method of display panel, which is characterized in that the display panel includes having at least one hollow-out parts Array substrate；The array substrate includes：Viewing area and non-display area；The viewing area includes the first viewing area and the second display Area, the hollow-out parts are located at first viewing area, and first viewing area includes a plurality of first data line；Second display Area includes a plurality of second data line；The non-display area includes：Multiple first multi-channel gating devices, multiple second multi-channel gating devices, N The first clock control of item line, N second clock control line and list is switched correspondingly with each first clock control line Member；Wherein, first multi-channel gating device is connect with the first data line described in M items, second multi-channel gating device It is connect with the second data line described in M items；All first multi-channel gating devices are electrically connected with the first clock control of N items line； All second multi-channel gating devices are electrically connected with the N second clock control line；Each first clock control line passes through Corresponding switch unit is connect with first control signal end, and control terminal and the second control signal end of each switch unit connect It connects；N >=M >=3 and be integer；
The driving method includes：
In data input phase in a vertical interval, first control signal is loaded to the first control signal end, to The second control signal end loads second control signal, and controlling each switch unit makes each first clock control line add The first clock control signal is carried, first data line is made to input corresponding data-signal；Simultaneously to each second clock control Line load second clock processed controls signal, and second data line is made to input corresponding data-signal；Wherein, first clock It is different from the second clock control signal of signal to control signal.
2. driving method as described in claim 1, which is characterized in that the electricity of the significant level of first clock control signal Pressure value is less than the voltage value of the significant level of second clock control signal.
3. driving method as described in claim 1, which is characterized in that the dimension of the significant level of first clock control signal Hold maintenance duration of the duration less than the significant level of second clock control signal.
4. driving method as claimed in claim 2 or claim 3, which is characterized in that a vertical interval includes at least one number According to input phase；Wherein, in the same data input phase, the voltage of the significant level of each first clock control signal It is worth identical and maintains duration identical；
In the different data input phases, when the voltage value of the significant level of same first clock control signal and maintenance At least one difference in length.
5. driving method as claimed in claim 4, which is characterized in that the second control signal end includes：It described is opened with each Close unit one-to-one second sub-control signal end；It is described to load second control signal, tool to the second control signal end Body includes：
To each second sub-control signal end load the second son identical with the second clock control signal sequence of signal Control signal；Wherein, second sub-control signal is corresponding with a second clock control signal sequence of signal.
6. driving method as claimed in claim 5, which is characterized in that when the maintenance of the significant level of the first control signal Length is identical and is not less than a horizontal-scanning interval；And the voltage value of the significant level of the first control signal is less than described Second clock controls the voltage value of the significant level of signal.
7. driving method as claimed in claim 6, which is characterized in that include continuous multiple numbers in a vertical interval When according to input phase, in the different data input phases, the voltage value of the significant level of the first control signal is different.
8. driving method as claimed in claim 5, which is characterized in that each second sub-control signal respectively with corresponding institute It is identical to state second clock control signal.
9. driving method as claimed in claim 8, which is characterized in that load signal identical second sub-control signal end and the Two clock control lines are electrically connected.
10. driving method as claimed in claim 5, which is characterized in that the switch unit includes：The first transistor；
The grid of the first transistor and corresponding second sub-control signal end are connected, the first pole of the first transistor with The first control signal end connection, the second pole of the first transistor is connected with the corresponding first clock control line.
11. driving method as claimed in claim 4, which is characterized in that the first control signal end includes：It described is opened with each Close unit one-to-one first sub-control signal end；It is described to load second control signal, tool to the first control signal end Body includes：
To the load of each first sub-control signal end signal sequence of signal identical first is controlled with each second clock Sub-control signal；Wherein, the signal sequence pair of first sub-control signal and a second clock control signal It answers.
12. driving method as claimed in claim 11, which is characterized in that the appearance of the significant level of the second control signal The appearance order of order and the significant level of all second clock control signals corresponds；And the second control letter Number significant level maintain duration be less than the second clock control signal significant level maintenance duration.
13. driving method as claimed in claim 12, which is characterized in that in a vertical interval including continuous multiple When data input phase, in the different data input phases, the maintenance duration of the significant level of the second control signal is not Together.
14. driving method as claimed in claim 11, which is characterized in that each first sub-control signal respectively with it is corresponding The second clock control signal is identical.
15. driving method as claimed in claim 14, which is characterized in that load signal identical first sub-control signal end with Second clock control line is electrically connected.
16. driving method as claimed in claim 11, which is characterized in that the switch unit includes：Second transistor；
The grid of the second transistor is connected with the second control signal end, the first pole of the second transistor with it is corresponding The connection of first sub-control signal end, the second pole of the second transistor and the corresponding first clock control line phase Even.
17. a kind of display panel, which is characterized in that driven using such as claim 1-16 any one of them driving methods.
18. a kind of display device, which is characterized in that including display panel as claimed in claim 17.
CN201811003751.3A 2018-08-30 2018-08-30 Display panel, driving method thereof and display device Active CN108806586B (en)

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