CN104992681A - Display panel and pixel circuit for display panel - Google Patents
Display panel and pixel circuit for display panel Download PDFInfo
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- CN104992681A CN104992681A CN201510386890.9A CN201510386890A CN104992681A CN 104992681 A CN104992681 A CN 104992681A CN 201510386890 A CN201510386890 A CN 201510386890A CN 104992681 A CN104992681 A CN 104992681A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
Abstract
The invention relates to a pixel circuit for a display panel. The pixel circuit includes a plurality of pixel units; each pixel unit at least comprises a first color sub-pixel unit and a second color sub-pixel unit; the first color sub-pixel unit includes a first liquid crystal capacitor and a first storage capacitor; the second color sub-pixel unit comprises a second liquid crystal capacitor and a second storage capacitor; the capacitance value of the first liquid crystal capacitor of the first color sub-pixel unit is not equal to the capacitance value of the second liquid crystal capacitor of the second color sub-pixel unit, or the capacitance value of the first storage capacitor of the first color sub-pixel unit is not equal to the capacitance value of the second storage capacitor of the second color sub-pixel unit.
Description
Technical field
The present invention relates to display panel field, particularly relate to a kind of display panel with special pixel circuit.
Background technology
Please refer to Fig. 1, it shows the schematic diagram of display panel 100 in a kind of prior art.Described display panel 100 comprises some sweep traces (gate line) 102s and some data lines (data line) 102d, some sweep trace 102s and some data line 102d and intermeshes to form multiple pixel cell 104.Each pixel cell 104 comprises three sub-pixel unit 106 (red sub-pixel unit R, green sub-pixels unit G, blue subpixels unit B), and each sub-pixel unit 106 is provided with a thin film transistor (TFT) 110 and connects the pixel electrode 108 of described thin film transistor (TFT) 110.
As shown in Figure 1, each sub-pixel unit 106 is controlled by an a sweep trace 102s and data line 102d, that is, when the resolution of described display panel 100 is MxN, described display panel 100 must be provided with the sweep trace 102s of M bar and the data line 102d of 3N bar.But, for undersized display panel, in order to promote the resolution of display panel, the design be connected with data driver by multiple demodulation multiplexer (demux) can be adopted, to increase the quantity of pixel cell in a limited space.
Please refer to Fig. 2, it shows the schematic diagram of the display panel 200 in a kind of prior art with demultiplexer unit 230.Described display panel 200 comprises data driver 210, gate pole driver 220, demultiplexer unit 230 and image element circuit 240.Described demultiplexer unit 230 has multiple demodulation multiplexer 232, and described data driver 210 is by many main data line (Dn, Dn+1 ...) 212 drive singal is passed to each demodulation multiplexer 232 respectively.Described demodulation multiplexer 232 comprises the first interrupteur SW 1, second switch SW2 and the 3rd interrupteur SW 3, for responding the first control signal Remux (R), the second control signal Remux (G) and the 3rd control signal Remux (B) that input from its outside respectively, and apply the described drive singal from corresponding main data line 212 reception to three secondary data lines (S1, S2, S3) 234 in order.
As shown in Figure 2, described image element circuit 240 comprises sweep trace (Gn, Gn+1 that described many secondary data lines 234 are connected with many and described gate pole driver 220 ...) 222.Described many secondary data lines 234 and described multi-strip scanning line 222 intermesh to define multiple pixel cell 242, and pixel cell 242 described in each comprises the red sub-pixel unit R of sequential, green sub-pixels unit G and blue subpixels unit B.Described drive singal is passed to described red sub-pixel unit R, described green sub-pixels unit G and described blue subpixels unit B respectively by described secondary data line S1, secondary data line S2 and secondary data line S3.
As shown in Figure 2, described red sub-pixel unit R comprises the first liquid crystal capacitance C (R) 1 and the first memory capacitance C (R) 2, described green sub-pixels unit G comprises the second liquid crystal capacitance C (G) 1 and the second memory capacitance C (G) 2 and described blue subpixels unit B comprises the 3rd liquid crystal capacitance C (B) 1 and the 3rd memory capacitance C (B) 2.In the prior art, the described first liquid crystal capacitance C (R) 1 of described red sub-pixel unit R is equal to the described second liquid crystal capacitance C (G) 1 of described green sub-pixels unit G and is equal to the described 3rd liquid crystal capacitance C (B) 1 of described blue subpixels unit B.Similarly, the described first memory capacitance C (R) 2 of described green sub-pixels unit G is equal to the described second memory capacitance C (G) 2 of described green sub-pixels unit G and is equal to the described 3rd memory capacitance C (B) 2 of described blue subpixels unit B.
Please refer to Fig. 3, the drive waveforms figure of the display panel 200 of its display shown in Fig. 2.When use some reversion a type of drive drive described display panel 200 or at heavily loaded pattern, described first interrupteur SW 1 of described demodulation multiplexer 232, described second switch SW2 and described 3rd interrupteur SW 3 are driven in order by described first control signal Remux (R), described second control signal Remux (G) and described 3rd control signal Remux (B), and are applied through the described drive singal of described main data line 212 input to the described secondary data line 234 of correspondence.As shown in Figure 3, in described display panel 200, the described red sub-pixel unit R of described image element circuit 240 can first be charged.But, due to the impact of capacitance-resistance hysteresis phenomenon (RC delay), make the charging effect of described red sub-pixel unit R be not so good as the charging effect of described green sub-pixels unit G and described blue subpixels unit B.Therefore, when described display panel 200 display frame, pure white picture can present inclined cyan originally.
In view of this, be necessary to propose a kind of display panel, its to improve due to some color sub-pixels unit between charge differential and cause the picture of display panel to present the phenomenon of colour cast and uneven color.
Summary of the invention
For solving the problem of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of display panel and the image element circuit for display panel, by the capacitance of the liquid crystal capacitance capacitance of the liquid crystal capacitance in a color sub-pixels unit specific in the image element circuit of described display panel or memory capacitance being set to be different from other color sub-pixels unit or memory capacitance, to compensate the electrical of described particular color sub-pixel unit, and then improvement causes the picture of described display panel to present the phenomenon of colour cast and uneven color due to the charge differential between some color sub-pixels unit.
To achieve these goals, the invention provides a kind of image element circuit for display panel, described image element circuit comprises: multi-strip scanning line, many secondary data lines, with the interlaced configuration of described multi-strip scanning line, and multiple pixel cell, described in each, pixel cell at least comprises: one first color sub-pixels unit and one second color sub-pixels unit, described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and be electrically connected to respectively in described many secondary data lines continuously arranged one first time data line and one second time data line, described first color sub-pixels unit comprises one first liquid crystal capacitance and one first memory capacitance, and described second color sub-pixels unit comprises one second liquid crystal capacitance and one second memory capacitance, the capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described second liquid crystal capacitance of described second color sub-pixels unit is unequal, or the capacitance of described second memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described second color sub-pixels unit is unequal.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit equals the capacitance of described second memory capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described second memory capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit equals the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the driver' s timing of described first color sub-pixels unit is early than the driver' s timing of described second color sub-pixels unit.
In the preferred embodiment of the present invention, pixel cell described in each of described image element circuit also comprises one the 3rd color sub-pixels unit, described 3rd color sub-pixels unit and described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and described 3rd color sub-pixels unit be also electrically connected to be arranged in after described second time data line one third time data line, described 3rd color sub-pixels unit comprises one the 3rd liquid crystal capacitance and one the 3rd memory capacitance, the capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit is unequal, or the capacitance of described 3rd memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described 3rd color sub-pixels unit is unequal.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit, and the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit equals the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit, and the capacitance of described second memory capacitance of described second color sub-pixels unit equals the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit.
The present invention also provides a kind of display panel, and described display panel comprises: an image element circuit comprises: multi-strip scanning line, many secondary data lines and the interlaced setting of described multi-strip scanning line, and multiple pixel cell, described in each, pixel cell at least comprises: one first color sub-pixels unit and one second color sub-pixels unit, described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and be electrically connected to respectively in described many secondary data lines continuously arranged one first time data line and one second time data line, described first color sub-pixels unit comprises one first liquid crystal capacitance and one first memory capacitance, and described second color sub-pixels unit comprises one second liquid crystal capacitance and one second memory capacitance, one data driver, is connected with many main data line for transmitting multiple data drive signal, one gate pole driver, is connected with described multi-strip scanning line for transmitting multiple gate drive signal, and a demultiplexer unit, comprise multiple demodulation multiplexer, one of them demodulation multiplexer is connected with described data driver by one of them of described many main data line, and for responding the multiple control signals from its outside input respectively, in order to described first time data line and described second time data line apply the described data drive signal that receives from corresponding described main data line, the capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described second liquid crystal capacitance of described second color sub-pixels unit is unequal, or the capacitance of described second memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described second color sub-pixels unit is unequal.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit equals the capacitance of described second memory capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described second memory capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit equals the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
In the preferred embodiment of the present invention, the described multiple control signal of described demodulation multiplexer response by the corresponding described data drive signal described first color sub-pixels unit of input and described second color sub-pixels unit, makes the driver' s timing of described first color sub-pixels unit early than the driver' s timing of described second color sub-pixels unit in order.
In the preferred embodiment of the present invention, pixel cell described in each of described image element circuit also comprises one the 3rd color sub-pixels unit, described 3rd color sub-pixels unit and described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and described 3rd color sub-pixels unit be also electrically connected to be arranged in after described second time data line one third time data line; Described 3rd color sub-pixels unit comprises one the 3rd liquid crystal capacitance and one the 3rd memory capacitance, the capacitance of the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit and described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit is unequal, or the capacitance of described 3rd memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described 3rd color sub-pixels unit is unequal.
In the preferred embodiment of the present invention, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit, and the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit equals the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit.
In the preferred embodiment of the present invention, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit, and the capacitance of described second memory capacitance of described second color sub-pixels unit equals the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit.
Accompanying drawing explanation
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Fig. 1 shows the schematic diagram of display panel in a kind of prior art;
Fig. 2 shows the schematic diagram of the display panel in a kind of prior art with demultiplexer unit;
Fig. 3 shows the drive waveforms figure of the display panel shown in Fig. 2;
Fig. 4 shows a kind of schematic diagram according to display panel of the present invention; And
Fig. 5 shows the schematic diagram of the pixel cell of image element circuit in the display panel shown in Fig. 4.
Embodiment
The preferred embodiments of the present invention coordinate accompanying drawing and explanation to be below described in detail, different graphic in, identical element numbers represents same or analogous assembly.
Please refer to Fig. 4, it shows a kind of schematic diagram according to display panel 300 of the present invention.Described display panel 300 comprises data driver 310, gate pole driver 320, demultiplexer unit 330 and an image element circuit 340.Described data driver 310 and many main data line (Dn, Dn+1 ...) 312 to be connected for multiple data drive signal is passed to described demultiplexer unit 330.Described gate pole driver 320 and multi-strip scanning line (Gn, Gn+1 ...) 322 to be connected for transmitting multiple gate drive signal.Described demultiplexer unit 330 comprises multiple demodulation multiplexer 332, and described data driver 310 is by many main data line (Dn, Dn+1 ...) 312 described data drive signal is passed to each demodulation multiplexer 332 respectively.Described demodulation multiplexer 332 comprises the first interrupteur SW 1, second switch SW2 and the 3rd interrupteur SW 3, for responding the first control signal Remux (R), the second control signal Remux (G) and the 3rd control signal Remux (B) that input from its outside respectively, and apply the described data drive signal from corresponding described main data line 312 reception to three secondary data lines (S1, S2, S3) 334 in order.
As shown in Figure 4, described image element circuit 340 comprises described multi-strip scanning line 322, described many secondary data lines 332 and multiple pixel cell 342, and described multi-strip scanning line 322 and described many secondary data lines 332 intermesh to define described multiple pixel cell 342.Pixel cell 342 described in each comprises red sub-pixel unit R, green sub-pixels unit G, the blue subpixels unit B of sequential.Described red sub-pixel unit R, described green sub-pixels unit G and described blue subpixels unit B are electrically connected to the same scan line 322 in described multi-strip scanning line 322, and be electrically connected to respectively in described many secondary data lines continuously arranged one first time data line, one second time data line and one third time data line, such as continuously arranged secondary data line S1, secondary data line S2 and secondary data line S3.When driving described display panel 300, pixel cell 342 driver' s timing of described image element circuit 340 is: first, drives described red sub-pixel unit R, then, drives described green sub-pixels unit G, finally, drives described blue subpixels unit B.It should be noted that the kind quantity of color sub-pixels unit comprised in the present embodiment is only as signal, be not limited to this.In more detail, in other embodiments, the color sub-pixels unit more than three kinds can be comprised.Moreover owing to comprising three kinds of color sub-pixels unit in the present embodiment, therefore each demodulation multiplexer 332 of described demultiplexer unit 330 applies described data drive signal to three secondary data lines (S1, S2, S3) 334 in order.But in other embodiments, when comprising four kinds of color sub-pixels unit, each demodulation multiplexer applies art data drive signal to four secondary data lines in order, and by that analogy, not in this to go forth.
Please refer to Fig. 5, the schematic diagram of the pixel cell 342 of image element circuit 340 in the display panel 300 of its display shown in Fig. 4.In described display panel 300, the described red sub-pixel unit R of the described pixel cell 342 of described image element circuit 340 comprises the first pixel electrode 3422, first liquid crystal capacitance C (R) 1 and the first memory capacitance C (R) 2, described green sub-pixels unit G and comprises the second pixel electrode 3424, second liquid crystal capacitance C (G) 1 and the second memory capacitance C (G) 2 and described blue subpixels unit B and comprise the 3rd pixel electrode 3426, the 3rd liquid crystal capacitance C (B) 1 and the 3rd memory capacitance C (B) 2.Described first liquid crystal capacitance C (R) 1 and described first memory capacitance C (R) 2 is by described the first film transistor 3422, described second liquid crystal capacitance C (G) 1 and described second memory capacitance C (G) 2 is by described second thin film transistor (TFT) 3424, and described 3rd liquid crystal capacitance C (G) 1 and described 3rd memory capacitance C (G) 2 is electrically connected to the same scan line 322 in described multi-strip scanning line 322 by described 3rd thin film transistor (TFT) 3426, and be electrically connected to continuously arranged first time data line 334 (S1) respectively, second time data line 334 (S2), with third time data line 334 (S3).
In the preferred embodiment of the present invention, in described display panel 300, the capacitance of the described first liquid crystal capacitance C (R) 1 in the described red sub-pixel unit R of the described pixel cell 342 of described image element circuit 340 is greater than the capacitance of the described second liquid crystal capacitance C (G) 1 in described green sub-pixels unit G, and is greater than the capacitance of the described 3rd liquid crystal capacitance C (B) 1 in described blue subpixels unit B.Further, the capacitance of the described second liquid crystal capacitance C (G) 1 in described green sub-pixels unit G equals the capacitance of the described 3rd liquid crystal capacitance C (B) 1 in described blue subpixels unit B.Moreover, the capacitance of the described first memory capacitance C (R) 2 in the described red sub-pixel unit R of the described pixel cell 342 of described image element circuit 340 equals the capacitance of the described second memory capacitance C (G) 2 in described green sub-pixels unit G, and equals the capacitance of the described 3rd memory capacitance C (B) 2 in described blue subpixels unit B.
In above preferred embodiment, capacitance by the described first liquid crystal capacitance C (R) 1 in the described red sub-pixel unit R of the described pixel cell 342 by described image element circuit 340 is set to the capacitance of the some liquid crystal capacitances be greater than in other color sub-pixels unit, to make sequentially to drive described red sub-pixel unit R, described green sub-pixels unit G, during with described blue subpixels unit B, described red sub-pixel unit R, described green sub-pixels unit G, consistent with maintenance (holding) voltage of described blue subpixels unit B, and then the impact improved due to capacitance-resistance hysteresis phenomenon (RC delay), the charging effect of described red sub-pixel unit R is caused to be less than described green sub-pixels unit G and described blue subpixels unit B and to cause the picture of described display panel 300 to present the phenomenon of colour cast and uneven color.
In another preferred embodiment of the present invention, the capacitance of the described first memory capacitance C (R) 2 in the described red sub-pixel unit R of the described pixel cell 342 of described image element circuit 340 is less than the capacitance of the described second memory capacitance C (G) 2 in described green sub-pixels unit G, and is less than the capacitance of the described 3rd memory capacitance C (B) 2 in described blue subpixels unit B.Further, the capacitance of the described second memory capacitance C (G) 2 in described green sub-pixels unit G equals the capacitance of the described 3rd memory capacitance C (B) 2 in described blue subpixels unit B.Moreover, the capacitance of the described first liquid crystal capacitance C (R) 1 in the described red sub-pixel unit R of the described pixel cell 342 of described image element circuit 340 equals the capacitance of the described second liquid crystal capacitance C (G) 1 in described green sub-pixels unit G, and equals the capacitance of the described 3rd liquid crystal capacitance C (B) 1 in described blue subpixels unit B.
In above preferred embodiment, capacitance by the described first memory capacitance C (R) 2 in the described red sub-pixel unit R of the described pixel cell 342 by described image element circuit 340 is set to the capacitance of the some memory capacitance be less than in other color sub-pixels unit, to make sequentially to drive described red sub-pixel unit R, described green sub-pixels unit G, during with described blue subpixels unit B, described red sub-pixel unit R, described green sub-pixels unit G, consistent with maintenance (holding) voltage of described blue subpixels unit B, and then the impact improved due to capacitance-resistance hysteresis phenomenon (RC delay), the charging effect of described red sub-pixel unit R is caused to be less than described green sub-pixels unit G and described blue subpixels unit B and to cause the picture of described display panel 300 to present the phenomenon of colour cast and uneven color.
Although be described Illustrative embodiments of the present invention, but should be appreciated that ground, the present invention is not limited to these Illustrative embodiments, within the spirit and principles in the present invention all, any amendment that those of ordinary skill in the art do, equivalent replacement, improvement etc., all should be included within right of the present invention.In addition, the use of term " ", " " etc. does not represent number quantitative limitation, but represents the reference part that there is at least one.
Claims (18)
1. for an image element circuit for display panel, it is characterized in that, described image element circuit comprises:
Multi-strip scanning line;
Many secondary data lines, with the interlaced configuration of described multi-strip scanning line; And
Multiple pixel cell, described in each, pixel cell at least comprises: one first color sub-pixels unit and one second color sub-pixels unit, described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and be electrically connected to respectively in described many secondary data lines continuously arranged one first time data line and one second time data line, described first color sub-pixels unit comprises one first liquid crystal capacitance and one first memory capacitance, and described second color sub-pixels unit comprises one second liquid crystal capacitance and one second memory capacitance,
The capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described second liquid crystal capacitance of described second color sub-pixels unit is unequal, or the capacitance of described second memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described second color sub-pixels unit is unequal.
2. image element circuit according to claim 1, it is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
3. image element circuit according to claim 2, it is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit equals the capacitance of described second memory capacitance of described second color sub-pixels unit.
4. image element circuit according to claim 1, it is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described second memory capacitance of described second color sub-pixels unit.
5. image element circuit according to claim 4, it is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit equals the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
6. image element circuit according to claim 1, is characterized in that, the driver' s timing of described first color sub-pixels unit is early than the driver' s timing of described second color sub-pixels unit.
7. image element circuit according to claim 1, it is characterized in that, pixel cell described in each of described image element circuit also comprises one the 3rd color sub-pixels unit, described 3rd color sub-pixels unit and described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and described 3rd color sub-pixels unit be also electrically connected to be arranged in after described second time data line one third time data line, described 3rd color sub-pixels unit comprises one the 3rd liquid crystal capacitance and one the 3rd memory capacitance, the capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit is unequal, or the capacitance of described 3rd memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described 3rd color sub-pixels unit is unequal.
8. image element circuit according to claim 7, it is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit, and the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit equals the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit.
9. image element circuit according to claim 7, it is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit, and the capacitance of described second memory capacitance of described second color sub-pixels unit equals the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit.
10. a display panel, is characterized in that, described display panel comprises:
One image element circuit comprises:
Multi-strip scanning line;
Many secondary data lines and the interlaced setting of described multi-strip scanning line; And
Multiple pixel cell, described in each, pixel cell at least comprises: one first color sub-pixels unit and one second color sub-pixels unit, described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and be electrically connected to respectively in described many secondary data lines continuously arranged one first time data line and one second time data line, described first color sub-pixels unit comprises one first liquid crystal capacitance and one first memory capacitance, and described second color sub-pixels unit comprises one second liquid crystal capacitance and one second memory capacitance,
One data driver, is connected with many main data line for transmitting multiple data drive signal;
One gate pole driver, is connected with described multi-strip scanning line for transmitting multiple gate drive signal; And
One demultiplexer unit, comprise multiple demodulation multiplexer, one of them demodulation multiplexer is connected with described data driver by one of them of described many main data line, and for responding the multiple control signals from its outside input respectively, in order to described first time data line and described second time data line apply the described data drive signal that receives from corresponding described main data line;
The capacitance of the capacitance of described first liquid crystal capacitance of wherein said first color sub-pixels unit and described second liquid crystal capacitance of described second color sub-pixels unit is unequal, or the capacitance of described second memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described second color sub-pixels unit is unequal.
11. display panels according to claim 10, it is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
12., according to display panel described in claim 11, is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit equals the capacitance of described second memory capacitance of described second color sub-pixels unit.
13. display panels according to claim 10, it is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described second memory capacitance of described second color sub-pixels unit.
14., according to display panel described in claim 13, is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit equals the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit.
15. display panels according to claim 10, it is characterized in that, the described multiple control signal of described demodulation multiplexer response by the corresponding described data drive signal described first color sub-pixels unit of input and described second color sub-pixels unit, makes the driver' s timing of described first color sub-pixels unit early than the driver' s timing of described second color sub-pixels unit in order.
16. display panels according to claim 10, it is characterized in that, pixel cell described in each of described image element circuit also comprises one the 3rd color sub-pixels unit, described 3rd color sub-pixels unit and described first color sub-pixels unit and described second color sub-pixels unit are electrically connected to the same scan line in described multi-strip scanning line, and described 3rd color sub-pixels unit be also electrically connected to be arranged in after described second time data line one third time data line; Described 3rd color sub-pixels unit comprises one the 3rd liquid crystal capacitance and one the 3rd memory capacitance, the capacitance of the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit and described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit is unequal, or the capacitance of described 3rd memory capacitance of the capacitance of described first memory capacitance of described first color sub-pixels unit and described 3rd color sub-pixels unit is unequal.
17. according to display panel described in claim 16, it is characterized in that, the capacitance of described first liquid crystal capacitance of described first color sub-pixels unit is greater than the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit, and the capacitance of described second liquid crystal capacitance of described second color sub-pixels unit equals the capacitance of described 3rd liquid crystal capacitance of described 3rd color sub-pixels unit.
18. according to display panel described in claim 16, it is characterized in that, the capacitance of described first memory capacitance of described first color sub-pixels unit is less than the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit, and the capacitance of described second memory capacitance of described second color sub-pixels unit equals the capacitance of described 3rd memory capacitance of described 3rd color sub-pixels unit.
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| CN201510386890.9A CN104992681B (en) | 2015-07-03 | 2015-07-03 | Display panel and the image element circuit for display panel |
| PCT/CN2015/085342 WO2017004856A1 (en) | 2015-07-03 | 2015-07-28 | Display panel, and pixel circuit for display panel |
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| CN201510386890.9A CN104992681B (en) | 2015-07-03 | 2015-07-03 | Display panel and the image element circuit for display panel |
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| Publication number | Publication date |
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| CN104992681B (en) | 2018-03-02 |
| WO2017004856A1 (en) | 2017-01-12 |
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