CN110070832B

CN110070832B - Display panel, signal reading method thereof and display device

Info

Publication number: CN110070832B
Application number: CN201910530072.XA
Authority: CN
Inventors: 殷新社
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-06-19
Filing date: 2019-06-19
Publication date: 2021-01-22
Anticipated expiration: 2039-06-19
Also published as: WO2020253376A1; CN110070832A

Abstract

A display panel, a signal reading method thereof and a display device are provided. The display panel includes: the pixel array comprises a first pixel unit group, a second pixel unit group, a first N-selected one selection circuit, a second N-selected one selection circuit, a first sensing line group and a second sensing line group which are adjacent to each other. The pixel unit group comprises N pixel circuits which are sequentially adjacent, the sensing line group comprises N sensing lines which are sequentially adjacent, and sensing signal output ends of the N pixel circuits are respectively and electrically connected with the N sensing lines; the N-out-of-one selection circuit comprises a control end, a signal output end and N signal input ends, wherein the control end is used for receiving a selection signal so as to sequentially select one of the N signal input ends to be connected with the signal output end; the N signal input ends are respectively and electrically connected with the N sensing lines; the total number of partial sensing lines arranged between the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected first is greater than or equal to 1.

Description

Display panel, signal reading method thereof and display device

Technical Field

The embodiment of the disclosure relates to a display panel, a signal reading method thereof and a display device.

Background

Organic Light Emitting Diode (OLED) display panels are receiving much attention due to advantages of wide viewing angle, high contrast, fast response speed, higher Light Emitting brightness, lower driving voltage, and the like compared to inorganic Light Emitting display devices. Due to the characteristics, the Organic Light Emitting Diode (OLED) display panel can be suitable for devices with display functions, such as mobile phones, displays, notebook computers, digital cameras, instruments and meters and the like.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display panel including: the pixel array comprises a first pixel unit group, a second pixel unit group, a first N-selected one selection circuit, a second N-selected one selection circuit, a first sensing line group and a second sensing line group. The first pixel unit group and the second pixel unit group are adjacently arranged; the first pixel unit group comprises N sequentially adjacent first pixel circuits, the first sensing line group comprises N sequentially adjacent first sensing lines, and sensing signal output ends of the N first pixel circuits are electrically connected with the N first sensing lines respectively; the second pixel unit group comprises N sequentially adjacent second pixel circuits, the second sensing line group comprises N sequentially adjacent second sensing lines, and sensing signal output ends of the N second pixel circuits are electrically connected with the N second sensing lines respectively; the first N-out-of-one selection circuit comprises a first control end, a first signal output end and N first signal input ends, wherein the first control end is used for receiving a selection signal so as to sequentially select one of the N first signal input ends to be connected with the first signal output end; the second N-out-of-one selection circuit comprises a second control end, a second signal output end and N second signal input ends, wherein the second control end is used for receiving the selection signal so as to sequentially select one of the N second signal input ends to be connected with the second signal output end; the N first signal input ends are electrically connected with the N first sensing lines respectively, and the N second signal input ends are electrically connected with the N second sensing lines respectively; and a total number of a part of the first sensing lines and a part of the second sensing lines, which are arranged between the first sensing lines connected with the first signal input end selected last and the second sensing lines connected with the second signal input end selected first, is greater than or equal to 1, and N is an integer greater than or equal to 2.

At least one embodiment of the present disclosure also provides a display device including the display panel provided in any one of the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a signal reading method for a display panel provided in any one of the embodiments of the present disclosure, including: one of the N first signal input ends is sequentially selected to be connected with the first signal output end through the first N-out-of-one selection circuit; and one of the N second signal input ends is sequentially selected to be connected with the second signal output end through the second N-out-of-one selection circuit.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic diagram of a pixel circuit;

FIG. 1B is a schematic diagram of another pixel circuit;

FIG. 1C is a schematic diagram of yet another pixel circuit;

FIG. 1D is a graph of sense voltage versus time;

FIG. 2A is a schematic diagram of a display panel;

FIG. 2B is a graph of the voltage at the source of the drive transistor of the display panel shown in FIG. 2A over time;

fig. 3A is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure;

fig. 3B is one example of a first pixel circuit and a second pixel circuit provided by at least one embodiment of the present disclosure;

fig. 3C is a schematic diagram of a first one of N select circuit provided by at least one embodiment of the present disclosure;

fig. 3D is a schematic diagram of a second one-of-N selection circuit provided in at least one embodiment of the present disclosure;

FIG. 4A is a schematic diagram of one example of the display panel shown in FIG. 3A;

FIG. 4B shows a schematic diagram of the first one of N select circuits shown in FIG. 4A;

FIG. 4C shows a schematic diagram of a second one of N select circuits shown in FIG. 4B;

fig. 4D illustrates a schematic diagram of another first one of N selection circuit provided by at least one embodiment of the present disclosure;

fig. 5 is a schematic flow chart of a signal reading method of a display panel provided by at least one embodiment of the present disclosure;

fig. 6 is an exemplary block diagram of a display panel provided by at least one embodiment of the present disclosure; and

figure 7 is a schematic view of the display panel shown in figure 6,

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The pixel circuits in an Organic Light Emitting Diode (OLED) display panel generally adopt a matrix driving method. The OLED display panel may be classified into an Active Matrix (Active Matrix) driving type and a Passive Matrix (Passive Matrix) driving type according to whether a switching device is introduced into each pixel unit. The pixel circuit of each pixel unit of the AMOLED (i.e., active matrix driven OLED) display panel includes a thin film transistor and a storage capacitor, and the intensity of a current for driving the OLED to emit light can be controlled by controlling the thin film transistor and the storage capacitor, so that the OLED emits light as needed.

The basic pixel circuit used in the AMOLED display panel is generally a 2T1C pixel circuit, i.e., a pixel circuit that drives an OLED to emit light using two Thin-film transistors (TFTs) and one storage capacitor Cst. Fig. 1A and 1B show schematic diagrams of two 2T1C pixel circuits.

As shown in fig. 1A, a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cst. For example, the gate of the switching transistor T0 is connected to a Scan line (not shown) to receive a Scan signal Scan 1; for example, the source of the switching transistor T0 is connected to a data line (not shown) to receive a data signal Vdata; the drain of the switching transistor T0 is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to the first voltage terminal to receive the first voltage Vdd, and the drain of the driving transistor N0 is connected to the positive terminal of the OLED; one end of the storage capacitor Cst is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and a first voltage terminal; the cathode terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss. For example, the voltage value of the first voltage Vdd is greater than the voltage value of the second voltage Vss. The 2T1C pixel circuit uses two TFTs and a storage capacitor Cst to control gray scales of a pixel unit including the pixel circuit. When the Scan signal Scan1 turns on the switching transistor T0 (applied via the Scan line), the data signal Vdata (provided by the data driving circuit) fed via the data line charges the storage capacitor Cst via the switching transistor T0, so that the data signal Vdata can be stored in the storage capacitor Cst, and the data signal Vdata stored in the storage capacitor Cst can control the conduction degree of the driving transistor N0, so that the intensity of the driving current (for driving the OLED to emit light) generated by the driving transistor N0 can be controlled, and the intensity of the current determines the gray scale of the pixel unit including the pixel circuit. In the 2T1C pixel circuit shown in fig. 1A, the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.

As shown in fig. 1B, another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0 and a storage capacitor Cst, but the connection of the pixel circuit shown in fig. 1B is slightly changed compared to the pixel circuit shown in fig. 1A, and the driving transistor N0 is an N-type transistor. The variations of the pixel circuit of FIG. 1B relative to the pixel circuit shown in FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), while the negative terminal is connected to the drain of the driving transistor N0, and the source of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, e.g., ground voltage). The storage capacitor Cst has one end connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end connected to the source of the driving transistor N0 and a second voltage terminal. The 2T1C pixel circuit shown in fig. 1B operates in substantially the same manner as the pixel circuit shown in fig. 1A and is not described here again.

In addition, for the pixel circuits shown in fig. 1A and 1B, the switching transistor T0 is not limited to an N-type transistor, but may also be a P-type transistor, and is not described herein again.

The OLED display panel generally includes a plurality of pixel units arranged in an array, and each pixel unit may include, for example, the pixel circuit described above. The inventors of the present disclosure have noticed in their studies that, in an OLED display panel, there may be a difference in threshold voltages of driving transistors in respective pixel circuits due to a manufacturing process; also, due to, for example, an influence of temperature variation, the threshold voltage of the driving transistor may be shifted, so that in a case where a plurality of pixel circuits of the OLED display panel receive the same data signal, the intensities of driving currents generated by the driving transistors of the plurality of pixel circuits may be different from each other, and thus the intensity of light emitted from the light emitting element driven by the plurality of pixel circuits and the gray scales of the plurality of pixel units may be different from each other, thereby reducing luminance uniformity and/or display quality of the OLED display panel. In summary, the threshold voltage needs to be compensated (e.g., compensated in real time) to ensure the display effect of the OLED display panel.

The inventor of the present disclosure has noticed in research that although the internal compensation technology can be used to perform threshold compensation on each pixel circuit of the OLED display panel, the pixel circuit using the internal compensation technology is not suitable for a display panel having a smaller pixel unit size due to its complicated structure (having more transistors and control lines) and larger size, thereby being disadvantageous to the improvement of the resolution of the display panel.

The inventors of the present disclosure also noted in their research that external compensation techniques may also be employed to perform threshold compensation for the individual pixel circuits of the OLED display panel, as exemplified below in connection with fig. 1C.

For example, fig. 1C shows a pixel circuit (i.e., a 3T1C circuit) that can detect the threshold voltage of a drive transistor, the drive transistor N0 being an N-type transistor. For example, as shown in fig. 1C, in order to implement the compensation function, the sensing transistor S0 may be introduced on the basis of a 2T1C circuit, that is, a first terminal of the sensing transistor S0 may be connected to the source of the driving transistor N0, and a second terminal of the sensing transistor S0 is connected to the detection circuit (not shown in fig. 1C) via a sensing line SENL.

For example, a set voltage (i.e., a reset signal) Vref may be applied to the source of the driving transistor N0 during the reset phase, and a data signal (e.g., a data voltage) Vdata, where Vdata > Vref + Vth, Vth representing the threshold voltage of the driving transistor, may be applied to the gate of the driving transistor N0 via the switching transistor T0 at the start time of the threshold establishing phase, whereby the data signal Vdata may cause the driving transistor N0 to turn on. When the driving transistor N0 is turned on, the detection circuit is discharged via the sensing transistor S0 or the capacitance provided on the sensing line or the parasitic capacitance Csc is charged via the sensing transistor S0, so that the source voltage Vs of the driving transistor N0 changes. When the source voltage Vs of the driving transistor N0 is equal to the difference between the gate voltage Vg of the driving transistor N0 and the threshold voltage Vth of the driving transistor, the driving transistor N0 will be turned off, and the source voltage Vs of the driving transistor N0 will not change. For example, after the driving transistor N0 is turned off, the turned-off source voltage (i.e., the source voltage Vb after the driving transistor N0 is turned off) may be obtained from the source of the driving transistor N0 via the turned-on sensing transistor S0. After acquiring the off-source voltage Vb, the threshold voltage of the driving transistor (that is, Vth — Vb) can be acquired. Thereby, it is possible to compensate a data signal (data voltage) to be displayed of the pixel circuit based on the threshold voltage of the driving transistor in each pixel circuit and to drive the pixel circuit using the compensated data signal, whereby a compensation function for the threshold voltage of each sub-pixel of the display panel can be realized. For example, the compensated Vdata _ C may be represented using the following expression: vdata _ C is Vdata + Vth.

The inventors of the present disclosure have also noted in their research that the time required for threshold detection is long in order to obtain accurate thresholds of the respective pixel circuits of the OLED display panel. The influence of the threshold detection time on the accuracy of threshold detection of the pixel circuit is exemplarily described below with reference to fig. 1D.

FIG. 1D shows a graph of the source voltage taken from the source of the drive transistor N0 via the conducting sense transistor S0 as a function of time. During the detection, the switching transistor T0 is kept turned on, and thus the gate voltage Vg of the driving transistor N0 is kept at the data signal (data voltage) Vdata. The inventors of the present disclosure have noticed that in the process of discharging the detection circuit via the sensing line or charging the capacitance or parasitic capacitance provided on the sensing line after the data signal Vdata is applied, the charging speed will correspondingly decrease (i.e., the speed at which the sensing voltage increases decreases) as the charging time of the storage capacitor Cst or the like increases (see fig. 1D), because the charging current will decrease as the source voltage (i.e., the source voltage Vs of the driving transistor N0) increases. Specifically, the current Ids output when the driving transistor N0 is in the saturation state can be calculated as follows:

Ids＝K(Vg-Vs-Vth)²

＝K(Vdata-Vs-Vth)²

＝K((Vdata-Vth)-Vs)²。

here, K is 1/2 × W/L × C × μ, W is the width of the channel of the driving transistor N0, L is the length of the channel of the driving transistor N0, W/L is the width-to-length ratio (i.e., the ratio of the width to the length) of the channel of the driving transistor N0, μ is the electron mobility, and C is the capacitance per unit area.

In the process that the voltage Vs of the source of the driving transistor N0 increases to Vdata-Vth, the value of [ (Vdata-Vth) -Vs ] will continuously decrease as Vs increases; accordingly, the current Ids and the charging speed outputted by the driving transistor N0 are reduced, and therefore, the time Ts from the start of charging to the turn-off of the driving transistor N0 is longer.

The inventors of the present disclosure have further noticed that, in a period of time before the driving transistor N0 is turned off, the amount of change in the voltage Vs at the source of the driving transistor N0 is small, and therefore, the threshold voltage of the driving transistor N0 (that is, Vth — Vdata-Vbp) may also be obtained based on the voltage Vbp obtained from the source of the driving transistor N0 before the driving transistor N0 is turned off, and the threshold voltage of the driving transistor N0 obtained at this time is more accurate; the time for threshold detection may thereby be reduced, and in some examples, detection of the threshold voltage of the drive transistor N0 may also be achieved during power-up (e.g., between adjacent display periods during display).

Fig. 2A is a schematic diagram of a display panel 500, and fig. 2B is a graph of a voltage of a source of a driving transistor of the display panel 500 shown in fig. 2A with time. The inventors of the present disclosure have further noticed in their studies that the accuracy of the threshold voltage of the driving transistor N0 obtained by sensing can be improved with the display panel 500 shown in fig. 2A. The following is an exemplary description with reference to fig. 2A and 2B.

As shown in fig. 2A, the display panel 500 includes a plurality of pixel cell groups 510 arranged in parallel, a plurality of N-select-one selection circuits 530 arranged in parallel, a plurality of sensing line groups 520 arranged in parallel, and a plurality of signal conversion circuits 550 arranged in parallel. For example, a plurality of pixel cell groups 510, a plurality of one-out-of-N selection circuits 530, a plurality of sensing line groups 520, and a plurality of signal conversion circuits 550 are respectively arranged in parallel in the first direction D1. For example, the numbers of the plurality of pixel cell groups 510, the plurality of one-out-of-N selection circuits 530, the plurality of sensing line groups 520, and the plurality of signal conversion circuits 550 are equal to each other (e.g., equal to M).

For example, a plurality of pixel cell groups 510 are located in the display area 501 of the display panel 500, a plurality of N-select selection circuits 530 and a plurality of signal conversion circuits 550 are located in the peripheral area of the display panel 500, and a plurality of sensing line groups 520 respectively extend from the display area 501 of the display panel 500 to the peripheral area of the display panel 500; the peripheral region of the display panel 500 is disposed around the display region 501 of the display panel 500, and the plurality of N-select selection circuits 530 and the plurality of signal conversion circuits 550 are located, for example, on one side (e.g., a lower side) of the display region 501 of the display panel 500.

For example, as shown in fig. 2A, each pixel cell group 510 includes a plurality of pixel circuits 511 arranged in an array. For example, each pixel cell group 510 includes N columns of pixel circuits 511 that are sequentially adjacent (sequentially adjacent in the first direction D1). For example, each sensing line group 520 includes N sensing lines 521 adjacent to each other in sequence, and the sensing signal output terminals of the N columns of pixel circuits 511 are respectively connected to the N sensing lines 521.

For example, as shown in fig. 2A, each one-out-of-N selection circuit 530 includes N sequentially adjacent selection transistors (T _1, T _2, … … T _ N-1, and T _ N) that are sequentially arranged in the first direction D1; the N selection transistors are also sequentially arranged in a second direction D2 intersecting the first direction D1, the first direction D1 being, for example, perpendicular to the second direction D2.

For example, as shown in fig. 2A, the input terminals of N selection transistors are configured as N signal input terminals of an N-out-of-one selection circuit 530, and are respectively connected to the corresponding N sensing lines 521; the output ends of the N selection transistors are all connected with the signal output end of the one-of-N selection circuit 530, and the signal output end of the one-of-N selection circuit 530 is connected with a corresponding one of the signal conversion circuits 550; the control terminals of the N selection transistors are configured to receive the N selection sub-signals to sequentially turn on the N selection transistors and to sequentially select one of the N signal input terminals of the N-select one selection circuit 530 to be connected with the signal output terminal of the N-select one selection circuit 530.

For example, the control terminals of the transistors located at the same position in the plurality of N one-out-of-one selection circuits 530 are connected to the same selection control line 151, whereby the wiring of the display panel 500 can be simplified. It should be noted that the transistors located at the same position in the N-out-of-one selection circuits 530 refer to the transistors in the N-out-of-one selection circuits 530 having the same sequence (sequence in the first direction D1), and the positions of the transistors with respect to the N-out-of-one selection circuits 530 are not required to be exactly the same; for example, the transistors in the N-select-one selection circuit 530 that are ordered as X are transistors with the same position, where X is an integer greater than or equal to 1 and less than or equal to N.

For example, each signal conversion circuit 550 is configured to convert an analog signal it receives into a digital signal; for example, each signal conversion circuit 550 may be implemented as an analog-to-digital conversion circuit.

For example, when each row of the pixel circuits 511 of the display region 501 is scanned, each of the N-select-one selection circuits 530 may turn on the N selection transistors of each of the N-select-one selection circuits 530 in sequence in a positive direction of the first direction D1 (e.g., a direction from left to right in fig. 2A), thereby making it possible for a corresponding one of the signal conversion circuits 550 to sequentially receive the N sensing signals output from the sensing signal output terminals of the N pixel circuits 511 that are sequentially adjacent in the first direction D1 and use the N sensing signals in acquiring the threshold voltages of the N pixel circuits 511.

As shown in fig. 2A, in the first direction D1, the number of transistors between the xth on-state selection transistor in each one of the N-select-one selection circuits 530 and the xth on-state selection transistor in the adjacent one of the N-select-one selection circuits 530 is equal to N-1, that is, the number of sensing lines 521 between the xth selected sensing line 521 in each sensing line group 520 and the xth selected sensing line 521 in the adjacent sensing line group 520 is equal to N-1, and the number of pixel circuits 511 between the xth selected sensing signal outputting pixel circuit 511 in each pixel cell group 510 and the xth selected sensing signal outputting pixel circuit 511 in the adjacent pixel cell group 510 is equal to N-1.

For example, by connecting the N sensing lines 521 to the same signal conversion circuit 550, each signal conversion circuit 550 can be used to convert the sensing signals output from the sensing signal output terminals of N sequentially adjacent pixel circuits 511 in the display region 501 into digital signals; in this case, the number of signal conversion circuits 550 can be reduced, whereby the cost of the display panel can be reduced, particularly for a display panel using a signal conversion circuit with higher detection accuracy and higher price.

For example, in the case where the threshold voltages of the N pixel circuits 511 in each pixel cell group 510 are the same as each other, the data voltages received by the N pixel circuits 511 are the same as each other, and the setting voltages received by the N pixel circuits 511 are the same as each other, the change curves of the sensing signals output by the N pixel circuits 511 are all the same (for example, all are the curves shown in fig. 2B); as shown in fig. 2B, the variation curve of the sensing signal includes a reset phase REST, a threshold establishing phase TH _ B (i.e., a phase in which the sensing signal is increasing continuously), and a threshold reading phase TH _ R, where the threshold reading phase TH _ R is temporally located after the Vth establishing phase (i.e., after the sensing signal is increasing enough) and before the driving transistor of the pixel circuit 511 is turned off, in this case, the pixel circuit 511 charges the capacitor (e.g., the capacitor on the sensing line) sufficiently, and the value of the sensing signal is close to but not equal to the value of the sensing signal when the driving transistor is in the off state.

For example, in a case where each one-of-N selection circuit 530 sequentially turns on the N selection transistors of each one-of-N selection circuit 530 in the positive direction of the first direction D1 (e.g., the left-to-right direction in fig. 2A), the sensing voltages output by the N pixel circuits 511 sequentially received by the corresponding one signal conversion circuit 550 are the sensing signal S _1 output by the first pixel circuit 511 located in each pixel cell group 510, the sensing signals S _2, … … output by the second pixel circuit 511 located in each pixel cell group 510, the sensing signal S _ N-1 output by the N-1 th pixel circuit 511 located in each pixel cell group 510, and the sensing signal S _ N output by the N-th pixel circuit 511 located in each pixel cell group 510 (see fig. 2B), thereby causing the sensing signals acquired by the signal conversion circuit 550, the difference between the systematic error of the sensing signal of the first pixel circuit 511 located in each pixel cell group 510 and the systematic error of the sensing signal of the nth pixel circuit 511 is the largest, and thus, the difference between the systematic error of the sensing signal of the nth pixel circuit 511 in each pixel cell group 510 and the systematic error of the sensing signal of the first pixel circuit 511 in the adjacent pixel cell group 510 is the largest, and thus, in the compensation phase, the difference between the systematic errors of the threshold voltages compensated for the adjacent pixel circuits 511 in the adjacent pixel cell group 510 (e.g., the nth pixel circuit 511 in each pixel cell group 510 and the first pixel circuit 511 in the adjacent pixel cell group 510) is made larger. For example, in the case where the gray scales of the respective image sub-pixels of the image to be displayed are the same as each other, the difference in luminance (for example, the intensity of emitted light) of the light emitting elements driven by the adjacent pixel circuits 511 in the adjacent pixel cell group 510 is large, so that the above-described difference in luminance may be observed by the user.

At least one embodiment of the present disclosure provides a display panel, a signal reading method thereof, and a display device, the display panel including: the pixel array comprises a first pixel unit group, a second pixel unit group, a first N-selected one selection circuit, a second N-selected one selection circuit, a first sensing line group and a second sensing line group. The first pixel unit group and the second pixel unit group are adjacently arranged; the first pixel unit group comprises N first pixel circuits which are adjacent in sequence, the first sensing line group comprises N first sensing lines which are adjacent in sequence, and sensing signal output ends of the N first pixel circuits are electrically connected with the N first sensing lines respectively; the second pixel unit group comprises N second pixel circuits which are adjacent in sequence, the second sensing line group comprises N second sensing lines which are adjacent in sequence, and sensing signal output ends of the N second pixel circuits are electrically connected with the N second sensing lines respectively; the first N-out-of-one selection circuit comprises a first control end, a first signal output end and N first signal input ends, wherein the first control end is used for receiving a selection signal so as to sequentially select one of the N first signal input ends to be connected with the first signal output end; the second N-out-of-one selection circuit comprises a second control end, a second signal output end and N second signal input ends, wherein the second control end is used for receiving a selection signal so as to sequentially select one of the N second signal input ends to be connected with the second signal output end; the N first signal input ends are respectively and electrically connected with the N first sensing lines, and the N second signal input ends are respectively and electrically connected with the N second sensing lines; the total number of the partial first sensing lines and the partial second sensing lines arranged between the first sensing line connected with the first signal input end selected last and the second sensing line connected with the second signal input end selected first is larger than or equal to 1, and N is an integer larger than or equal to 2.

In some examples, a total number of the partial first sensing lines and the partial second sensing lines disposed between the first sensing line connected to the last selected first signal input terminal and the second sensing line connected to the first selected second signal input terminal is less than or equal to N-1.

For example, at least one embodiment of the present disclosure provides a display panel, a signal reading method thereof, and a display device, which can reduce the maximum value of the difference of the systematic errors in the luminance of light emitting elements driven by adjacent pixel circuits.

Fig. 3A is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure. As shown in fig. 3A, the display panel includes: the pixel driving circuit includes a first pixel cell group 111, a second pixel cell group 112, a first one-out-of-N selection circuit 130, a second one-out-of-N selection circuit 140, a first sensing line group 121, and a second sensing line group 122. As shown in fig. 3A, the display panel may further include a first signal conversion circuit 152 and a second signal conversion circuit 153 according to practical application requirements; here, N is an integer of 2 or more.

For example, as shown in fig. 3A, the display panel includes a display region 101 and a peripheral region disposed around the display region 101 of the display panel, the first pixel cell group 111 and the second pixel cell group 112 being located in the display region 101; the first one-of-N selection circuit 130, the second one-of-N selection circuit 140, the first signal conversion circuit 152 and the second signal conversion circuit 153 are located in the peripheral area; the first and second

sensing line groups

121 and 122 respectively extend from a display region of the display panel to a peripheral region of the display panel. For example, the first one-of-N selection circuit 130, the second one-of-N selection circuit 140, the first signal conversion circuit 152, and the second signal conversion circuit 153 may be located at one side (e.g., a lower side) of the display area. It should be noted that the display panel may not be provided with the first signal conversion circuit 152 and the first signal conversion circuit 152, and in this case, the first signal conversion circuit 152 and the second signal conversion circuit 153 outside the display panel may be electrically connected (e.g., directly connected) to the first N-select selection circuit 130 and the second N-select selection circuit 140 by bonding, respectively.

For example, as shown in fig. 3A, the first and second pixel cell groups 111 and 112 (e.g., the first and second

pixel cell groups

111 and 112 located at the leftmost side of fig. 3A) are adjacently disposed. It should be noted that, the adjacent arrangement of the first pixel cell group 111 and the second pixel cell group 112 means that no other pixel cell group or pixel cell (valid pixel cell group or valid pixel cell) is arranged in the first pixel cell group 111 and the second pixel cell, and other "adjacent arrangement" in this disclosure also has similar meaning, and is not described again. For example, as shown in fig. 3A, the first one-of-N selection circuit 130 and the second one-of-N selection circuit 140 are disposed adjacently; the first sensing wire group 121 and the second sensing wire group 122 are adjacently disposed; the first signal conversion circuit 152 and the second signal conversion circuit 153 are disposed adjacent to each other.

For example, the first pixel cell group 111, the first N-select-one selection circuit 130, and the first signal conversion circuit 152 are sequentially arranged in the second direction D2 intersecting the first direction D1, and the second pixel cell group 112, the second N-select-one selection circuit 140, and the second signal conversion circuit 153 are sequentially arranged in the second direction D2. For example, the first direction D1 may be a row direction of the display panel or an extending direction of gate lines of the display panel, and the second direction D2 may be a column direction of the display panel or an extending direction of data lines of the display panel. For example, the first direction D1 is perpendicular to the second direction D1.

For example, as shown in fig. 3A, the display panel may include a plurality of first pixel cell groups 111 and a plurality of second pixel cell groups 112, and the plurality of first pixel cell groups 111 and the plurality of second pixel cell groups 112 may be alternately arranged in the first direction D1 (i.e., a parallel arrangement direction of the plurality of first pixel cell groups 111 and the plurality of second pixel cell groups 112). Correspondingly, the display panel may include a plurality of first N-select selection circuits 130, a plurality of second N-select selection circuits 140, a plurality of first sensing line groups 121, a plurality of second sensing line groups 122, a plurality of first signal conversion circuits 152, and a plurality of second signal conversion circuits 153; the plurality of first N-select-one selection circuits 130 and the plurality of second N-select-one selection circuits 140 may be alternately arranged in the first direction D1; the plurality of first sensing line groups 121 and the plurality of second sensing line groups 122 may be alternately arranged in the first direction D1; the plurality of first signal conversion circuits 152 and the plurality of second signal conversion circuits 153 may be alternately arranged in the first direction D1.

For example, as shown in fig. 3A, the number of the plurality of first pixel cell groups 111, the number of the plurality of first N-select selection circuits 130, the number of the plurality of first sensing line groups 121, and the number of the plurality of first signal conversion circuits 152 are equal to each other (e.g., equal to M, M being an integer equal to or greater than 2); the number of the plurality of second pixel cell groups 112, the number of the plurality of second N-one selection circuits 140, the number of the plurality of second sensing line groups 122, and the number of the plurality of second signal conversion circuits 153 are equal to each other (e.g., equal to M).

For clarity, the following description is directed to the first pixel cell group 111, the second pixel cell group 112, the first N-select-one selection circuit 130, the second N-select-one selection circuit 140, the first sensing line group 121, the second sensing line group 122, the first signal conversion circuit 152, and the second signal conversion circuit 153 on the leftmost side of the display panel shown in fig. 3A, and the other first pixel cell group 111, the second pixel cell group 112, the first N-select-one selection circuit 130, the second N-select-one selection circuit 140, the first sensing line group 121, the second sensing line group 122, the first signal conversion circuit 152, and the second signal conversion circuit 153 in the display panel may be configured by referring to the following description, or may adopt other related designs, which is not repeated.

As shown in fig. 3A, the first pixel cell group 111 includes N rows of sequentially adjacent first pixel circuits 113, the first sensing line group 121 includes N sequentially adjacent first sensing lines 123, and sensing signal output terminals of the N rows of first pixel circuits 113 are electrically connected (e.g., directly connected) to the N first sensing lines 123, respectively, so that sensing signals of each row of first pixel circuits 113 can be provided to a corresponding one of the first sensing lines 123 in a time-sharing manner. As shown in fig. 3A, the second pixel cell group 112 includes N sequentially adjacent second pixel circuits 114, the second sensing cell group 122 includes N sequentially adjacent second sensing lines 124, and sensing signal output ends of the N second pixel circuits 114 are electrically connected (e.g., directly connected) to the N second sensing lines 124, respectively, so that the sensing signal of each column of the second pixel circuits 114 can be provided to a corresponding one of the second sensing lines 124 in a time-sharing manner. For example, when the pixel circuits (the first pixel circuit 113 and the second pixel circuit 114) in the jth row of the display region are selected, the sensing signal output from the selected pixel circuit (the pixel circuit in the jth row) in each column of the pixel circuits (the first pixel circuit 113 or the second pixel circuit 114) may be supplied to the corresponding sensing line. For example, J is 1 or more and 1 or less and the number of rows of pixel circuits in the display region.

For example, as shown in fig. 3A, N columns of the first pixel circuits 113 are sequentially adjacent in the first direction D1, N columns of the first sensing lines 123 are sequentially adjacent in the first direction D1, N columns of the second pixel circuits 114 are sequentially adjacent in the first direction D1, and N columns of the second sensing lines 124 are sequentially adjacent in the first direction D1. It should be noted that, the N first sensing lines 123 being sequentially adjacent in the first direction D1 means that the N first sensing lines 123 are sequentially arranged in the first direction D1, and other sensing lines (effective sensing lines) are not disposed between the adjacent first sensing lines 123, and other "sequentially adjacent" in the present disclosure also have similar meanings, and are not described again.

It should be noted that, for the sake of clarity, the number of the first pixels in each column of the first pixel circuits 113 and the number of the second pixel circuits 114 in each column of the second pixel circuits 114 shown in fig. 2A are both two, but the embodiments of the disclosure are not limited thereto, and the number of the first pixels in each column of the first pixel circuits 113 and the number of the second pixel circuits 114 in each column of the second pixel circuits 114 may also be 540, 1080, 2160 or other suitable numbers according to the practical application requirements.

For example, each pixel circuit shown in fig. 3A (e.g., each first pixel circuit 113 in the N columns of first pixel circuits 113 and each second pixel circuit 114 in the N columns of second pixel circuits 114) may employ the 3T1C pixel circuit shown in fig. 3B, but the embodiments of the present disclosure are not limited thereto, and each pixel circuit shown in fig. 3A may also employ the pixel circuit shown in fig. 1A, the pixel circuit shown in fig. 1B, or other suitable pixel circuits according to practical application requirements. For convenience of description, fig. 3B also shows a first power supply voltage terminal VDD, a second power supply voltage terminal VSS, a sensing line SENL, a data line DL, and a light emitting element EL associated with the pixel circuit.

For example, as shown in fig. 3B, each pixel circuit may include a driving transistor T3, a sensing switch transistor T2 (whose control terminal is G2), a gate transistor T1 (whose control terminal is G1), and a storage capacitor Cst; the second and first poles of the driving transistor T3 are configured to be connected to the first power voltage terminal VDD and the first pole of the light emitting element EL, respectively; a second pole of the light emitting element EL is connected to the second power supply voltage terminal VSS; a first pole of the sensing switching transistor T2 is electrically connected with a first pole of the driving transistor T3; a first pole of the sensing switch transistor T2 is electrically connected (e.g., directly connected) to a sensing line SENL (e.g., the first sensing line 123 or the second sensing line 124). Either a parasitic capacitance Csc is present on the sense line SENL or an additional capacitance is placed on the sense line SENL. For example, the voltage value of the first power voltage terminal VDD is higher than the voltage value of the second power voltage terminal VSS.

For example, the second poles (i.e., the sensing signal output ends of the first pixel circuits 113) of the sensing switching transistors T2 of the N first pixel circuits 113 are electrically connected to the N first sensing lines 123, respectively; the second poles (i.e., the sensing signal output ends of the second pixel circuits 114) of the sensing switching transistors T2 of the N second pixel circuits 114 are electrically connected to the N second sensing lines 124, respectively. For example, the second poles of the sensing switching transistors T2 of the N first pixel circuits 113 are directly connected to the N first sensing lines 123, respectively, and the second poles of the sensing switching transistors T2 of the N second pixel circuits 114 are directly connected to the N second sensing lines 124, respectively.

For example, as shown in fig. 3B, a first pole of the gate transistor T1 is connected to a data driving circuit (not shown in the figure) via a data line DL to obtain a data signal from the data driving circuit; the second pole of the gate transistor T1 is connected to the gate electrode of the driving transistor T3 and the first terminal of the storage capacitor Cst to write the acquired data signal to the gate electrode of the driving transistor T3 and the first terminal of the storage capacitor Cst; the second terminal of the storage capacitor Cst is connected to the first electrode of the driving transistor T3 and the first electrode of the sensing switch transistor T2, and is configured to store a data signal.

Fig. 3C is a schematic diagram of a first one-of-N selection circuit 130 according to at least one embodiment of the disclosure, and fig. 3D is a schematic diagram of a second one-of-N selection circuit 140 according to at least one embodiment of the disclosure. For example, as shown in fig. 3A, the first N-out-of-one selection circuit 130 includes a first control terminal 131, a first signal output terminal 132, and N first signal input terminals 133 (e.g., 133_1, 133_2, … … 133_ N-1, and 133_ N), the first control terminal 131 is configured to receive a selection signal to sequentially select one of the N first signal input terminals 133 to be connected to the first signal output terminal 132; as shown in fig. 3B, the second one-of-N selection circuit 140 includes a second control terminal 141, a second signal output terminal 142, and N second signal input terminals 143 (e.g., 143_1, 143_2, … … 143_ N-1 and 143_ N), where the second control terminal 141 is configured to receive a selection signal to sequentially select one of the N second signal input terminals 143 to be connected to the second signal output terminal 142; as shown in fig. 3A, the N first signal input terminals 133 are respectively connected to the N first sensing lines 123, and the N second signal input terminals 143 are respectively connected to the N second sensing lines 124.

For example, the first signal input terminal 133, the first sensing line 123, and the first pixel circuit 113, which are electrically connected to each other, have the same position number; the second signal input terminal 143, the second sensing line 124, and the second pixel circuit 114, which are electrically connected to each other, have the same position number. For example, the first signal input terminal 133 with position number X in the first direction D1 in the first one-of-N selection circuit 130, the first sensing line 123 with position number X in the first direction D1 in the first sensing line group 121, and the first pixel circuit 113 with position number X in the first direction D1 in the first pixel cell group 111 are electrically connected to each other.

For example, the specific implementation manners of the first one-of-N selection circuit 130 and the second one-of-N selection circuit 140 may be selected according to the actual application requirements; for clarity, specific examples of the first and second one-of-

N selection circuits

130 and 140 will be described in the examples shown in fig. 4A and 5.

It should be noted that "sequentially selecting" means selecting according to a predetermined order. For example, sequentially selecting one of the N first signal input terminals 133 to connect with the first signal output terminal 132 may refer to sequentially connecting the N first signal input terminals 133 with the first signal output terminal 132 according to the position arrangement order of the N first signal input terminals 133; the sequential selection of one of the N second signal input terminals 143 to be connected to the second signal output terminal 142 may refer to sequential connection of the N second signal input terminals 143 to the second signal output terminal 142 according to the position arrangement order of the N second signal input terminals 143; for example, the order of positional arrangement in which the N first signal input terminals 133 are sequentially connected to the first signal output terminal 132 and the order of positional arrangement in which the N second signal input terminals 143 are sequentially connected to the second signal output terminal 142 may be reversed.

In one example, the first one 133_1, the second one 133_2, the … …, the N-1 st first signal input 133_ N-1, and the nth first signal input 133_ N in the first N-select selection circuit 130 in a positive direction of the first direction D1 (e.g., in a left-to-right direction) may be sequentially electrically connected to the first signal output 132; correspondingly, the nth second signal input terminal 143_ N, the nth-1 second signal input terminals 143_ N-1, … …, the second signal input terminal 143_2 and the first second signal input terminal 143_1 in the positive direction of the first direction D1 (e.g., in the left-to-right direction) in the second N-one selection circuit 140 may be sequentially connected to the second signal output terminal 142. In this case, the total number of the part of the first sensing lines 123 and the part of the second sensing lines 124 provided between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143 is equal to 2 × (N-X), that is, the total number of the part of the first pixel circuits 113 and the part of the second pixel circuits 114 provided between the first pixel circuit 113 electrically connected to the xth selected first signal input terminal 133 and the second pixel circuit 114 electrically connected to the xth selected second signal input terminal 143 is equal to 2 × (N-X), where X is equal to or greater than 1 and equal to or less than N; for example, the number (N-X) of first sensing lines 123 disposed between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143 is equal to the number (N-X) of second sensing lines 124 disposed between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143. For example, the total number of the part of the first sensing lines 123 and the part of the second sensing lines 124 disposed between the first sensing line 123 connected to the last selected first signal input terminal 133 and the second sensing line 124 connected to the last selected second signal input terminal 143 is equal to 0.

In another example, the nth first signal input terminal 133_ N, the nth-1 first signal input terminals 133_ N-1, … …, the second first signal input terminal 133_2 and the first signal input terminal 133_1 in the positive direction of the first direction D1 (e.g., in the left-to-right direction) in the first N-select selection circuit 130 may be sequentially electrically connected to the first signal output terminal 132; correspondingly, the first second signal input terminal 143_1, the second signal input terminals 143_2, … …, the N-1 th second signal input terminal 143_ N-1 and the nth second signal input terminal 143_ N in the positive direction of the first direction D1 (e.g., in the left-to-right direction) in the second N-select selection circuit 140 may be sequentially connected to the second signal output terminal 142. In this case, the total number of the part of the first sensing lines 123 and the part of the second sensing lines 124 provided between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143 is equal to 2 × (X-1), that is, the total number of the part of the first pixel circuits 113 and the part of the second pixel circuits 114 provided between the first pixel circuit 113 electrically connected to the xth selected first signal input terminal 133 and the second pixel circuit 114 electrically connected to the xth selected second signal input terminal 143 is equal to 2 × (X-1), where X is equal to or greater than 1 and equal to or less than N. For example, the number (X-1) of first sensing lines 123 provided between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143 is equal to the number (X-1) of second sensing lines 124 provided between the first sensing line 123 connected to the xth selected first signal input terminal 133 and the second sensing line 124 connected to the xth selected second signal input terminal 143. For example, the total number of the part of the first sensing lines 123 and the part of the second sensing lines 124 disposed between the first sensing line 123 connected to the last selected first signal input terminal 133 and the second sensing line 124 connected to the last selected second signal input terminal 143 is equal to 2N-2.

It should be noted that "sequentially selecting" is not limited to the above two examples, and other applicable predetermined sequences may be selected according to practical application requirements, as long as the total number of the part of the first sensing lines 123 and the part of the second sensing lines 124 arranged between the first sensing line 123 connected to the last selected first signal input terminal 133 and the second sensing line 124 connected to the first selected second signal input terminal 143 is greater than or equal to 1 (e.g., greater than or equal to 1 and less than or equal to N-1); in this case, the total number of the partial first pixel circuits 113 and the partial second pixel circuits 114 provided between the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last and the second pixel circuit 114 connected to the second signal input terminal 143 selected first is equal to or greater than 1 (for example, equal to or greater than 1 and equal to or less than N-1).

For example, by making the total number of the part of the first pixel circuits 113 and the part of the second pixel circuits 114 provided between the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last and the second pixel circuit 114 electrically connected to the second signal input terminal 143 selected first 1 or more (for example, 1 or more and N-1 or less), the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last and the second pixel circuit 114 connected to the second signal input terminal 143 selected first are not adjacent, in this case, although the difference between the system error of the sensing signal having the largest system error output from the first pixel circuit 113 in the first pixel cell group 111 and the system error of the sensing signal having the smallest system error output from the second pixel circuit 114 in the second pixel cell remains unchanged for example, however, the first pixel circuit 113 in the first pixel cell group 111, which outputs the sensing signal having the largest system error, is not adjacent to the second pixel circuit 114 in the second pixel cell, which outputs the sensing signal having the smallest system error, so that the maximum value of the difference in the system errors in the luminance of the light emitting elements driven by the adjacent pixel circuits can be reduced. For example, in the case where the gray scales of the respective image sub-pixels of the image to be displayed are the same as each other, at least one embodiment of the present disclosure provides a display panel that can reduce the maximum value of the difference in luminance of the light emitting elements driven by the adjacent first and

second pixel circuits

113 and 114.

For example, the first signal conversion circuit 152 and the second signal conversion circuit 153 are analog-to-digital conversion circuits, respectively, and are configured to convert the received analog signals into digital signals, respectively, for subsequent processing (e.g., calculating threshold voltages of the drive transistors of the respective pixel circuits). For example, as shown in fig. 3A, the signal receiving terminal of the first signal conversion circuit 152 is connected to the first signal output terminal 132, and the signal receiving terminal of the second signal conversion circuit 153 is connected to the second signal output terminal 142. For example, when a certain row of pixel circuits in the display area is scanned (selected), the first signal conversion circuit 152 may sequentially receive the N first sensing signals output by the sensing signal output terminals of the N first pixel circuits 113 in the first pixel cell group 111 through the corresponding first sensing lines 123, and for example, sequentially convert the received N first sensing signals into corresponding first digital signals; the second signal conversion circuit 153 may sequentially receive the N second sensing signals output from the sensing signal output terminals of the N second pixel circuits 114 in the second pixel cell group 112 through the corresponding second sensing lines 124, and for example, sequentially convert the received N second sensing signals into corresponding second digital signals.

For example, according to the actual application requirement, a detection circuit (not shown in the figure) may be further disposed between each sensing line and the signal conversion circuit, that is, one end of the detection circuit is connected to the sensing line, and the other end is connected to the signal conversion circuit; the detection circuit may acquire a voltage (analog signal) on the sensing line at a specific timing based on the sampling signal and supply the acquired analog signal to the signal conversion circuit. For example, according to the actual application requirement, the output end of the detection circuit is further connected to an amplifying circuit, and the analog signal output by the detection circuit is amplified and then provided to the signal conversion circuit. For example, two ends of the detection circuit may be respectively connected between the sensing line and the one-from-N selection circuit, or respectively connected to the one-from-N selection circuit and the signal conversion circuit.

For example, the display panel may further include a signal adjusting circuit 154. For example, in the case where the positional arrangement order in which the N first signal input terminals 133 are sequentially connected to the first signal output terminal 132 is opposite to the positional arrangement order in which the N second signal input terminals 143 are sequentially connected to the second signal output terminal 142, the signal adjusting circuit is configured to reverse the order in time of the signal output by the second signal converting circuit or the signal output by the first signal converting circuit. For example, the signal conditioning circuit 154 may be implemented based on an FPGA (field programmable gate array) or other programmable circuitry used. For example, by providing the signal adjusting circuit 154, the difficulty of at least one of subsequent signal processing, signal storage, and signal reading can be simplified.

In one example, the signal adjusting circuit 154 is configured to be connected to the signal output terminal of the second signal conversion circuit 153, and configured to reverse the order in time of the signals (digital signals) received by the second signal conversion circuit 153, so that the order in time of the N second sensing signals output by the signal adjusting circuit 154 coincides with the positional arrangement order of the corresponding N second pixel circuits 114. For example, the second signal conversion circuit 153 may convert signals in time in a first arrangement order, where the first arrangement order refers to: the second sensing signal output from the nth second pixel circuit 114, the second sensing signal output from the N-1 st second pixel circuit 114, the second sensing signal … …, the second sensing signal output from the second pixel circuit 114, and the second sensing signal output from the first second pixel circuit 114 in the positive direction of the first direction D1 (e.g., in the left-to-right direction) are arranged from first to second in time; the second arrangement order is: the second sensing signal output from the first second pixel circuit 114 in the positive direction of the first direction D1 (e.g., in the left-to-right direction), the second sensing signal output from the second pixel circuit 114, … …, the second sensing signal output from the N-1 th second pixel circuit 114, and the nth sensing signal output from the first second pixel circuit 114 are arranged from first to second in time.

In another example, the signal adjusting circuit 154 is configured to be connected to the signal output terminal of the first signal conversion circuit 152, and configured to reverse the order in time of the signals (digital signals) received by the first signal conversion circuit 152, so that the order in time of the N first sensing signals output by the signal adjusting circuit 154 coincides with the positional arrangement order of the corresponding N first pixel circuits 113.

It should be noted that, in the case where the "sequential selection" corresponds to other applicable predetermined sequences, the signal adjusting circuit 154 is further configured to make the arrangement sequence of the first sensing signals output by the plurality of first pixel circuits located in the same row in the first pixel unit group in time be identical to the arrangement sequence of the plurality of first pixel circuits located in the same row in the first direction in the first pixel unit group; the signal adjusting circuit 154 is further configured such that an arrangement order in time of the second sensing signals output from the plurality of second pixel circuits located in the same row in the second pixel cell group coincides with an arrangement order in the first direction of the plurality of second pixel circuits located in the same row in the second pixel cell group.

For example, as shown in fig. 3A, the display panel may further include an arithmetic circuit 155, the arithmetic circuit 155 being configured to be connected to two of the first signal conversion circuit 152, the second signal conversion circuit 153, and the signal adjustment circuit 154 (e.g., connected to the first signal conversion circuit 152 and the second signal conversion circuit 153 or connected to the first signal conversion circuit 152 and the signal adjustment circuit 154) to receive the first sensing signal and the second sensing signal and acquire the threshold voltage of each first pixel circuit 113 in the first pixel cell group 111 based on the first sensing signal and acquire the threshold voltage of each second pixel circuit 114 in the second pixel cell group 112 based on the second sensing signal. For example, the threshold voltage of each first pixel circuit 113 and the threshold voltage of each second pixel circuit 114 may be used in threshold compensation for each first pixel circuit 113 and each second pixel circuit 114, respectively. For example, the threshold voltage of each first pixel circuit 113 and the threshold voltage of each second pixel circuit 114 may be stored in a memory.

In another example, the memory is configured to store the first sensing signal and the second sensing signal, in which case the memory is connected to two of the first signal conversion circuit 152, the second signal conversion circuit 153, and the signal adjustment circuit 154.

For example, in the threshold compensation of each of the first pixel circuits 113 and each of the second pixel circuits 114, a controller (e.g., a timing controller) is configured to receive the first data signal and the threshold voltage of each of the first pixel circuits 113 and the second data signal and the threshold voltage of each of the second pixel circuits 114, and is configured to acquire a compensated first data signal based on the first data signal and the threshold voltage of the first pixel circuit 113, acquire a compensated second data signal based on the second data signal and the threshold voltage of the second pixel circuit 114, the compensated first data signal and the compensated second data signal being configured to be supplied to a data driving circuit, the data driving circuit being configured to convert the compensated first data signal and the compensated second data signal into corresponding analog digital signals, and supply the corresponding analog digital signals to each of the first pixel circuits 113 and the second pixel circuits 114 of the display panel.

In some examples, the operation circuit 155, the first signal conversion circuit 152, the second signal conversion circuit 153, the signal adjustment circuit 154, the memory, the controller, and the data driving circuit may be integrated in one integrated circuit, for example, which may be directly disposed on the display panel or electrically connected to the display panel by bonding.

Fig. 4A is a schematic diagram of an example of the display panel shown in fig. 3A, fig. 4B shows a schematic diagram of the first one-of-N selection circuit 130 shown in fig. 4A, and fig. 4C shows a schematic diagram of the second one-of-N selection circuit 140 shown in fig. 4B.

For example, as shown in fig. 4A and 4B, the first control terminal 131 includes N sequentially adjacent first selection signal terminals 134; as shown in fig. 4A and 4C, the second control terminal 141 includes N sequentially adjacent second selection signal terminals 144.

For example, as shown in fig. 4A to 4C, the display panel further includes N selection control lines 151; the first selection signal terminal 134 corresponding to the xth selected first signal input terminal 133 and the second selection signal terminal 144 corresponding to the xth selected second signal input terminal 143 are connected to the same selection control line 151. In this case, the selection signal includes N selection sub-signals; the first control terminal 131 corresponding to the xth selected first signal input terminal 133 and the second control terminal 141 corresponding to the xth selected second signal input terminal 143 receive the same selection sub-signal.

It should be noted that the embodiment of the present disclosure provides that the first selection signal terminal 134 corresponding to the xth selected first signal input terminal 133 and the second selection signal terminal 144 corresponding to the xth selected second signal input terminal 143 and the same selection control line 151 are not limited to be connected to the same selection control line, and both may be connected to different selection control lines according to practical application requirements, as long as the first control terminal 131 corresponding to the xth selected first signal input terminal 133 and the second control terminal 141 corresponding to the xth selected second signal input terminal 143 are ensured to receive the same selection sub-signal.

For example, as shown in fig. 4A-4C, the first one-of-N selection circuit 130 includes N sequentially adjacent first selection sub-circuits 135, and the second one-of-N selection circuit includes N sequentially adjacent second selection sub-circuits 145; each of the N first selection sub-circuits 135 includes a control terminal, a first terminal, and a second terminal, the control terminal of each of the N first selection sub-circuits 135 is connected to a corresponding one of the N first selection signal terminals 134, the first terminal of each of the N first selection sub-circuits 135 is connected to a corresponding one of the N first signal input terminals 133, and the second terminal of each of the N first selection sub-circuits 135 is connected to the first signal output terminal 132; each of the N second selection sub-circuits 145 includes a control terminal, a first terminal, and a second terminal, the control terminal of each of the N second selection sub-circuits 145 is connected to a corresponding one of the N second selection signal terminals 144, the first terminal of each of the N second selection sub-circuits 145 is connected to a corresponding one of the N second signal input terminals 143, and the second terminal of each of the N second selection sub-circuits 145 is connected to the second signal output terminal 142.

It should be noted that the display panel provided in at least one embodiment of the present disclosure is not limited to the first N-select selection circuit shown in fig. 4B, and the first N-select selection circuit 1 shown in fig. 4D may also be used according to practical application requirements. Fig. 4D illustrates a schematic diagram of another first N-select selection circuit 130 provided by at least one embodiment of the present disclosure.

As shown in fig. 4D, the first N-select selecting circuit 130 further includes a first decoding circuit 170, the first decoding circuit 170 includes C signal input terminals 171 and N signal output terminals 172, and when the C signal input terminals 171 receive binary signals, C-ceil (log2(N)), ceil (log2(N)) represents rounding down to log2 (N)). For example, when N is 5-8, C is 3; when N is 9-16, C is 4. In this case, as shown in fig. 4D, the first control terminal 131 includes C first selection signal terminals 134, and the selection signal includes C selection sub-signals; c signal input ends 171 of the first decoding circuit 170 are respectively connected to C first selection control ends 134, and N signal output ends 172 of the first decoding circuit 170 are respectively connected to control ends of N selection sub-circuits; the first decoding circuit 170 is configured to cause a corresponding one of the signal output terminals 172 of the first decoding circuit 170 to output an active signal and cause the other signal output terminals 172 of the first decoding circuit 170 to output an inactive signal based on the received signal, thereby enabling the first N-out-of-one selection circuit 130 to sequentially select one of the N first signal input terminals 133 to be connected to the first signal output terminal 132. Correspondingly, the second one-of-N selection circuit 140 further includes a second decoding circuit (not shown in the figure), and the second decoding circuit includes C signal input terminals and N signal output terminals, which are not described herein again.

It should be noted that the signal input end 171 is not limited to receive binary signals, and may also be based on M-ary signals (e.g., decimal signals or hexadecimal signals), in which case, C ═ ceil (logm (n)), ceil (logm (n)) indicates that logm (n)) is rounded down.

For example, as shown in fig. 4A, each selection sub-circuit (e.g., each of the N first selection sub-circuits 135 and the N second selection sub-circuits 145) may be implemented as a transistor having a gate, a first pole, and a second pole configured as a control terminal, a first terminal, and a second terminal, respectively, of the selection sub-circuit. It should be noted that each selection sub-circuit is not limited to include one transistor as shown in fig. 4A, and each selection sub-circuit may also include a combination of two or more transistors or may include other suitable circuit structures according to the actual application requirements. For example, the transistors selected by the plurality of selection sub-circuits have the same conduction characteristics, and the transistors selected by the plurality of selection sub-circuits are all N-type transistors or all P-type transistors, for example.

For example, as shown in fig. 4A, the first selection sub-circuit 135 corresponding to the xth selected first signal input terminal 133 and the second selection sub-circuit 145 corresponding to the xth selected second signal input terminal 143 are located in the same row; correspondingly, the first control terminal 131 corresponding to the xth selected first signal input terminal 133 and the first control terminal 131 corresponding to the xth selected second signal input terminal 143 are located in the same row.

It should be noted that the N-out-of-one circuit (the first N-out-of-one circuit and the second N-out-of-one circuit) is not limited to the example shown in fig. 4A, and other suitable circuit structures may be adopted for the N-out-of-one circuit, which is not described herein again.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish the gate of the transistor from the control terminal, one of the terminals is directly described as the first terminal, and the other terminal is directly described as the second terminal, so that the first terminal and the second terminal of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first terminal of the transistor of the embodiments of the present disclosure may be a source, and the second terminal may be a drain; or the first end of the transistor is a drain electrode, and the second end of the transistor is a source electrode. In addition, transistors can be divided into N-type and P-type transistors according to the characteristic distinction of the transistors, the type of the transistors is not limited by the embodiment of the disclosure, and the embodiment in the disclosure can be realized by using N-type and/or P-type transistors according to the actual requirement by a person skilled in the art.

At least one embodiment of the present disclosure also provides a signal reading method for a display panel provided in any one of the embodiments of the present disclosure, including: one of the N first signal input ends is sequentially selected to be connected with the first signal output end through a first N-out-of-one selection circuit; one of the N second signal input ends is sequentially selected to be connected with the second signal output end through a second N-out-of-one selection circuit.

Fig. 5 is a schematic flowchart of a signal reading method of a display panel provided by at least one embodiment of the present disclosure, the signal reading method including the following steps S100 and S200.

Step S100: one of the N first signal input ends is sequentially selected to be connected with the first signal output end through the first N-out-of-one selection circuit.

Step S200: one of the N second signal input ends is sequentially selected to be connected with the second signal output end through a second N-out-of-one selection circuit.

For example, the total number of the partial first sensing lines and the partial second sensing lines provided between the first sensing line connected to the xth selected first signal input terminal and the second sensing line connected to the xth selected second signal input terminal is equal to 2 × (N-X) or 2 × (X-1); that is, the total number of the partial first pixel circuits and the partial second pixel circuits provided between the first pixel circuit electrically connected to the xth selected first signal input terminal and the second pixel circuit electrically connected to the xth selected second signal input terminal is 2 × (N-X) or 2 × (X-1), where X is 1 or more and N or less. For example, the signal reading method of the display panel can refer to the embodiment of the display panel, and is not described herein again.

For example, step S100 is performed before the voltages of the first electrodes of the driving transistors of the first pixels are stable and the driving transistors of the first pixels are turned off. For example, the ratio of the voltage of the first pole of the driving transistor of each first pixel to the voltage of the first pole (source voltage) after the driving transistor of the first pixel is turned off is greater than 90% (e.g., greater than 95%, greater than 98%, greater than 99%, or greater than 99.5%).

For example, step S200 is performed before the voltages of the first electrodes of the driving transistors of the plurality of second pixels are stable and the driving transistors of the plurality of second pixels are turned off. For example, the ratio of the voltage of the first pole of the driving transistor of each second pixel to the voltage of the first pole (source voltage) of the second pixel after the driving transistor is turned off is greater than 90% (e.g., greater than 95%, greater than 98%, greater than 99%, or greater than 99.5%).

Fig. 6 is an exemplary block diagram of the display device 10 provided by at least one embodiment of the present disclosure. For example, as shown in fig. 6, the display device 10 includes a display panel 100.

For example, fig. 7 shows a schematic view of the display device 10 shown in fig. 6. For example, as shown in fig. 7, the display device 10 includes a pixel circuit of a display panel 100, a signal converter ADC, a data line DL, a sensing line SENL, and a control device 120, the display device 10 having a display area and a peripheral area disposed around the display area; the display region of the display device 10 includes a plurality of pixel units, each of which may include a pixel circuit, and the pixel units included in the display device 10 may be arranged in an array, for example, and accordingly the pixel circuits may be arranged in an array, for example. It should be noted that, for clarity, the display device 10 only shows one pixel circuit, but the embodiments of the disclosure are not limited thereto.

As shown in fig. 7, the control device 120 is disposed in the peripheral area outside the display area. For example, the display device 10 may further include a data driving circuit 130, a detection circuit 140, and a scan driving circuit (not shown) also disposed in the peripheral area.

For example, the pixel circuit shown in fig. 3B, the pixel circuit shown in fig. 1A, the pixel circuit shown in fig. 1B, or other suitable pixel circuits may be adopted as the pixel circuit, and the detailed structure of the pixel circuit is not described herein again. As shown in fig. 7, the pixel circuit includes a driving transistor T3 including a first pole, a sensing switch transistor T2 (whose control terminal is G2) and a gate transistor T1 (whose control terminal is G1), and the sensing line SENL is electrically connected to the first pole of the driving transistor T3.

For example, the detection circuit 140 is configured to read a first sensing voltage from the sense line SENL. For example, the detection circuit 140 may be a sampling circuit, which may provide a sampling signal SAMP and may obtain a first sensing voltage from the first pole of the driving transistor T3 via the sensing switch transistor T2.

The display apparatus 10 further comprises, for example, a selection signal generator (not shown in the figure) configured to generate a selection signal in response to a control signal of the control apparatus 120.

For example, the control device 120 is configured to perform threshold compensation (e.g., generate compensated signals for the respective pixel circuits of the display panel) for the respective pixel circuits of the display panel based on the sensing signal provided by the signal converter ADC or using a threshold signal (threshold voltage) acquired based on the sensing signal acquired by the signal converter ADC.

For example, the control device 120 is also configured to control the data driving circuit 130 and the detection circuit 140. For example, the data driving circuit 130 is configured to provide the compensated data voltages at different times according to actual application requirements. The scan driving circuit is to provide scan signals of the sensing switch transistor T2 and the gate transistor T1 to control the turn-on states (e.g., on or off) of the sensing switch transistor T2 and the gate transistor T1.

It should be noted that, for convenience of description, some embodiments of the present disclosure introduce signal input terminals, signal output terminals, etc., but those skilled in the art will understand that the signal input terminals, the signal output terminals, etc., are paths through which signals are transmitted, and it is not required that, for example, pad structures exist in the display panel as the signal input terminals, the signal output terminals, etc. In some examples, as shown in fig. 4A, the signal input end, the signal output end, etc. may be integrally formed with the sensing line, which is not described again.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims

1. A display panel, comprising: a first pixel cell group, a second pixel cell group, a first N-selected-one selection circuit, a second N-selected-one selection circuit, a first sensing line group and a second sensing line group,

wherein the first pixel cell group and the second pixel cell group are adjacently disposed;

the first pixel unit group comprises N sequentially adjacent first pixel circuits, the first sensing line group comprises N sequentially adjacent first sensing lines, sensing signal output ends of the N first pixel circuits are respectively and electrically connected with the N first sensing lines, and the N first sensing lines are configured to respectively receive N first sensing signals output by sensing signal output ends of the N first pixel circuits;

the second pixel unit group comprises N sequentially adjacent second pixel circuits, the second sensing unit group comprises N sequentially adjacent second sensing lines, sensing signal output ends of the N second pixel circuits are respectively and electrically connected with the N second sensing lines, and the N second sensing lines are configured to respectively receive N second sensing signals output by sensing signal output ends of the N second pixel circuits;

the first N-out-of-one selection circuit comprises a first control end, a first signal output end and N first signal input ends, wherein the N first signal input ends are respectively electrically connected with the N first sensing lines, the first control end is used for receiving a selection signal to sequentially select one of the N first signal input ends to be connected with the first signal output end, so that the first signal output end sequentially outputs N first sensing signals output by the sensing signal output ends of the N first pixel circuits;

the second N-out-of-one selection circuit comprises a second control terminal, a second signal output terminal and N second signal input terminals, the N second signal input terminals are electrically connected with the N second sensing lines respectively, the second control terminal is configured to receive the selection signal to sequentially select one of the N second signal input terminals to be connected with the second signal output terminal, so that the second signal output terminal sequentially outputs N second sensing signals output by the sensing signal output terminals of the N second pixel circuits; and

the total number of the partial first sensing lines and the partial second sensing lines arranged between the first sensing line connected with the first signal input end selected last and the second sensing line connected with the second signal input end selected first is larger than or equal to 1, and N is an integer larger than or equal to 2.

2. The display panel according to claim 1, wherein a total number of a part of the first sensing lines and a part of the second sensing lines disposed between the first sensing lines connected to the last selected first signal input terminal and the second sensing lines connected to the last selected second signal input terminal is equal to 0 or 2N "2.

3. The display panel according to claim 1, wherein a total number of a part of the first sensing lines and a part of the second sensing lines provided between the first sensing lines connected to the xth selected first signal input terminal and the second sensing lines connected to the xth selected second signal input terminal is equal to 2 × (N-X) or 2 × (X-1), and wherein X is 1 or more and N or less.

4. The display panel according to claim 3, wherein the number of the first sensing lines provided between the first sensing line connected to the Xth selected first signal input terminal and the second sensing line connected to the Xth selected second signal input terminal is equal to the number of the second sensing lines provided between the first sensing line connected to the Xth selected first signal input terminal and the second sensing line connected to the Xth selected second signal input terminal.

5. The display panel according to any one of claims 1 to 4, wherein a total number of a part of the first sensing lines and a part of the second sensing lines provided between the first sensing lines connected to the first signal input terminal selected last and the second sensing lines connected to the second signal input terminal selected first is not more than N-1.

6. The display panel according to claim 1 or 2, wherein the first control terminal includes N sequentially adjacent first selection signal terminals;

the second control end comprises N second selection signal ends which are adjacent in sequence.

7. The display panel of claim 6, wherein the selection signal comprises N selection sub-signals; and

the first control terminal corresponding to the xth selected first signal input terminal and the second control terminal corresponding to the xth selected second signal input terminal receive the same select sub-signal.

8. The display panel of claim 7, further comprising N selection control lines, wherein the first selection signal terminal corresponding to the xth selected first signal input terminal and the second selection signal terminal corresponding to the xth selected second signal input terminal are connected to the same selection control line.

9. The display panel of claim 6, wherein the first N-out-of-one selection circuit comprises N sequentially adjacent first selection sub-circuits, and the second N-out-of-one selection circuit comprises N sequentially adjacent second selection sub-circuits;

each of the N first selection sub-circuits includes a control terminal, a first terminal and a second terminal, the control terminal of each of the N first selection sub-circuits is connected to a corresponding one of the N first selection signal terminals, the first terminal of each of the N first selection sub-circuits is connected to a corresponding one of the N first signal input terminals, and the second terminal of each of the N first selection sub-circuits is connected to the first signal output terminal; and

each of the N second selection sub-circuits includes a control terminal, a first terminal, and a second terminal, the control terminal of each of the N second selection sub-circuits is connected to a corresponding one of the N second selection signal terminals, the first terminal of each of the N second selection sub-circuits is connected to a corresponding one of the N second signal input terminals, and the second terminal of each of the N second selection sub-circuits is connected to the second signal output terminal.

10. The display panel according to any one of claims 1 to 4, wherein the display panel includes a plurality of first pixel cell groups, a plurality of second pixel cell groups, a plurality of first N-selected-one selection circuits, a plurality of second N-selected-one selection circuits, a plurality of first sensing line groups, and a plurality of second sensing line groups;

the plurality of first pixel unit groups and the plurality of second pixel unit groups are alternately arranged in a direction of parallel arrangement of the plurality of first pixel unit groups and the plurality of second pixel unit groups;

the plurality of first N-selected-one selection circuits and the plurality of second N-selected-one selection circuits are alternately arranged in the direction; and

the plurality of first sensing line groups and the plurality of second sensing line groups are alternately arranged in the direction.

11. The display panel according to any one of claims 1 to 4, further comprising a first signal conversion circuit and a second signal conversion circuit, wherein a signal receiving terminal of the first signal conversion circuit is connected to the first signal output terminal, and a signal receiving terminal of the second signal conversion circuit is connected to the second signal output terminal.

12. The display panel according to claim 11, wherein the first signal conversion circuit and the second signal conversion circuit are analog-to-digital conversion circuits, respectively.

13. The display panel according to claim 11, further comprising a signal adjustment circuit, wherein the signal adjustment circuit is configured to reverse a signal output by the second signal conversion circuit or a signal output by the first signal conversion circuit in time.

14. The display panel according to any one of claims 1 to 4, wherein each of the N first pixel circuits and the N second pixel circuits includes a driving transistor and a sensing switch transistor;

the second and first poles of the driving transistor are configured to be connected to a first power supply voltage terminal and a first pole of the light emitting element, respectively;

the second pole of the light emitting element is connected to a second power supply voltage terminal;

a first pole of the sensing switch transistor is electrically connected with a first pole of the driving transistor;

second poles of sensing switch transistors of the N first pixel circuits are electrically connected with the N first sensing lines respectively; and

second poles of sensing switch transistors of the N second pixel circuits are electrically connected with the N second sensing lines respectively.

15. A display device comprising a display panel as claimed in any one of claims 1 to 14.

16. A signal reading method of the display panel according to any one of claims 1 to 14, comprising:

one of the N first signal input ends is sequentially selected to be connected with the first signal output end through the first N-out-of-one selection circuit;

and one of the N second signal input ends is sequentially selected to be connected with the second signal output end through the second N-out-of-one selection circuit.