WO2020253376A1

WO2020253376A1 - Display panel, signal reading method therefor and display apparatus

Info

Publication number: WO2020253376A1
Application number: PCT/CN2020/086683
Authority: WO
Inventors: 殷新社
Original assignee: 京东方科技集团股份有限公司
Priority date: 2019-06-19
Filing date: 2020-04-24
Publication date: 2020-12-24
Also published as: CN110070832B; CN110070832A

Abstract

A display panel, a signal reading method therefor and a display apparatus. The display panel comprises a first pixel unit group (111) and a second pixel unit group (112) that are adjacent to each other, a first N-to-1 multiplexer circuit (130), a second N-to-1 multiplexer circuit (140), a first sensing line group (121), and a second sensing line group (122). The pixel unit groups (111; 112) comprise N sequentially adjacent pixel circuits (113; 114). The sensing line groups (121; 122) comprise N sequentially adjacent sensing lines (123; 124). Sensing signal output terminals of the N pixel circuits (113; 114) are electrically connected to the N sensing lines (123; 124) respectively. The N-to-1 multiplexer circuits (130; 140) comprise control terminals (131; 141), signal output terminals (132; 142), and N signal input terminals (133; 143). The control terminals (131; 141) are used to receive selection signals so as to sequentially select one of the N signal input terminals (133; 143) to connect to the signal output terminals (132; 142). The N signal input terminals (133; 143) are electrically connected to the N sensing lines (123; 124) respectively. The total number of a part of the sensing lines (123; 124) disposed between the first sensing line (123) connected to the last selected first signal input terminal (133) and the second sensing line (124) connected to the first selected second signal input terminal (143) is greater than or equal to one.

Description

Display panel and its signal reading method and display device

Cross reference to related applications

This application claims the priority of Chinese Patent Application No. 201910530072.X filed on June 19, 2019. For all purposes, the disclosure of the above-mentioned Chinese patent application is quoted here in full as a part of this application.

Technical field

The embodiments of the present disclosure relate to a display panel, a signal reading method thereof, and a display device.

Background technique

Organic Light Emitting Diode (OLED) display panels have gradually gained popularity due to their advantages such as wide viewing angle, high contrast, fast response speed, higher luminous brightness and lower driving voltage compared to inorganic light-emitting display devices. Wide attention. Due to the above characteristics, organic light emitting diode (OLED) display panels can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, and instrumentation.

Summary of the invention

At least one embodiment of the present disclosure provides a display panel, which includes: a first pixel unit group, a second pixel unit group, a first N one-N selection circuit, a second N one-N selection circuit, and a first sensing line Group and the second sensing line group. The first pixel unit group and the second pixel unit group are arranged adjacent to each other; the first pixel unit group includes N sequentially adjacent first pixel circuits, and the first sensing line group includes sequentially adjacent The N first sensing lines of the N first pixel circuits are respectively electrically connected to the N first sensing lines; the second pixel unit group includes N sequentially adjacent , The second sensing line group includes N second sensing lines adjacent to each other in sequence, and the sensing signal output terminals of the N second pixel circuits are connected to the N second sensing lines respectively. The measuring line is electrically connected; the first N one-to-n selection circuit includes a first control terminal, a first signal output terminal and N first signal input terminals, and the first control terminal is used to receive a selection signal to sequentially select One of the N first signal input terminals is connected to the first signal output terminal; the second N one-to-one selection circuit includes a second control terminal, a second signal output terminal and N second signal input terminals, so The second control terminal is used to receive the selection signal to sequentially select one of the N second signal input terminals to be connected to the second signal output terminal; the N first signal input terminals are respectively connected to the N first sensing lines are electrically connected, and the N second signal input terminals are electrically connected to the N second sensing lines respectively; and the first sensing line connected to the first signal input terminal selected last The total number of part of the first sensing line and part of the second sensing line set between the test line and the second sensing line connected to the second signal input terminal selected first is greater than or equal to 1, and N is An integer greater than or equal to 2.

For example, in at least one example of the display panel, the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected last The total number of part of the first sensing line and part of the second sensing line arranged between the lines is equal to 0 or 2N-2.

For example, in at least one example of the display panel, the first sensing line connected to the Xth selected first signal input terminal and the second sensing line connected to the Xth selected second signal input terminal The total number of part of the first sensing line and part of the second sensing line set between the sensing lines is equal to 2×(NX) or 2×(X-1), and the X is greater than or equal to 1 and less than Equal to N.

For example, in at least one example of the display panel, the first sensing line connected to the Xth selected first signal input terminal and the Xth selected second signal input terminal The number of the first sensing lines set between the connected second sensing lines is equal to the number of the first sensing lines connected to the Xth selected first signal input terminal and the Xth The number of the second sensing lines set between the second sensing lines connected to the selected second signal input terminals.

For example, in at least one example of the display panel, the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected first The total number of the part of the first sensing line and the part of the second sensing line set between is less than or equal to N-1.

For example, in at least one example of the display panel, the first control terminal includes N sequentially adjacent first selection signal terminals; and the second control terminal includes N sequentially adjacent second selection signal terminals end.

For example, in at least one example of the display panel, the selection signal includes N selection sub-signals; and a first control terminal corresponding to the X-th selected first signal input terminal and corresponding to the The second control terminals of the X selected second signal input terminals receive the same selector signal.

For example, in at least one example of the display panel, the display panel further includes N selection control lines, wherein the first selection signal terminal corresponding to the X-th selected first signal input terminal and The second selection signal terminal corresponding to the X-th selected second signal input terminal is connected to the same selection control line among the N selection control lines.

For example, in at least one example of the display panel, the first N one-N selection circuit includes N sequentially adjacent first selection sub-circuits, and the second N one-N selection circuit includes N sequentially adjacent first selection sub-circuits. Each of the N first selection sub-circuits includes a control terminal, a first terminal, and a second terminal, and the control terminal of each of the N first selection sub-circuits is connected to the N A corresponding one of the N first selection signal terminals is connected, a first terminal of each of the N first selection sub-circuits is connected to a corresponding one of the N first signal input terminals, and the N first selection The second terminal of each sub-circuit is connected to the first signal output terminal; and each of the N second selection sub-circuits includes a control terminal, a first terminal, and a second terminal, the N second The control terminal of each selection sub-circuit is connected to a corresponding one of the N second selection signal terminals, and the first terminal of each of the N second selection sub-circuits is connected to the N second signal input terminals The corresponding one of the N second selection sub-circuits is connected, and the second terminal of each of the N second selection sub-circuits is connected to the second signal output terminal.

For example, in at least one example of the display panel, the display panel includes a plurality of first pixel unit groups, a plurality of second pixel unit groups, a plurality of first N one-N selection circuits, and a plurality of second N selection circuits. A selection circuit, a plurality of first sensing line groups and a plurality of second sensing line groups; the plurality of first pixel unit groups and the plurality of second pixel unit groups are in the plurality of first pixel units The groups and the plurality of second pixel unit groups are alternately arranged in the parallel arrangement direction; the plurality of first-N one-N selection circuits and the plurality of second one-N selection circuits are arranged in the parallel arrangement direction And the plurality of first sensing line groups and the plurality of second sensing line groups are alternately arranged in the parallel arrangement direction.

For example, in at least one example of the display panel, the display panel further includes a first signal conversion circuit and a second signal conversion circuit, wherein the signal receiving end of the first signal conversion circuit is connected to the first signal The output end is connected, and the signal receiving end of the second signal conversion circuit is connected to the second signal output end.

For example, in at least one example of the display panel, the first signal conversion circuit and the second signal conversion circuit are respectively analog-to-digital conversion circuits.

For example, in at least one example of the display panel, 2 the display panel further includes a signal adjustment circuit, wherein the signal adjustment circuit is configured to convert the signal output by the second signal conversion circuit or the first signal The signals output by the conversion circuit are reversed in time.

For example, in at least one example of the display panel, each of the N first pixel circuits and the N second pixel circuits includes a driving transistor and a sensing switch transistor; the second electrode of the driving transistor And the first pole are configured to be respectively connected to the first power supply voltage terminal and the first pole of the light emitting element; the second pole of the light emitting element is connected to the second power supply voltage terminal; the first pole of the sensing switch transistor and The first pole of the driving transistor is electrically connected; the second poles of the sensing switch transistors of the N first pixel circuits are electrically connected to the N first sensing lines respectively; and the N second pixels The second poles of the sensing switch transistors of the circuit are electrically connected to the N second sensing lines respectively.

At least one embodiment of the present disclosure also provides a display device, which includes the display panel provided by any embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a signal reading method for the display panel provided by any embodiment of the present disclosure, which includes: sequentially selecting the N one-N selection circuits through the first one-N selection circuit. One of the first signal input terminals is connected to the first signal output terminal; one of the N second signal input terminals is sequentially selected to be connected to the second signal output terminal by the second N one-N selection circuit .

For example, in at least one example of the signal reading method of the display panel, the first N one-N selection circuit is used to sequentially select one of the N first signal input terminals and the first signal Connecting to the output terminal and sequentially selecting one of the N second signal input terminals to be connected to the second signal output terminal through the second N one-to-N selection circuit includes: Part of the first sensing line and part of the second sensing line provided between the first sensing line connected to the signal input terminal and the second sensing line connected to the second signal input terminal selected first The total number of survey lines is greater than or equal to 1, and N is an integer greater than or equal to 2.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the drawings of the embodiments. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

Fig. 1A is a schematic diagram of a pixel circuit;

FIG. 1B is a schematic diagram of another pixel circuit;

FIG. 1C is a schematic diagram of another pixel circuit;

Figure 1D is a graph showing the change of sensing voltage over time;

FIG. 2A is a schematic diagram of a display panel;

FIG. 2B is a curve of the voltage of the source of the driving transistor of the display panel shown in FIG. 2A changing with time;

3A is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure;

3B is an example of the first pixel circuit and the second pixel circuit provided by at least one embodiment of the present disclosure;

FIG. 3C is a schematic diagram of a first one-N selection circuit provided by at least one embodiment of the present disclosure;

Fig. 3D is a schematic diagram of a second one-N selection circuit provided by at least one embodiment of the present disclosure;

4A is a schematic diagram of an example of the display panel shown in FIG. 3A;

4B shows a schematic diagram of the first one-N selection circuit shown in FIG. 4A;

FIG. 4C shows a schematic diagram of the second one-N selection circuit shown in FIG. 4B;

FIG. 4D shows a schematic diagram of another first one-N selection circuit provided by at least one embodiment of the present disclosure;

FIG. 5 is a schematic flowchart of a signal reading method of a display panel provided by at least one embodiment of the present disclosure;

FIG. 6 is an exemplary block diagram of a display panel provided by at least one embodiment of the present disclosure; and

FIG. 7 is a schematic diagram of the display panel shown in FIG. 6.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, "including" or "including" and other similar words mean that the elements or items appearing in front of the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

The pixel circuit in an organic light emitting diode (OLED) display panel generally adopts a matrix driving mode. According to whether switching components are introduced in each pixel unit, OLED display panels can be divided into active matrix (Active Matrix) drive type and passive matrix (Passive Matrix) drive type. The pixel circuit of each pixel unit of the AMOLED (that is, active matrix driven OLED) display panel includes a thin film transistor and a storage capacitor. By controlling the thin film transistor and the storage capacitor, the intensity of the current used to drive the OLED to emit light can be controlled. So that the OLED emits light as needed.

The basic pixel circuit used in the AMOLED display panel is usually a 2T1C pixel circuit, that is, a pixel circuit that uses two thin-film transistors (TFT) and a storage capacitor Cst to drive the OLED to emit light. Figures 1A and 1B show schematic diagrams of two types of 2T1C pixel circuits.

As shown in FIG. 1A, a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cst. For example, the gate of the switching transistor T0 is connected to a scan line (not shown in the figure) to receive the scan signal Scan1; for example, the source of the switching transistor T0 is connected to a data line (not shown in the figure) to receive the data signal Vdata The drain of the switching transistor T0 is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to the first voltage terminal to receive the first voltage Vdd, and the drain of the driving transistor N0 is connected to the positive terminal of the OLED; storage One end of the capacitor Cst is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the first voltage terminal; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage. Voltage Vss. For example, the voltage value of the first voltage Vdd is greater than the voltage value of the second voltage Vss. The 2T1C pixel circuit uses two TFTs and a storage capacitor Cst to control the gray scale of the pixel unit including the pixel circuit. When the scan signal Scan1 (applied via the scan line) turns on the switching transistor T0, the data signal Vdata (provided by the data driving circuit) sent via the data line will charge the storage capacitor Cst via the switching transistor T0, so that the data signal Vdata can be stored in In the storage capacitor Cst, and the data signal Vdata stored in the storage capacitor Cst can control the degree of conduction of the driving transistor N0, thereby controlling the intensity of the driving current (used to drive the OLED to emit light) generated by the driving transistor N0. The intensity of determines the gray scale of the pixel unit including the pixel circuit. In the 2T1C pixel circuit shown in FIG. 1A, the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.

As shown in FIG. 1B, another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cst. However, compared to the pixel circuit shown in FIG. 1A, the connection method of the pixel circuit shown in FIG. 1B is slightly different. Change, and the driving transistor N0 is an N-type transistor. The changes of the pixel circuit of FIG. 1B relative to the pixel circuit shown in FIG. 1A include: the positive terminal of the OLED is connected to the first voltage terminal to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the driving transistor N0 At the drain, the source of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage). One end of the storage capacitor Cst is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the source of the driving transistor N0 and the second voltage terminal. The working mode of the 2T1C pixel circuit shown in FIG. 1B is basically the same as that of the pixel circuit shown in FIG. 1A, and will not be repeated here.

In addition, for the pixel circuit shown in FIG. 1A and FIG. 1B, the switching transistor T0 is not limited to an N-type transistor, but may also be a P-type transistor, which will not be repeated here.

An OLED display panel usually includes a plurality of pixel units arranged in an array, and each pixel unit may include the aforementioned pixel circuit, for example. The inventors of the present disclosure have noticed in their research that in OLED display panels, the threshold voltage of the driving transistor in each pixel circuit may be different due to the manufacturing process; and, due to, for example, the influence of temperature changes, the threshold voltage of the driving transistor may be Drift occurs, so that when multiple pixel circuits of the OLED display panel receive the same data signal, the drive current intensities generated by the drive transistors of the multiple pixel circuits may be different from each other, and thus cause the multiple pixel circuits to drive light emission. The intensity of the light emitted by the element and the gray scales of multiple pixel units may be different from each other, thereby reducing the brightness uniformity and/or display quality of the OLED display panel. In summary, the threshold voltage needs to be compensated (for example, real-time compensation) to ensure the display effect of the OLED display panel.

The inventors of the present disclosure have noticed in their research that although the internal compensation technology can be used to perform threshold compensation for each pixel circuit of the OLED display panel, the structure of the pixel circuit using the internal compensation technology is complex (with more transistors and control Therefore, the pixel circuit adopting the internal compensation technology is not suitable for the display panel with the smaller pixel unit size, which is not conducive to the improvement of the resolution of the display panel.

The inventors of the present disclosure also noticed in their research that the external compensation technology can also be used to perform threshold compensation for each pixel circuit of the OLED display panel, which will be illustrated below with reference to FIG. 1C.

For example, FIG. 1C shows a pixel circuit (that is, a 3T1C circuit) that can detect the threshold voltage of a driving transistor, and the driving transistor N0 is an N-type transistor. For example, as shown in FIG. 1C, in order to realize the compensation function, the sensing transistor S0 can be introduced on the basis of the 2T1C circuit, that is, the first end of the sensing transistor S0 can be connected to the source of the driving transistor N0, and the sensing The second end of the transistor S0 is connected to a detection circuit (not shown in FIG. 1C) via a sensing line SENL.

For example, a set voltage (ie, reset signal) Vref may be applied to the source of the driving transistor N0 in the reset phase, and a data signal (for example, the gate of the driving transistor N0 may be applied via the switching transistor T0 at the beginning of the threshold setting phase) Data voltage) Vdata, where Vdata>Vref+Vth, and Vth represents the threshold voltage of the driving transistor, so the data signal Vdata can turn on the driving transistor N0. After the driving transistor N0 is turned on, the detection circuit is discharged through the sensing transistor S0 or the capacitance or parasitic capacitance Csc set on the sensing line through the sensing transistor S0 is charged, so that the source voltage Vs of the driving transistor N0 changes. When the source voltage Vs of the driving transistor N0 is equal to the difference between the gate voltage Vg of the driving transistor N0 and the threshold voltage Vth of the driving transistor, the driving transistor N0 will be turned off and the source voltage Vs of the driving transistor N0 will not change. For example, after the driving transistor N0 is turned off, the turned-off source voltage (that is, the source voltage Vb after the driving transistor N0 is turned off) can be obtained from the source of the driving transistor N0 through the turned-on sensing transistor S0. After obtaining the cut-off source voltage Vb, the threshold voltage of the driving transistor (that is, Vth=Vdata-Vb) can be obtained. In this way, the data signal (data voltage) to be displayed of the pixel circuit can be compensated based on the threshold voltage of the driving transistor in each pixel circuit, and the compensated data signal can be used to drive the pixel circuit. Sub-pixel threshold voltage compensation function. For example, the compensated Vdata_C can be expressed by the following expression: Vdata_C=Vdata+Vth.

The inventors of the present disclosure have also noticed in their research that, in order to obtain the accurate thresholds of each pixel circuit of the OLED display panel, the threshold detection requires a long time. The influence of the threshold detection time on the accuracy of the threshold detection of the pixel circuit will be exemplified below in conjunction with FIG. 1D.

FIG. 1D shows a graph of the source voltage obtained from the source of the driving transistor N0 via the turned-on sensing transistor SO over time. During the detection process, the switching transistor T0 is kept on, and therefore, the gate voltage Vg of the driving transistor N0 is kept as the data signal (data voltage) Vdata. The inventor of the present disclosure noted that after the data signal Vdata is applied, in the process of discharging the detection circuit through the sensing line or charging the capacitance or parasitic capacitance set on the sensing line, the storage capacitor Cst, etc., is charged with time Increases, the charging speed will correspondingly decrease (that is, the speed at which the sensing voltage increases will decrease) (see Figure 1D), because the charging current will increase with the source voltage (that is, the source voltage Vs of the driving transistor N0 ) Increases and decreases. Specifically, the output current Ids when the driving transistor N0 is in a saturated state can be obtained by the following calculation formula:

Ids=K(Vg-Vs-Vth) ²

＝K(Vdata-Vs-Vth) ²

=K((Vdata-Vth)-Vs) ² .

Here, K=1/2×W/L×C×μ, W is the width of the channel of the driving transistor N0, L is the length of the channel of the driving transistor N0, and W/L is the width of the channel of the driving transistor N0 Length ratio (that is, the ratio of width to length), μ is the electron mobility, and C is the capacitance per unit area.

In the process that the source voltage Vs of the driving transistor N0 increases to Vdata-Vth, as Vs increases, the value of [(Vdata-Vth)-Vs] will continue to decrease; correspondingly, the current Ids output by the driving transistor N0 And the charging speed will continue to decrease accordingly. Therefore, the time Ts required from the start of charging to the turn-off of the driving transistor N0 is longer.

The inventors of the present disclosure have also noticed in their research that during a period of time before the driving transistor N0 is turned off, the amount of change in the voltage Vs of the source of the driving transistor N0 is small. Therefore, it can also be based on The voltage Vbp obtained by the source of the driving transistor N0 can obtain the threshold voltage of the driving transistor N0 (that is, Vth=Vdata-Vbp), and the threshold voltage of the driving transistor N0 obtained at this time is more accurate; thus, the threshold detection time can be shortened In some examples, the detection of the threshold voltage of the driving transistor N0 can also be implemented during the startup period (for example, between adjacent display periods in the display process).

2A is a schematic diagram of a display panel 500, and FIG. 2B is a curve of the voltage of the source of the driving transistor of the display panel 500 shown in FIG. 2A changing with time. The inventor of the present disclosure has also noticed in research that the display panel 500 shown in FIG. 2A can be used to improve the accuracy of the threshold voltage of the driving transistor N0 obtained by sensing. An exemplary description will be given below in conjunction with FIG. 2A and FIG. 2B.

As shown in FIG. 2A, the display panel 500 includes a plurality of pixel unit groups 510 arranged in parallel, a plurality of one-to-N selection circuits 530 arranged in parallel, a plurality of sensing line groups 520 arranged in parallel, and a plurality of parallel arranged sensing line groups 520. Signal conversion circuit 550. For example, a plurality of pixel unit groups 510, a plurality of one-N selection circuits 530, a plurality of sensing line groups 520, and a plurality of signal conversion circuits 550 are respectively arranged in parallel in the first direction D1. For example, the numbers of the pixel unit groups 510, the one-to-N selection circuits 530, the sensing line groups 520, and the signal conversion circuits 550 are equal to each other (for example, all equal to M).

For example, multiple pixel unit groups 510 are located in the display area 501 of the display panel 500, multiple N-to-one selection circuits 530 and multiple signal conversion circuits 550 are located in the peripheral area of the display panel 500, and multiple sensing line groups 520 are respectively displayed from the display The display area 501 of the panel 500 extends to the peripheral area of the display panel 500; the peripheral area of the display panel 500 is arranged around the display area 501 of the display panel 500, and a plurality of one-N selection circuits 530 and a plurality of signal conversion circuits 550 are, for example, located in the display panel One side of the display area 501 of 500 (the same side, for example, the lower side).

For example, as shown in FIG. 2A, each pixel unit group 510 includes a plurality of pixel circuits 511 arranged in an array. For example, each pixel unit group 510 includes N columns of pixel circuits 511 that are sequentially adjacent (sequentially adjacent in the first direction D1). For example, each sensing line group 520 includes N sequentially adjacent sensing lines 521, and the sensing signal output terminals of the N columns of pixel circuits 511 are respectively connected to the N sensing lines 521.

For example, as shown in FIG. 2A, each N-select-one selection circuit 530 includes N sequentially adjacent selection transistors (T_1, T_2, ... T_N-1, and T_N), and the N selection transistors are aligned in the first direction D1. The N selection transistors are also arranged sequentially in a second direction D2 that crosses the first direction D1, the first direction D1 is, for example, perpendicular to the second direction D2.

For example, as shown in FIG. 2A, the input terminals of the N selection transistors are respectively configured as the N signal input terminals of the N-to-one selection circuit 530, and are respectively connected to the corresponding N sensing lines 521; The output terminals are all connected to the signal output terminal of the one-N selection circuit 530. The signal output terminal of the one-N selection circuit 530 is connected to a corresponding signal conversion circuit 550; the control terminals of the N selection transistors are configured to receive N selections. The sub-signal is connected to the signal output terminal of the N-to-one selection circuit 530 by sequentially turning on the N selection transistors and sequentially selecting one of the N signal input terminals of the N-to-one selection circuit 530. For example, the one-to-N selection circuit 530 has only one signal output terminal.

For example, the control terminals of the transistors in the same position in the multiple N one-to-one selection circuits 530 are connected to the same selection control line 151, thereby simplifying the wiring of the display panel 500. It should be noted that the transistors located in the same position in the multiple N-one-selection selection circuits 530 refer to the transistors in the multiple-N-one-one selection circuit 530 that have the same ordering (ordering in the first direction D1) with each other, and these transistors are not required. The positions of the transistors relative to the one-to-N selection circuit 530 where they are located are strictly the same; for example, the transistors ranked as X in the multiple-N-to-one selection circuits 530 are transistors with the same position, where X is greater than or equal to 1 and less than or equal to N Integer between.

For example, each signal conversion circuit 550 is configured to convert an analog signal it receives into a digital signal; for example, each signal conversion circuit 550 may be implemented as an analog-to-digital conversion circuit.

For example, when each row of pixel circuits 511 in the display area 501 is scanned, each N one-to-one selection circuit 530 may be along the positive direction of the first direction D1 (for example, the direction from left to right in FIG. 2A) such that each N The N selection transistors of the selection circuit 530 are turned on sequentially, so that a corresponding signal conversion circuit 550 can sequentially receive the output of the sensing signal output terminals of the N pixel circuits 511 adjacent to each other in the first direction D1 The above N sensing signals are used to obtain the threshold voltages of the N pixel circuits 511.

As shown in FIG. 2A, in the first direction D1, the X-th selection transistor in each N-to-one selection circuit 530 is in the conductive state and the X-th one in the adjacent N-to-one selection circuit 530 is in the conductive state. The number of transistors between the selection transistors is equal to N-1, that is, the X-th selected sensing line 521 in each sensing line group 520 and the X-th selected sensing line in the adjacent sensing line group 520 are The number of the sensing lines 521 between the selected sensing lines 521 is equal to N-1, and the X-th (or column) of each pixel unit group 510 is selected to output the sensing signal of the pixel circuit 511 and adjacent pixels The number of pixel circuits 511 (or the number of columns) between the pixel circuits 511 selected to output the sensing signal in the Xth (or column) of the unit group 510 is equal to N-1. For example, the transistor between the X-th in the on-state selection transistor in each N-to-one selection circuit 530 and the X-th in the on-state selection transistor in the adjacent N-to-one selection circuit 530 refers to the transistor located at each Between the column where the X-th selection transistor in the on-state of the N-to-one selection circuit 530 is located and the column where the X-th selection transistor in the adjacent N-to-one selection circuit 530 is located Transistor.

For example, by connecting N sensing lines 521 to the same signal conversion circuit 550, each signal conversion circuit 550 can be used to output the sensing signal output terminals of N sequentially adjacent pixel circuits 511 in the display area 501. The measured signal is converted into a digital signal; in this case, the number of signal conversion circuits 550 can be reduced, thereby reducing the cost of the display panel, especially for display panels that use signal conversion circuits with higher detection accuracy and higher prices. Say.

For example, in the case where the threshold voltages of the N pixel circuits 511 in each pixel unit group 510 are the same as each other, the data voltages received by the N pixel circuits 511 are the same as each other, and the setting voltages received by the N pixel circuits 511 are the same as each other, N The change curves of the sensing signal output by the pixel circuit 511 are all the same (for example, all are the curves shown in FIG. 2B); as shown in FIG. 2B, the change curve of the sensing signal includes the reset stage REST and the threshold establishment stage TH_B (that is, , The sensing signal increases continuously) and the threshold reading stage TH_R. The threshold reading stage TH_R is temporally located after the Vth establishment stage (the sensing signal is increased enough) and before the driving transistor of the pixel circuit 511 is turned off. In this case, the pixel circuit 511 charges the capacitor (for example, the capacitor on the sensing line) sufficiently, and the value of the sensing signal is close to but not equal to the value of the sensing signal when the driving transistor is turned off.

For example, in the positive direction of each N-to-one selection circuit 530 along the first direction D1 (for example, the direction from left to right in FIG. 2A), the N selection transistors of each N-to-one selection circuit 530 are sequentially turned on. In this case, the sensing voltage output by the N pixel circuits 511 sequentially received by a corresponding signal conversion circuit 550 is the sensing signal S_1 output by the first pixel circuit 511 in each pixel unit group 510, which is located in each pixel unit. The sensing signal S_2 output by the second pixel circuit 511 in the group 510,..., the sensing signal S_N-1 output by the N-1th pixel circuit 511 in each pixel unit group 510 and the sensing signal S_N-1 output by the pixel circuit 511 in each pixel unit group The sensing signal S_N output by the Nth pixel circuit 511 in 510 (see FIG. 2B), so that the sensing signal obtained by the signal conversion circuit 550 is located in the sensing signal of the first pixel circuit 511 in each pixel unit group 510 The difference between the system error of the sensing signal and the system error of the sensing signal of the Nth pixel circuit 511 is the largest. Therefore, the systematic error of the sensing signal of the Nth pixel circuit 511 in each pixel unit group 510 and the phase The difference in the systematic error of the sensing signal of the first pixel circuit 511 in the adjacent pixel unit group 510 is the largest, and thus makes the compensation phase for the adjacent pixel circuit 511 in the adjacent pixel unit group 510 (for example , The difference between the system error of the threshold voltage after the compensation of the Nth pixel circuit 511 in each pixel unit group 510 and the first pixel circuit 511 in the adjacent pixel unit group 510 is relatively large. For example, in the case where the gray scales of the respective image sub-pixels of the image to be displayed are the same as each other, the brightness (for example, the intensity of emitted light) of the light-emitting elements driven by the adjacent pixel circuits 511 in the adjacent pixel unit group 510 is different It is larger, so that the user may observe the above-mentioned brightness difference.

At least one embodiment of the present disclosure provides a display panel, a signal reading method thereof, and a display device. The display panel includes: a first pixel unit group, a second pixel unit group, a first N out of one selection circuit, and a second N select one selection circuit, first sensing line group and second sensing line group. The first pixel unit group and the second pixel unit group are arranged adjacent to each other; the first pixel unit group includes N sequentially adjacent first pixel circuits, and the first sensing line group includes sequentially adjacent N first sensing lines , The sensing signal output ends of the N first pixel circuits are electrically connected to the N first sensing lines; the second pixel unit group includes N sequentially adjacent second pixel circuits, and the second sensing line group includes sequentially N adjacent second sensing lines, the sensing signal output terminals of the N second pixel circuits are respectively electrically connected to the N second sensing lines; the first N one-N selection circuit includes a first control terminal, a first A signal output terminal and N first signal input terminals. The first control terminal is used to receive a selection signal to sequentially select one of the N first signal input terminals to connect to the first signal output terminal; the second N one-to-N selection circuit includes A second control terminal, a second signal output terminal and N second signal input terminals, the second control terminal is used for receiving a selection signal to sequentially select one of the N second signal input terminals to be connected to the second signal output terminal; N The first signal input terminals are electrically connected to the N first sensing lines, and the N second signal input terminals are electrically connected to the N second sensing lines. The first signal input terminal is connected to the last selected first signal input terminal. The total number of part of the first sensing line and part of the second sensing line provided between the first sensing line and the second sensing line connected to the first selected second signal input terminal is greater than or equal to 1, and N is greater than An integer equal to 2.

In some examples, a part of the first sensing line is provided between the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected first. The total number of measuring lines and part of the second sensing lines is less than or equal to N-1.

For example, the display panel, the signal reading method thereof, and the display device provided by at least one embodiment of the present disclosure can reduce the maximum value of the difference in the system error of the luminance of the light-emitting elements driven by adjacent pixel circuits.

FIG. 3A is a schematic diagram of a display panel provided by at least one embodiment of the present disclosure. As shown in FIG. 3A, the display panel includes: a first pixel unit group 111, a second pixel unit group 112, a first one-N-one selection circuit 130, a second one-N-one selection circuit 140, and a first sensing line group 121 And the second sensing line group 122. As shown in FIG. 3A, according to actual application requirements, the display panel may further include a first signal conversion circuit 152 and a second signal conversion circuit 153; here, N is an integer greater than or equal to 2.

For example, as shown in FIG. 3A, the display panel includes a display area 101 and a peripheral area (not shown in the figure) arranged around the display area 101 of the display panel. The first pixel unit group 111 and the second pixel unit group 112 are located in the display area 101. ; The first N-to-one selection circuit 130, the second N-to-one selection circuit 140, the first signal conversion circuit 152 and the second signal conversion circuit 153 are located in the peripheral area; the first sensing line group 121 and the second sensing line group 122 respectively extend from the display area 101 of the display panel to the peripheral area of the display panel. For example, the first N one-N selection circuit 130, the second N one-N selection circuit 140, the first signal conversion circuit 152, and the second signal conversion circuit 153 may be located on one side (the same side, for example, the lower side) of the display area 101 . It should be noted that the display panel may not be provided with the first signal conversion circuit 152 and the first signal conversion circuit 152. In this case, the first signal conversion circuit 152 and the second signal conversion circuit 153 outside the display panel can be It is determined to be electrically connected (for example, directly connected) to the first one-N-one-N selection circuit 130 and the second one-N-one selection circuit 140 respectively.

For example, as shown in FIG. 3A, the first pixel unit group 111 and the second pixel unit group 112 (for example, the first pixel unit group 111 and the second pixel unit group 112 located on the leftmost side of FIG. 3A) are adjacently arranged. It should be noted that the adjacent arrangement of the first pixel unit group 111 and the second pixel unit group 112 means that the first pixel unit group 111 and the second pixel unit are not provided with other pixel unit groups or pixel units (effective pixel unit groups or Effective pixel unit), other "adjacent settings" in the present disclosure also have similar meanings, and will not be repeated here. For example, as shown in FIG. 3A, the first one-N-one selection circuit 130 and the second one-N-one selection circuit 140 are arranged adjacently; the first sensing line group 121 and the second sensing line group 122 are arranged adjacently; The signal conversion circuit 152 and the second signal conversion circuit 153 are arranged adjacently.

For example, the first pixel unit group 111, the first N one-N selection circuit 130, and the first signal conversion circuit 152 are sequentially arranged in the second direction D2 crossing the first direction D1, and the second pixel unit group 112, the second The one-N selection circuit 140 and the second signal conversion circuit 153 are sequentially arranged in the second direction D2. For example, the first direction D1 may be the row direction of the display panel or the extension direction of the gate lines of the display panel, and the second direction D2 may be the column direction of the display panel or the extension direction of the data lines of the display panel. For example, the first direction D1 is perpendicular to the second direction D1.

For example, as shown in FIG. 3A, the display panel may include a plurality of first pixel unit groups 111 and a plurality of second pixel unit groups 112, and the plurality of first pixel unit groups 111 and the plurality of second pixel unit groups 112 may be Alternately arranged in the first direction D1 (that is, the parallel arrangement direction of the plurality of first pixel unit groups 111 and the plurality of second pixel unit groups 112), that is, two adjacent (for example, any adjacent) A second pixel unit group 112 is arranged between the first pixel unit groups 111, and two adjacent (for example, arbitrarily adjacent) second pixel unit groups 112 are provided with a first pixel unit group 111. Correspondingly, the display panel may include a plurality of first-N one-N selection circuits 130, a plurality of second one-N selection circuits 140, a plurality of first sensing line groups 121, a plurality of second sensing line groups 122, A first signal conversion circuit 152 and a plurality of second signal conversion circuits 153; a plurality of first N one-N selection circuits 130 and a plurality of second N one-N selection circuits 140 may be alternately arranged in the first direction D1; more A first sensing line group 121 and a plurality of second sensing line groups 122 may be arranged alternately in the first direction D1; a plurality of first signal conversion circuits 152 and a plurality of second signal conversion circuits 153 may be arranged in the first direction D1. Alternately arranged in the direction D1.

For example, as shown in FIG. 3A, the number of the plurality of first pixel unit groups 111, the number of the first N one-N selection circuits 130, the number of the first sensing line groups 121, and the plurality of first signal conversions The number of circuits 152 is equal to each other (for example, all are equal to M, and M is an integer greater than or equal to 2); the number of second pixel unit groups 112, the number of second-N-one selection circuits 140, and the number of The number of the two sensing line groups 122 and the number of the plurality of second signal conversion circuits 153 are equal to each other (for example, both are equal to M).

For clarity, the following is directed to the first pixel unit group 111, the second pixel unit group 112, the first one-N-one selection circuit 130, and the second one-N-one selection circuit 140 located on the leftmost side of the display panel shown in FIG. 3A. , The first sensing line group 121, the second sensing line group 122, the first signal conversion circuit 152, and the second signal conversion circuit 153 are described, the other first pixel unit group 111 and the second pixel unit group in the display panel 112. The first N one-N selection circuit 130, the second N one-N selection circuit 140, the first sensing line group 121, the second sensing line group 122, the first signal conversion circuit 152, and the second signal conversion circuit 153 are both You can refer to the following description to set up, and other related designs can also be used, which will not be repeated.

As shown in FIG. 3A, the first pixel unit group 111 includes N columns of first pixel circuits 113 adjacent to each other in sequence, and the first sensing line group 121 includes N first sensing lines 123 adjacent to each other in sequence. The sensing signal output terminals of the pixel circuit 113 are respectively electrically connected (for example, directly connected) to the N first sensing lines 123, so that the sensing signal of each column of the first pixel circuit 113 can be provided to the corresponding A first sensing line 123. As shown in FIG. 3A, the second pixel unit group 112 includes N successively adjacent second pixel circuits 114, the second sensing line group 122 includes successively adjacent N second sensing lines 124, and N second The sensing signal output terminals of the pixel circuit 114 are respectively electrically connected (for example, directly connected) to the N second sensing lines 124, so that the sensing signal of the second pixel circuit 114 of each column can be provided to the corresponding One second sensing line 124. For example, when the pixel circuit (first pixel circuit 113 and second pixel circuit 114) in the display area is selected, the selected pixel in each column of pixel circuit (first pixel circuit 113 or second pixel circuit 114) The sensing signal output by the circuit (the pixel circuit located in the Jth row) can be provided to the corresponding sensing line. For example, J is greater than or equal to 1 and less than or equal to the number of rows of pixel circuits in the display area.

For example, as shown in FIG. 3A, N columns of first pixel circuits 113 are sequentially adjacent in the first direction D1, N first sensing lines 123 are sequentially adjacent in the first direction D1, and N columns of second pixel circuits 114 They are adjacent to each other in the first direction D1, and the N second sensing lines 124 are adjacent to each other in the first direction D1. It should be noted that, that the N first sensing lines 123 are sequentially adjacent in the first direction D1 means that the N first sensing lines 123 are sequentially arranged in the first direction D1, and the adjacent first sensing lines No other sensing lines (effective sensing lines) are set between 123, and other "sequentially adjacent" in the present disclosure also have similar meanings, and will not be repeated.

It should be noted that, for clarity, the number of first pixels in each column of the first pixel circuit 113 and the number of second pixel circuits 114 in each column of the second pixel circuit 114 are both two, but the present disclosure The embodiment is not limited to this. According to actual application requirements, the number of first pixels in each column of first pixel circuits 113 and the number of second pixel circuits 114 in each column of second pixel circuits 114 may also be 540, 1080, 2160, or Other applicable numbers.

FIG. 3B is an example of the first pixel circuit and the second pixel circuit provided by at least one embodiment of the present disclosure. For example, each pixel circuit shown in FIG. 3A (for example, each first pixel circuit 113 in the first pixel circuit 113 of N columns and each second pixel circuit 114 in the second pixel circuit 114 of N columns) may adopt a diagram. The 3T1C pixel circuit shown in 3B, but the embodiments of the present disclosure are not limited to this. According to actual application requirements, each pixel circuit shown in FIG. 3A may also adopt the pixel circuit shown in FIG. 1A and the pixel circuit shown in FIG. 1B. Or other applicable pixel circuits. For ease of description, FIG. 3B also shows the first power supply voltage terminal VDD, the second power supply voltage terminal VSS, the sensing line SENL, the data line DL and the light emitting element EL related to the pixel circuit.

For example, as shown in FIG. 3B, each pixel circuit may include a driving transistor T3, a sensing switch transistor T2 (its control terminal is G2), a gate transistor T1 (its control terminal is G1), and a storage capacitor Cst; driving transistor T3 The second pole and the first pole of the light emitting element EL are respectively connected to the first power supply voltage terminal VDD and the first pole of the light emitting element EL; the second pole of the light emitting element EL is connected to the second power supply voltage terminal VSS; the sensing switch transistor T2 The first electrode of the transistor T3 is electrically connected to the first electrode of the driving transistor T3; the first electrode of the sensing switch transistor T2 is electrically connected to the sensing line SENL (for example, the first sensing line 123 or the second sensing line 124) (for example , Directly connected). The sensing line SENL has a parasitic capacitance Csc or an additional capacitance is provided on the sensing line SENL. For example, the voltage value of the first power supply voltage terminal VDD is higher than the voltage value of the second power supply voltage terminal VSS.

For example, the second poles of the sensing switch transistors T2 of the N first pixel circuits 113 (that is, the sensing signal output end of the first pixel circuit 113) are electrically connected to the N first sensing lines 123, respectively; The second pole of the sensing switch transistor T2 of the second pixel circuit 114 (that is, the sensing signal output terminal of the second pixel circuit 114) is electrically connected to the N second sensing lines 124, respectively. For example, the second poles of the sensing switch transistors T2 of the N first pixel circuits 113 are directly connected to the N first sensing lines 123, and the second poles of the sensing switch transistors T2 of the N second pixel circuits 114 are respectively It is directly connected to N second sensing lines 124.

For example, as shown in FIG. 3B, the first electrode of the gate transistor T1 is connected to a data driving circuit (not shown in the figure) via a data line DL to obtain a data signal from the data driving circuit; the second electrode of the gate transistor T1 Connected to the gate of the driving transistor T3 and the first end of the storage capacitor Cst to write the acquired data signal into the gate of the driving transistor T3 and the first end of the storage capacitor Cst; the second end of the storage capacitor Cst is connected to the driving The first pole of the transistor T3 is connected to the first pole of the sensing switch transistor T2 and is configured to store a data signal.

3C is a schematic diagram of a first one-N-to-N selection circuit 130 provided by at least one embodiment of the present disclosure, and FIG. 3D is a schematic diagram of a second one-to-N selection circuit 140 provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 3A, the first N one-N selection circuit 130 includes a first control terminal 131, a first signal output terminal 132, and N first signal input terminals 133 (for example, 133_1, 133_2, ... 133_N-1 And 133_N), the first control terminal 131 is used to receive a selection signal to sequentially select one of the N first signal input terminals 133 to be connected to the first signal output terminal 132; as shown in FIG. 3B, the second N-one selection circuit 140 includes a second control terminal 141, a second signal output terminal 142, and N second signal input terminals 143 (for example, 143_1, 143_2, ... 143_N-1 and 143_N). The second control terminal 141 is used to receive a selection signal to One of the N second signal input terminals 143 is sequentially selected to be connected to the second signal output terminal 142; as shown in FIG. 3A, the N first signal input terminals 133 are respectively connected to the N first sensing lines 123, and N The second signal input terminals 143 are respectively connected with N second sensing lines 124. For example, the selection signal received by the first control terminal 131 and the selection signal received by the second control terminal 141 are the same selection signal.

For example, the first signal input terminal 133, the first sensing line 123, and the first pixel circuit 113 that are electrically connected to each other have the same position number; the second signal input terminal 143, the second sensing line 124, and the first pixel circuit are electrically connected to each other. The two pixel circuits 114 have the same position number. For example, the first signal input terminal 133 with the position number X in the first direction D1 in the first one-N selection circuit 130, the first signal input terminal 133 with the position number X in the first direction D1 in the first sensing line group 121 The sensing line 123 and the first pixel circuit 113 whose position number is X in the first direction D1 in the first pixel unit group 111 are electrically connected to each other.

For example, the specific implementations of the first N one-N selection circuit 130 and the second N one-N selection circuit 140 can be selected according to actual application requirements; for clarity, the first N one-N selection circuit 130 and the second N one-N selection circuit A specific example of the circuit 140 will be described in the example shown in FIGS. 4A and 5.

It should be noted that "sequential selection" refers to selection in a predetermined order. For example, sequentially selecting one of the N first signal input terminals 133 to be connected to the first signal output terminal 132 may mean that the N first signal input terminals 133 are arranged in sequence according to the order of the positions of the N first signal input terminals 133. Is connected to the first signal output terminal 132; sequentially selecting one of the N second signal input terminals 143 to be connected to the second signal output terminal 142 may mean that the N second signal input terminals 143 are arranged in an order such that the Nth The two signal input terminals 143 are sequentially connected to the second signal output terminal 142; for example, the N first signal input terminals 133 are sequentially connected to the first signal output terminal 132 according to the position arrangement sequence and the N second signal input terminals The sequence of the positions in which the 143 is sequentially connected to the second signal output terminal 142 may be reversed.

In an example, as shown in FIG. 3A, FIG. 3C, and FIG. 3D, the first N one-N selection circuit 130 may be sequentially arranged along the positive direction of the first direction D1 (for example, along the left-to-right direction) The first first signal input terminal 133_1, the second first signal input terminal 133_2,..., the N-1th first signal input terminal 133_N-1 and the Nth first signal input terminal 133_N are sequentially connected with The first signal output terminal 132 is electrically connected; correspondingly, the Nth in the second N one-to-one selection circuit 140 arranged in the opposite direction of the first direction D1 (for example, along the right to left direction) sequentially arranged The second signal input terminal 143_N, the N-1th second signal input terminal 143_N-1,..., the second second signal input terminal 143_2, and the first second signal input terminal 143_1 are sequentially connected to the second signal output terminal 142 connections. In this case, between the first sensing line 123 connected to the X-th selected first signal input terminal 133 and the second sensing line 124 connected to the X-th selected second signal input terminal 143 The total number of the part of the first sensing line 123 and the part of the second sensing line 124 arranged in between is equal to 2×(NX), that is, the first pixel that is electrically connected to the X-th selected first signal input terminal 133 The total number of the part of the first pixel circuit 113 and the part of the second pixel circuit 114 provided between the circuit 113 and the second pixel circuit 114 electrically connected to the X-th selected second signal input terminal 143 is equal to 2×(NX), Here, X is greater than or equal to 1 and less than or equal to N; for example, between the first sensing line 123 connected to the X-th selected first signal input terminal 133 and the X-th selected second signal input terminal 143 The number (NX) of the first sensing lines 123 provided between the connected second sensing lines 124 is equal to the first sensing line 123 connected to the X-th selected first signal input terminal 133 and the The number (NX) of the second sensing lines 124 provided between the second sensing lines 124 connected to the X selected second signal input terminals 143. For example, a portion of the first sensing line 123 connected to the first signal input terminal 133 selected last and the second sensing line 124 connected to the second signal input terminal 143 selected last The total number of the measuring line 123 and part of the second sensing line 124 is equal to zero.

In another example, as shown in FIG. 3A, FIG. 3C, and FIG. 3D, the first N one-N selection circuit 130 may be arranged in order along the opposite direction of the first direction D1 (for example, in the right-to-left direction). The Nth first signal input terminal 133_N, the N-1th first signal input terminal 133_N-1,..., the second first signal input terminal 133_2 and the first first signal input terminal 133_1 in sequence It is electrically connected to the first signal output terminal 132; correspondingly, the first one in the second N one-to-one selection circuit 140 that is sequentially arranged along the positive direction of the first direction D1 (for example, along the left-to-right direction) The second signal input terminal 143_1, the second second signal input terminal 143_2,..., the N-1th second signal input terminal 143_N-1, and the Nth second signal input terminal 143_N sequentially output the second signal端142 is connected. In this case, between the first sensing line 123 connected to the X-th selected first signal input terminal 133 and the second sensing line 124 connected to the X-th selected second signal input terminal 143 The total number of the part of the first sensing line 123 and the part of the second sensing line 124 arranged in between is equal to 2×(X-1), that is, at the first signal input terminal 133 electrically connected to the Xth selected first signal input terminal 133 The total number of part of the first pixel circuit 113 and part of the second pixel circuit 114 provided between a pixel circuit 113 and the second pixel circuit 114 electrically connected to the X-th selected second signal input terminal 143 is equal to 2×(X -1), where X is greater than or equal to 1 and less than or equal to N. For example, it is provided between the first sensing line 123 connected to the Xth selected first signal input terminal 133 and the second sensing line 124 connected to the Xth selected second signal input terminal 143 The number of first sensing lines 123 (X-1) is equal to the first sensing line 123 connected to the X-th selected first signal input terminal 133 and the X-th selected second signal input terminal The number (X-1) of the second sensing lines 124 arranged between the second sensing lines 124 connected by 143. For example, a portion of the first sensing line 123 connected to the first signal input terminal 133 selected last and the second sensing line 124 connected to the second signal input terminal 143 selected last The total number of the measuring lines 123 and part of the second sensing lines 124 is equal to 2N-2.

It should be noted that “select in sequence” is not limited to the above two examples. According to actual application requirements, other applicable predetermined sequences can also be selected, as long as the first sensor connected to the first signal input terminal 133 selected last The total number of part of the first sensing line 123 and part of the second sensing line 124 provided between the line 123 and the second sensing line 124 connected to the second signal input terminal 143 selected first is greater than or equal to 1 (for example, Greater than or equal to 1 and less than or equal to N-1); in this case, the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last and the one connected to the second signal input terminal 143 selected first The total number of part of the first pixel circuit 113 and part of the second pixel circuit 114 provided between the second pixel circuits 114 is greater than or equal to 1 (for example, greater than or equal to 1 and less than or equal to N-1).

For example, a portion provided between the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last and the second pixel circuit 114 electrically connected to the second signal input terminal 143 selected first The total number of the first pixel circuit 113 and part of the second pixel circuit 114 is greater than or equal to 1 (for example, greater than or equal to 1 and less than or equal to N-1), the first pixel circuit 113 electrically connected to the first signal input terminal 133 selected last, and The second pixel circuit 114 connected to the second signal input terminal 143 that is selected first is not adjacent. In this case, although the first pixel circuit 113 in the first pixel unit group 111 outputs the sensor with the largest systematic error The difference between the system error of the signal and the system error of the sensing signal with the smallest system error output by the second pixel circuit 114 in the second pixel unit, for example, remains unchanged (for example, compared to the example shown in FIG. 2A) , But the first pixel circuit 113 that outputs the sensing signal with the largest system error in the first pixel unit group 111 is not adjacent to the second pixel circuit 114 that outputs the smallest system error in the second pixel unit. The maximum value of the difference in the systematic error of the luminance of the light-emitting elements driven by adjacent pixel circuits is reduced. For example, in the case where the gray scales of the respective image sub-pixels of the image to be displayed are the same as each other, the display panel provided by at least one embodiment of the present disclosure can reduce the driving force of the adjacent first pixel circuit 113 and the second pixel circuit 114. The maximum value of the brightness difference of the light-emitting element.

For example, the first signal conversion circuit 152 and the second signal conversion circuit 153 are respectively analog-to-digital conversion circuits, and are respectively configured to convert received analog signals into digital signals for subsequent processing (for example, calculating each pixel circuit The threshold voltage of the drive transistor). For example, as shown in FIG. 3A, the signal receiving terminal of the first signal conversion circuit 152 is connected to the first signal output terminal 132, and the signal receiving terminal of the second signal conversion circuit 153 is connected to the second signal output terminal 142. For example, when a certain row of pixel circuits in the display area is scanned (selected), the first signal conversion circuit 152 may sequentially receive the N first pixel circuits in the first pixel unit group 111 via the corresponding first sensing line 123 The N first sensing signals output by the sensing signal output terminal of 113, and for example, the corresponding first digital signals are sequentially converted into the received N first sensing signals; the second signal conversion circuit 153 may be connected to The second sensing line 124 of the second pixel unit group 112 sequentially receives the N second sensing signals output by the sensing signal output ends of the N second pixel circuits 114, and for example, sequentially combines the received N second sensing signals The corresponding second digital signal converted from the second sensing signal.

For example, according to actual application requirements, a detection circuit (not shown in the figure) can be provided between each sensing line and the signal conversion circuit, that is, one end of the detection circuit is connected to the sensing line, and the other end is connected to the signal conversion circuit. Connected; the detection circuit can obtain the voltage (analog signal) on the sensing line at a specific moment based on the sampling signal, and provide the obtained analog signal to the signal conversion circuit. For example, according to actual application requirements, the output terminal of the detection circuit is also connected to an amplifier circuit, and the analog signal output by the detection circuit is amplified before being provided to the signal conversion circuit. For example, the two ends of the detection circuit can be respectively connected between the sensing line and the one-N selection circuit, or can be connected with the one-N selection circuit and the signal conversion circuit respectively.

For example, the display panel may further include a signal adjustment circuit 154. For example, the sequence of the positions in which the N first signal input terminals 133 are connected to the first signal output terminal 132 in sequence and the positions in which the N second signal input terminals 143 are connected to the second signal output terminal 142 in sequence When the arrangement order is reversed, the signal adjustment circuit is configured to reverse the signal output from the second signal conversion circuit or the signal output from the first signal conversion circuit in time. For example, the signal adjustment circuit 154 may be implemented based on FPGA (Field Programmable Gate Array) or other programmable circuits used. For example, by providing the signal adjustment circuit 154, the difficulty of at least one of subsequent signal processing, signal storage, and signal reading can be simplified.

In one example, the signal adjustment circuit 154 is configured to be connected to the signal output terminal of the second signal conversion circuit 153, and is configured to reverse the time sequence of the signal (digital signal) received by the second signal conversion circuit 153, so that The temporal sequence of the N second sensing signals output by the signal adjustment circuit 154 is consistent with the sequence of the corresponding N second pixel circuits 114. For example, the second signal conversion circuit 153 may convert signals in the following first arrangement order in terms of time into signals in the following second arrangement order. Here, the first arrangement order means: along the first direction D1 The Nth second pixel circuit 114, the N-1th second pixel circuit 114, ..., the second second pixel circuit 114, and the second pixel circuit 114 arranged in the reverse direction (for example, in the direction from right to left) sequentially The second sensing signals output by a second pixel circuit 114 are arranged from first to back in time; the second arrangement sequence refers to: along the positive direction of the first direction D1 (for example, along the left to right direction) The first second pixel circuit 114, the second second pixel circuit 114, ..., the second sensing signal output by the N-1th second pixel circuit 114, and the second sensing signal output by the Nth second pixel circuit 114 The N sensing signals are arranged from first to back in time.

In another example, the signal adjustment circuit 154 is configured to be connected to the signal output terminal of the first signal conversion circuit 152, and is configured to reverse the time sequence of the signal (digital signal) received by the first signal conversion circuit 152 to Therefore, the temporal sequence of the N first sensing signals output by the signal adjustment circuit 154 is consistent with the positional sequence of the corresponding N first pixel circuits 113.

It should be noted that in the case that "select in sequence" corresponds to other applicable predetermined sequences, the signal adjustment circuit 154 is further configured to make the first pixel circuit in the first pixel unit group output the first pixel circuits located in the same row. The arrangement sequence of a sensing signal in time is consistent with the arrangement sequence of the plurality of first pixel circuits in the same row in the first pixel unit group in the first direction; the signal adjustment circuit 154 is also configured to make the The temporal arrangement of the second sensing signals output by the plurality of second pixel circuits located in the same row in the two pixel unit group is the same as that of the plurality of second pixel circuits located in the same row in the second pixel unit group. The arrangement order in the first direction is the same.

It should be noted that although FIG. 4A only shows one signal adjustment circuit 154, those skilled in the art will understand that the display panel may also include a plurality of signal adjustment circuits 154. The two signal conversion circuits 153 are respectively electrically connected.

For example, as shown in FIG. 3A, the display panel may further include an arithmetic circuit 155, which is configured to be connected to two of the first signal conversion circuit 152, the second signal conversion circuit 153, and the signal adjustment circuit 154 (for example, Connected to the first signal conversion circuit 152 and the second signal conversion circuit 153 or connected to the first signal conversion circuit 152 and the signal adjustment circuit 154) to receive the first sensing signal and the second sensing signal, and based on the first sensing The sensing signal acquires the threshold voltage of each first pixel circuit 113 in the first pixel unit group 111, and the threshold voltage of each second pixel circuit 114 in the second pixel unit group 112 is acquired based on the second sensing signal. For example, the threshold voltage of each first pixel circuit 113 and the threshold voltage of each second pixel circuit 114 may be used for threshold compensation of each first pixel circuit 113 and each second pixel circuit 114, respectively. For example, the threshold voltage of each first pixel circuit 113 and the threshold voltage of each second pixel circuit 114 may be stored in a memory (not shown in the figure). For example, the memory may include volatile memory and/or non-volatile memory, for example, may include read-only memory (ROM), hard disk, flash memory, etc.

In another example, the memory is configured to store the first sensing signal and the second sensing signal. In this case, the memory and the first signal conversion circuit 152, the second signal conversion circuit 153, and the signal adjustment circuit 154 The two are connected.

For example, in the threshold compensation of each first pixel circuit 113 and each second pixel circuit 114, the controller (for example, a timing controller) is configured to receive the first data signal and threshold voltage of each first pixel circuit 113 and each The second data signal and the threshold voltage of the second pixel circuit 114 are configured to obtain the compensated first data signal based on the first data signal and the threshold voltage of the first pixel circuit 113, based on the second data signal and the second pixel circuit The threshold voltage of 114 obtains the compensated second data signal. The compensated first data signal and the compensated second data signal are configured to be provided to the data driving circuit, and the data driving circuit is configured to transfer the compensated first data signal. A data signal and the compensated second data signal are converted into corresponding analog digital signals, and the corresponding analog digital signals are provided to each of the first pixel circuit 113 and the second pixel circuit 114 of the display panel.

In some examples, the arithmetic circuit 155, the first signal conversion circuit 152, the second signal conversion circuit 153, the signal adjustment circuit 154, the memory, the controller, and the data driving circuit may be integrated in an integrated circuit, for example, the integrated circuit may It is directly arranged on the display panel or electrically connected to the display panel through bonding.

FIG. 4A is a schematic diagram of an example of the display panel shown in FIG. 3A, FIG. 4B shows a schematic diagram of the first N-to-one selection circuit 130 shown in FIG. 4A, and FIG. 4C shows a second N selection circuit shown in FIG. 4B. Choose a schematic diagram of the selection circuit 140.

For example, as shown in FIGS. 4A and 4B, the first control terminal 131 includes N sequentially adjacent first selection signal terminals 134; as shown in FIGS. 4A and 4C, the second control terminal 141 includes N sequentially adjacent The second selection signal terminal 144.

For example, as shown in FIGS. 4A-4C, the display panel further includes N selection control lines 151; the first selection signal terminal 134 corresponding to the Xth selected first signal input terminal 133 and the first selection signal terminal 134 corresponding to the Xth selected first signal input terminal 133; The second selection signal terminal 144 of the selected second signal input terminal 143 is connected to the same selection control line 151. In this case, the selection signal includes N selection sub-signals; the first control terminal 131 corresponding to the X-th selected first signal input terminal 133 and the first control terminal 131 corresponding to the X-th selected second signal input terminal 143 The second control terminal 141 receives the same selector signal.

It should be noted that the embodiment of the present disclosure provides a first selection signal terminal 134 corresponding to the Xth selected first signal input terminal 133 and a second selection signal terminal 134 corresponding to the Xth selected second signal input terminal 143 The selection signal terminal 144 and the same selection control line 151 are not limited to be set to be connected to the same selection control line. According to actual application requirements, the two can also be connected to different selection control lines, as long as it is guaranteed to correspond to the Xth selected control line. The first control terminal 131 of the first signal input terminal 133 and the second control terminal 141 corresponding to the X-th selected second signal input terminal 143 may receive the same selector signal.

For example, as shown in FIGS. 4A-4C, the first N one-N selection circuit 130 includes N sequentially adjacent first selection sub-circuits 135, and the second N one-out selection circuit includes N sequentially adjacent second selection sub-circuits. Sub-circuit 145; each of the N first selection sub-circuits 135 includes a control terminal, a first terminal, and a second terminal, the control terminal of each of the N first selection sub-circuits 135 and N first selection signal terminals 134 The first terminal of each of the N first selection sub-circuits 135 is connected to a corresponding one of the N first signal input terminals 133, and the second terminal of each of the N first selection sub-circuits 135 Terminal is connected to the first signal output terminal 132; each of the N second selection sub-circuits 145 includes a control terminal, a first terminal and a second terminal, and each of the N second selection sub-circuits 145 has a control terminal and N A corresponding one of the second selection signal terminals 144 is connected, the first terminal of each of the N second selection sub-circuits 145 is connected to a corresponding one of the N second signal input terminals 143, and the N second selection sub-circuits 145 The second terminal of each is connected to the second signal output terminal 142.

For example, the first signal input terminal 133 connected to the first end of each of the N first selection sub-circuits 135 has a position number in the first direction D1 and each of the aforementioned N first selection sub-circuits 135 is in the first direction. The position numbers in direction D1 are the same. For example, the position number of the second signal input terminal 143 connected to the first end of each of the N second selection sub-circuits 145 in the first direction D1 is the same as that of each of the N second selection sub-circuits 145 in the first direction. The position numbers on D1 are the same.

For example, as shown in FIG. 4A, the first terminals of the N first selection sub-circuits 135 arranged sequentially from left to right are respectively connected to the first first signal input terminal 133_1 and the second first signal input terminal 133_1 and the second signal input terminal 133_1 shown in FIG. 3C. A signal input terminal 133_2,..., the N-1th first signal input terminal 133_N-1 and the Nth first signal input terminal 133_N are electrically connected; as shown in FIG. 4A, they are arranged sequentially from left to right The first terminals of the N second selection sub-circuits 145 are respectively connected to the first first second signal input terminal 143_1, the second second signal input terminal 143_2, ..., the N-1th shown in FIG. 3D The second signal input terminal 143_N-1 is electrically connected to the Nth second signal input terminal 143_N.

For example, as shown in FIGS. 4A-4C, the first N one-N selection circuit 130 includes N successively adjacent first selection sub-circuits 135 arranged in the second direction D2, and the first N one-N selection circuit 130 It includes N sequentially adjacent first selection sub-circuits 135 arranged in sequence in the first direction D1; the second N-select one selection circuit includes N sequentially adjacent second selection sub-circuits 145 in sequence in the second direction D2 Arrangement; the second N one-out selection circuit includes N sequentially adjacent second selection sub-circuits 145 arranged in sequence in the first direction D1.

For example, as shown in FIGS. 4A to 4C, the first N one-to-one selection circuit 130 includes N sequentially adjacent first selection sub-circuits 135 (from left to right) in the first direction D1 with position numbers Q11 respectively 1, 2, ... X, ... N-1, N; N sequentially adjacent first selection sub-circuits 135 (from top to bottom) included in the first N-to-one selection circuit 130 are in the second direction D1 The position numbers Q12 are 1, 2, ... X, ... N-1, N respectively.

For example, as shown in FIGS. 4A-4C, each of the N sequentially adjacent first selection sub-circuits 135 included in the first N one-to-one selection circuit 130 has a position number Q11 in the first direction D1 and a position number Q11 in the second direction. The position number Q12 on D2 is equal. For example, as shown in FIGS. 4A to 4C, the first N one-to-one selection circuit 130 includes N sequentially adjacent first selection sub-circuits 135 located in the second column (that is, the position number in the first direction D1 The first selector circuit 135 of two) is located in the second row (that is, the position number in the second direction D2 is also two).

For example, as shown in FIGS. 4A-4C, the second N one-to-one selection circuit includes N successively adjacent second selection sub-circuits 145 (from left to right) in the first direction D1, and the position numbers Q21 are 1 respectively. , 2, ... X, ... N-1, N; the second N one-to-one selection circuit includes N successively adjacent second selection sub-circuits 145 (from top to bottom) in the second direction D2 Q21 is 1, 2,...X,...N-1, N.

For example, as shown in FIGS. 4A-4C, each of the N sequentially adjacent second selection sub-circuits 145 included in the second N-one-selection selection circuit has a position number Q21 in the first direction D1 and a position number Q21 in the second direction D2. The upper position sequence number Q22 satisfies the following relationship: Q21+Q22=N+1. For example, as shown in FIGS. 4A to 4C, the first N one-to-one selection circuit 130 includes N sequentially adjacent first selection sub-circuits 135, and the first selection sub-circuit 135 located in the second column is in the first direction D1. The upper position number Q21 is 2, and the upper position number Q22 in the second direction D2 is N-1. In this case, Q21+Q22=N+1.

For example, as shown in FIGS. 4A-4C, N selection control lines 151 are sequentially arranged in the second direction D2. For example, as shown in FIGS. 4A-4C, the first selection sub-circuit 135 and the second selection sub-circuit 145 with the same position number in the second direction D2 are electrically connected to the same selection control line 151, that is, located in the same row The first selection sub-circuit 135 and the second selection sub-circuit 145 are electrically connected to the same selection control line 151. For example, as shown in FIGS. 4A-4C, the position number of the selection control line 151 connected to the first selection sub-circuit 135 in the second direction D2 is the same as the position number of the first selection sub-circuit 1351 in the second direction D2; The position number of the selection control line 151 connected to the second selection sub-circuit 145 in the second direction D2 is the same as the position number of the second selection sub-circuit 145 in the second direction D2.

For example, as shown in FIGS. 4A-4C, the position numbers of the N selection control lines 151 (from top to bottom) in the second direction D2 are 1, 2, ... X, ... N-1, N, respectively.

For example, as shown in FIGS. 4A-4C, the first selection sub-circuit 135 and the second selection sub-circuit 145 connected to the selection control line 151 with the position number X in the second direction D2 are in the first direction D1. Respectively X and N+1-X; correspondingly, the first sensing line connected to the first selection sub-circuit 135 connected to the selection control line 151 with the position number X in the second direction D2 and the The number of part of the first sensing line and the number of part of the second sensing line provided between the second sensing lines connected to the second selection sub-circuit 145 connected to the selection control line 151 with the position number X on D2 are both NX Therefore, the first sensing line connected to the first selection sub-circuit 135 connected to the selection control line 151 with the position number X in the second direction D2 and the selection control line with the position number X in the second direction D2 The total number of part of the first sensing line and part of the second sensing line provided between the second sensing lines connected to the second selection sub-circuit 145 connected to 151 is 2 (NX).

In an example, the N selection control lines 151 are selected sequentially from top to bottom; in this case, the first sensing line connected to the Xth selected first selection sub-circuit 135 and the Xth The total number of part of the first sensing line and part of the second sensing line set between the second sensing lines connected to the second selection sub-circuit 145 is equal to 2×(NX); A portion of the first sensing line 123 and a portion of the second sensing line 123 and a portion of the second sensing line 124 connected to the second sensing line 124 connected to the second selection sub-circuit 145 selected first The total number of survey lines 124 is equal to N-1.

In another example, the N selection control lines 151 are selected sequentially from bottom to top; in this case, the first sensing line connected to the Xth selected first selection sub-circuit 135 and the Xth The total number of part of the first sensing line and part of the second sensing line set between the second sensing lines connected to the selected second selection sub-circuit 145 is equal to 2×(X-1); Part of the first sensing line 123 and part of the first sensing line 123 and part of the first sensing line 123 connected to the first selection sub-circuit 135 and the second sensing line 124 connected to the second selection sub-circuit 145 first selected The total number of the two sensing lines 124 is equal to N-1.

It should be noted that the display panel provided by at least one embodiment of the present disclosure is not limited to adopting the first N out of N selection circuit shown in FIG. 4B. According to actual application requirements, the first N out of N selection circuit shown in FIG. 4D may also be used. Select circuit 1. FIG. 4D shows a schematic diagram of another first one-N-one selection circuit 130 provided by at least one embodiment of the present disclosure.

As shown in FIG. 4D, the first N one-N selection circuit 130 further includes a first decoding circuit 170. The first decoding circuit 170 includes C signal input terminals 171 and N signal output terminals 172. In the case of a binary signal, C=ceil(log2(N)), ceil(log2(N)) means that log2(N)) is rounded down. For example, when N=5-8, C=3; when N=9-16, C=4. In this case, as shown in FIG. 4D, the first control terminal 131 includes C first selection signal terminals 134, and the selection signal includes C selection sub-signals; the C signal input terminals 171 of the first decoding circuit 170 and C The first selection control terminals 134 are connected, and the N signal output terminals 172 of the first decoding circuit 170 are respectively connected to the control terminals of the N selection sub-circuits; the first decoding circuit 170 is configured to enable the first decoding based on the received signal A corresponding signal output terminal 172 of the circuit 170 outputs a valid signal (a signal that turns on the transistor of the first selection sub-circuit 135), and makes the other signal output terminal 172 of the first decoding circuit 170 output an invalid signal (makes the first selection The transistor of the sub-circuit 135 is turned off), so that the first N one-N selection circuit 130 can sequentially select one of the N first signal input terminals 133 to be connected to the first signal output terminal 132. Correspondingly, the second N one-N selection circuit 140 further includes a second decoding circuit (not shown in the figure), and the second decoding circuit includes C signal input terminals and N signal output terminals, which will not be repeated here.

It should be noted that the signal input terminal 171 is not limited to receiving binary signals, but can also be based on M-ary signals (for example, decimal signals or hexadecimal signals). In this case, C=ceil(logM(N)), ceil(logM(N)) means to round down logM(N)).

For example, as shown in FIG. 4A, each selection sub-circuit (for example, each of the N first selection sub-circuits 135 and N second selection sub-circuits 145) may be implemented as a transistor, and the gate of the transistor, the first electrode The and second poles are respectively configured as the control terminal, the first terminal and the second terminal of the selection sub-circuit. It should be noted that each selection sub-circuit is not limited to include one transistor as shown in FIG. 4A. According to actual application requirements, each selection sub-circuit may also include a combination of two or more transistors or may include other suitable circuit structures. For example, the transistors selected by the multiple selector sub-circuits have the same conduction characteristics, and the transistors selected by the multiple selector sub-circuits are, for example, all N-type transistors or all P-type transistors.

For example, as shown in FIG. 4A, the first selection sub-circuit 135 corresponding to the X-th selected first signal input terminal 133 and the second selection sub-circuit 145 corresponding to the X-th selected second signal input terminal 143 are located in The same row; correspondingly, the first control terminal 131 corresponding to the X-th selected first signal input terminal 133 and the first control terminal 131 corresponding to the X-th selected second signal input terminal 143 are located in the same row.

It should be noted that the one-to-N circuit (the first one-to-N circuit and the second one-to-N circuit) are not limited to the example shown in FIG. 4A. The one-to-N circuit can also adopt other applicable circuit structures, which will not be omitted here. Repeat.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable. In the embodiment of the present disclosure, in order to distinguish the gate of the transistor as the control terminal, one pole is directly described as the first terminal and the other pole is the second terminal. Therefore, in the embodiment of the present disclosure, the first terminal of all or part of the transistor is The second end is interchangeable as needed. For example, the first terminal of the transistor of the embodiment of the present disclosure may be a source and the second terminal may be a drain; or, the first terminal of the transistor may be a drain and the second terminal may be a source. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of transistors. The embodiments of the present disclosure do not limit the types of transistors. Those skilled in the art can use N-type and/or P-type transistors to implement the invention according to actual needs. Examples in the disclosure.

At least one embodiment of the present disclosure further provides a signal reading method for the display panel provided by any embodiment of the present disclosure, which includes: sequentially selecting N first signal inputs through a first N one-N selection circuit One of the terminals is connected to the first signal output terminal; one of the N second signal input terminals is sequentially selected to be connected to the second signal output terminal through the second N one-to-one selection circuit.

FIG. 5 is a schematic flowchart of a signal reading method of a display panel provided by at least one embodiment of the present disclosure. The signal reading method includes the following steps S100 and S200.

Step S100: sequentially select one of the N first signal input terminals to be connected to the first signal output terminal through the first N one-N selection circuit.

Step S200: Select one of the N second signal input terminals to be connected to the second signal output terminal in sequence through the second N one-N selection circuit.

For example, a part of the first sensing line is provided between the first sensing line connected to the X-th selected first signal input terminal and the second sensing line connected to the X-th selected second signal input terminal. The total number of measuring lines and part of the second sensing line is equal to 2×(NX) or 2×(X-1); that is, the first pixel circuit electrically connected to the X-th selected first signal input terminal and The total number of part of the first pixel circuit and part of the second pixel circuit provided between the second pixel circuit electrically connected to the X-th selected second signal input terminal is equal to 2×(NX) or 2×(X-1) Here, X is greater than or equal to 1 and less than or equal to N. For example, the signal reading method of the above display panel can be referred to the embodiment of the display panel, which will not be repeated here.

For example, step S100 is performed before the voltages of the first electrodes of the driving transistors of the plurality of first pixels are relatively stable and the driving transistors of the plurality of first pixels are turned off. For example, the ratio of the voltage of the first electrode of the driving transistor of each first pixel to the voltage (source voltage) of the first electrode after the driving transistor of the first pixel is turned off is greater than 90% (for example, greater than 95%, greater than 98%, greater than 99%, or greater than 99.5%).

For example, step S200 is performed before the voltages of the first electrodes of the driving transistors of the plurality of second pixels are relatively stable and the driving transistors of the plurality of second pixels are turned off. For example, the ratio of the voltage of the first electrode of the driving transistor of each second pixel to the voltage of the first electrode (source voltage) after the driving transistor of the second pixel is turned off is greater than 90% (for example, greater than 95%, greater than 98%, greater than 99%, or greater than 99.5%).

FIG. 6 is an exemplary block diagram of a display device 10 provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 6, the display device 10 includes a display panel 100.

For example, FIG. 7 shows a schematic diagram of the display device 10 shown in FIG. 6. For example, as shown in FIG. 7, the display device 10 includes a pixel circuit of a display panel 100, a signal converter ADC, a data line DL, a sensing line SENL, and a control device 120. The display device 10 has a display area and a display area arranged around the display area. Peripheral area; the display area of the display device 10 includes a plurality of pixel units, each pixel unit may include a pixel circuit, the pixel units included in the display device 10 may be arranged in an array, for example, corresponding pixel circuits may be arranged in an array, for example. It should be noted that, for clarity, the display device 10 only shows one pixel circuit, but the embodiments of the present disclosure are not limited thereto.

As shown in FIG. 7, the control device 120 is provided in a peripheral area located outside the display area. For example, the display device 10 may further include a data driving circuit 130, a detection circuit 140, and a scan driving circuit (not shown) that are also provided in the peripheral area.

For example, the pixel circuit may adopt the pixel circuit shown in FIG. 3B, the pixel circuit shown in FIG. 1A, the pixel circuit shown in FIG. 1B or other applicable pixel circuits or other applicable pixel circuits. The specific structure of the pixel circuit is not here. Repeat it again. As shown in FIG. 7, the pixel circuit includes a driving transistor T3, a sensing switch transistor T2 (its control terminal is G2), and a gate transistor T1 (its control terminal is G1). The driving transistor includes a first pole, and the sensing line SENL is electrically connected to the first pole of the driving transistor T3.

For example, the detection circuit 140 is configured to read the first sensing voltage from the sensing line SENL. For example, the detection circuit 140 may be a sampling circuit, the sampling circuit may provide a sampling signal SAMP, and may obtain the first sensing voltage from the first pole of the driving transistor T3 via the sensing switch transistor T2.

The display device 10 further includes, for example, a selection signal generator (not shown in the figure), which is configured to generate a selection signal in response to a control signal of the control device 120.

For example, the control device 120 (e.g., the controller) is configured to perform a control on each pixel circuit of the display panel based on the sensing signal provided by the signal converter ADC or using a threshold signal (threshold voltage) acquired based on the sensing signal acquired by the signal converter ADC. Perform threshold compensation (for example, generate a compensated signal for each pixel circuit of the display panel).

For example, the control device 120 is also configured to control the data driving circuit 130 and the detection circuit 140. For example, the data driving circuit 130 is configured to provide the compensated data voltage at different times according to actual application requirements. The scan driving circuit is used to provide scan signals of the sensing switch transistor T2 and the gate transistor T1 to control the conduction state (for example, on or off) of the sense switch transistor T2 and the gate transistor T1.

It should be noted that, for ease of description, some embodiments of the present disclosure introduce signal input terminals, signal output terminals, etc., but those skilled in the art can understand that signal input terminals, signal output terminals, etc. are paths through which signals are transmitted. It is not required that there is, for example, a pad structure as a signal input terminal, a signal output terminal, etc. in the display panel. In some examples, as shown in FIG. 4A, the signal input terminal, the signal output terminal, etc. can be formed integrally with the sensing line, which will not be repeated.

Although general descriptions and specific implementations have been used above to describe the present disclosure in detail, some modifications or improvements can be made on the basis of the embodiments of the present disclosure, which is obvious to those skilled in the art. Therefore, all these modifications or improvements made without departing from the spirit of the present disclosure fall within the scope of protection claimed by the present disclosure.

The foregoing descriptions are merely exemplary implementations of the present disclosure, and are not used to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims

A display panel includes: a first pixel unit group, a second pixel unit group, a first one-N-to-one selection circuit, a second one-N-to-one selection circuit, a first sensing line group, and a second sensing line group,

Wherein, the first pixel unit group and the second pixel unit group are arranged adjacently;

The first pixel unit group includes N successively adjacent first pixel circuits, the first sensing line group includes successively neighboring N first sensing lines, and the sensing of the N first pixel circuits The measurement signal output terminals are respectively electrically connected to the N first sensing lines;

The second pixel unit group includes N sequentially adjacent second pixel circuits, the second sensing line group includes sequentially adjacent N second sensing lines, and the sensing of the N second pixel circuits The measurement signal output terminals are electrically connected to the N second sensing lines respectively;

The first N one-N selection circuit includes a first control terminal, a first signal output terminal, and N first signal input terminals. The first control terminal is used to receive a selection signal to sequentially select the N first signal input terminals. One of the signal input terminals is connected to the first signal output terminal;

The second N one-N selection circuit includes a second control terminal, a second signal output terminal, and N second signal input terminals, and the second control terminal is used to receive the selection signal to sequentially select the N One of the second signal input terminals is connected to the second signal output terminal;

The N first signal input terminals are respectively electrically connected to the N first sensing lines, and the N second signal input terminals are respectively electrically connected to the N second sensing lines; and

A portion of the first sensing line and the second sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected first The total number of part of the second sensing lines is greater than or equal to 1, and N is an integer greater than or equal to 2.
The display panel of claim 1, wherein the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected last The total number of the part of the first sensing line and the part of the second sensing line set between is equal to 0 or 2N-2.
The display panel according to claim 1 or 2, wherein the first sensing line connected to the Xth selected first signal input terminal and the Xth selected second signal input terminal are connected The total number of part of the first sensing line and part of the second sensing line set between the two sensing lines is equal to 2×(NX) or 2×(X-1), and the X is greater than or equal to 1 and Less than or equal to N.
3. The display panel of claim 3, wherein the first sensing line connected to the X-th selected first signal input terminal and the X-th selected second signal input terminal are connected The number of the first sensing lines set between the second sensing lines is equal to the number of the first sensing lines connected to the Xth selected first signal input terminal and the Xth The number of the second sensing lines set between the second sensing lines connected to the selected second signal input terminal.
The display panel according to any one of claims 1-4, the first sensing line connected to the first signal input terminal selected last and the second sensing line connected to the second signal input terminal selected first The total number of part of the first sensing line and part of the second sensing line arranged between the lines is less than or equal to N-1.
5. The display panel according to any one of claims 1-5, wherein the first control terminal comprises N sequentially adjacent first selection signal terminals; and

The second control terminal includes N sequentially adjacent second selection signal terminals.
The display panel according to claim 6, wherein the selection signal includes N selection sub-signals; and

The first control terminal corresponding to the X-th selected first signal input terminal and the second control terminal corresponding to the X-th selected second signal input terminal receive the same selector signal.
8. The display panel according to claim 7, further comprising N selection control lines, wherein the first selection signal terminal corresponding to the X-th selected first signal input terminal and the first selection signal terminal corresponding to the first signal input terminal The second selection signal terminals of the X selected second signal input terminals are connected to the same selection control line among the N selection control lines.
7. The display panel according to any one of claims 6-8, wherein the first one-N-N selection circuit comprises N sequentially adjacent first selection sub-circuits, and the second one-N-N selection circuit comprises N Two successively adjacent second selector subcircuits;

Each of the N first selection sub-circuits includes a control terminal, a first terminal, and a second terminal, and the control terminal of each of the N first selection sub-circuits corresponds to the N first selection signal terminals Is connected to one of the N first selection sub-circuits, the first end of each of the N first selection sub-circuits is connected to a corresponding one of the N first signal input terminals, and the first end of each of the N first selection sub-circuits The two ends are connected to the first signal output end; and

Each of the N second selection sub-circuits includes a control terminal, a first terminal, and a second terminal, and the control terminal of each of the N second selection sub-circuits corresponds to the N second selection signal terminals Is connected to one of the N second selection sub-circuits, the first end of each of the N second selection sub-circuits is connected to a corresponding one of the N second signal input terminals, and the first end of each of the N second selection sub-circuits The two ends are connected to the second signal output end.
9. The display panel according to any one of claims 1-9, wherein the display panel comprises a plurality of first pixel unit groups, a plurality of second pixel unit groups, a plurality of first one-N selection circuits, and a plurality of Two-N-one selection circuit, multiple first sensing line groups and multiple second sensing line groups;

The plurality of first pixel unit groups and the plurality of second pixel unit groups are alternately arranged in a parallel arrangement direction of the plurality of first pixel unit groups and the plurality of second pixel unit groups;

The plurality of first one-N selection circuits and the plurality of second one-N selection circuits are alternately arranged in the parallel arrangement direction; and

The plurality of first sensing line groups and the plurality of second sensing line groups are alternately arranged in the parallel arrangement direction.
The display panel according to any one of claims 1-10, further comprising a first signal conversion circuit and a second signal conversion circuit, wherein the signal receiving end of the first signal conversion circuit is connected to the first signal output end , The signal receiving end of the second signal conversion circuit is connected to the second signal output end.
11. The display panel of claim 11, wherein the first signal conversion circuit and the second signal conversion circuit are respectively analog-to-digital conversion circuits.
The display panel according to claim 11 or 12, further comprising a signal adjustment circuit, wherein the signal adjustment circuit is configured to convert the signal output by the second signal conversion circuit or the signal output by the first signal conversion circuit in Reverse order in time.
15. The display panel according to any one of claims 1-13, wherein each of the N first pixel circuits and the N second pixel circuits comprises a driving transistor and a sensing switch transistor;

The second electrode and the first electrode of the driving transistor are configured to be respectively connected to the first power supply voltage terminal and the first electrode of the light emitting element;

The second pole of the light-emitting element is connected to the second power supply voltage terminal;

The first pole of the sensing switch transistor is electrically connected to the first pole of the driving transistor;

The second poles of the sensing switch transistors of the N first pixel circuits are electrically connected to the N first sensing lines respectively; and

The second poles of the sensing switch transistors of the N second pixel circuits are electrically connected to the N second sensing lines, respectively.
A display device comprising the display panel according to any one of claims 1-14.
A signal reading method for a display panel according to any one of claims 1-14, comprising:

Sequentially selecting one of the N first signal input terminals to be connected to the first signal output terminal by the first N one-N selection circuit;

One of the N second signal input terminals is sequentially selected to be connected to the second signal output terminal through the second N one-N selection circuit.
16. The signal reading method of the display panel according to claim 16, wherein said one of said N first signal input terminals and said first signal output are sequentially selected by said first N one-N selection circuit Terminal connection and sequentially selecting one of the N second signal input terminals to be connected to the second signal output terminal through the second N one-N selection circuit includes: making the first signal Part of the first sensing line and part of the second sensing line provided between the first sensing line connected to the input terminal and the second sensing line connected to the second signal input terminal selected first The total number of lines is greater than or equal to 1, and N is an integer greater than or equal to 2.