JP2010102266A - Liquid crystal display device and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a structure of an active matrix type liquid crystal display device of an SSD system reducing power consumption due to a switching element for the SSD. <P>SOLUTION: This liquid crystal display device has data signal lines DL11-DLn, scanning signal lines GL1-GLm, a pixel electrode 6, an opposing electrode 11, and a data signal line drive circuit 1. A set of data signal lines DL11, DL12, DL13 corresponding to RGB is connected to an output signal line D1 via a selection switch part 33. The data signal line drive circuit 1 time-divides data signals corresponding to RGB within one horizontal scanning period and outputs them to the output signal line D1. As the data signal lines DL11, DL12, DL13 corresponding to RGB are sequentially selected by the selection switch part 33, the data signal is supplied to each data signal line. Each output signal line D1-Dn/3 is connected to the data signal line drive circuit 31 via a first switch part and connected to each other via a second switch part 32. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a driving system for bundling a plurality of data lines for supplying video signals and connecting them to the output of a data line driving circuit to output video signals in a time-sharing manner. The present invention relates to a liquid crystal display device and a driving method thereof.

  Conventionally, a method called SSD (Source Shared Driving) has been used as one of driving methods of liquid crystal display devices. In a liquid crystal display device, pixels are two-dimensionally arranged in a matrix at intersections of a plurality of scanning signal lines and data signal lines that are orthogonal to each other. In the SSD method, a set of a plurality of data signal lines is divided into a plurality of groups. This is a driving method in which a source signal (data signal) is time-divided and driven by a data output circuit common to the data signal lines.

  FIG. 14 is an equivalent circuit diagram showing a configuration of a conventional liquid crystal display device of an SSD active matrix type. As shown in FIG. 14, the conventional liquid crystal display device includes a data signal line drive circuit (source driver) 101, a scanning signal line drive circuit (gate driver) 102, a switch control unit 103, and a display unit 109. .

  The display unit 109 includes a plurality (m) of scanning signal lines GL1 to GLm and a plurality (n) of data signal lines DL11 to DLn orthogonal to the scanning signal lines GL1 to GLm. A plurality (m × n) of pixel switching elements (transistors; TFTs) 105 and liquid crystal capacitors 106 correspond to the intersections of the scanning signal lines GL1 to GLm and the data signal lines DL11 to DLn, respectively. A pixel forming portion is provided. The pixel forming portions are arranged in a matrix and constitute a pixel array.

  In each pixel formation portion, the pixel switching element 105 has a scanning signal line connected to the gate terminal, a data signal line connected to the source terminal, and a pixel electrode connected to the drain terminal. In addition, a common counter electrode is provided opposite to the pixel electrode in all the pixel formation portions, and the pixel electrode and the counter electrode sandwich a liquid crystal layer between them to form a liquid crystal that constitutes a pixel capacitor. A capacitor 106 is formed.

  A potential corresponding to an image to be displayed is applied to the pixel electrode by the data signal line driving circuit 101 and the scanning signal line driving circuit 102, while a predetermined potential is applied to the common electrode from a counter electrode control unit (not shown). . By applying this voltage, the amount of light transmitted to the liquid crystal layer is controlled to display an image. Note that a polarizing plate (not shown) is used in order to control the amount of transmitted light by applying a voltage to the liquid crystal layer.

  In addition, in the SSD active matrix liquid crystal display device shown in FIG. 14, a plurality of data signal lines DL11 to DLn are bundled by three via the selection switch unit 104, and a data signal is transmitted as a set of three. It is connected to the output signal lines D1 to Dn / 3 of the line drive circuit 101.

  The selection switch unit 104 is connected to the switch control unit 103 by data signal line selection lines GLR, GLG, and GLB. The switch control unit 103 controls on / off of the selection switch unit 104. As a result, the three data signal lines forming the set are sequentially connected to the output signal lines D1 to Dn / 3. For example, the data signal lines DL11, DL12, and DL13 form a set and are connected to the output signal line D1, and are controlled by the switch control unit 103 to turn on / off the selection switch unit 104. , DL13 are sequentially electrically connected to the output signal line D1.

  As described above, in the SSD liquid crystal display device, the three data signal lines (for example, DL11, DL12, and DL13) can be controlled by the switch control unit 103, so that the data signal line driving circuit 101 is configured. There is an advantage that the number of data output circuits (source driver chips) can be reduced to 1/3.

  However, in the SSD type liquid crystal display device, the number of source driver chips can be reduced, but the charge / discharge current per source driver chip increases (in this case, triples). The load capacity increases, and the power consumption and heat generation per chip increase. Further, the selection switch unit 104 requires a high voltage for the on / off switching operation. Thus, the SSD liquid crystal display device has a problem that the power consumption of the entire device increases.

Therefore, for example, Patent Document 1 discloses a method for solving this problem. FIG. 15 is a block diagram illustrating a configuration of the display device disclosed in Patent Document 1. In FIG. As shown in the figure, the display device 100 includes a plurality of switching elements 1241, 1242,..., 1249 connected to the data signal lines at the end (lower side of the paper) of the data signal non-input side. Yes. Each data signal line is short-circuited by turning on this switching element every horizontal scanning period. According to this configuration, the electric charge charged in the load on the data signal line can be averaged for each horizontal scanning period, so that power consumption can be reduced.
JP 2007-114496 A (published on May 10, 2007)

  However, in the configuration of Patent Document 1, charges accumulated in capacitors floating in SSD switching elements (corresponding to a selection switch unit) 1214, 1215,... Cannot be averaged. There is a problem that power consumption cannot be reduced. The reason will be specifically described with reference to FIG.

  Taking the pixel Gmn at the intersection of the DRn line and the GLm line in FIG. 16 as an example, when a signal potential is written to the pixel Gmn, an on-voltage is supplied to the scanning signal line GLm. All the switching elements (transistors) connected to GLm are in the on state. In this state, the SSD switching elements 1216n, 1215n, and 1214n are turned on in a time division order in the order of RGB, and corresponding source signals are supplied from the DRn line. Then, after the transistors connected to the scanning signal line GLm are turned off, the switching elements 1241, 1242,..., 1249 are turned on, and all the data signal lines are short-circuited.

  As described above, in the configuration of Patent Document 1, when the transistor connected to the scanning signal line GLm is in the off state (non-display period), the switching elements 1241, 1242,. Each data signal line is short-circuited. That is, while the transistor connected to the scanning signal line GLm is in the on state, the writing potential to each pixel fluctuates, so that the switching elements 1241, 1242, ..., 1249 cannot be turned on. Therefore, the writing to the next pixel (here, the G pixel) is performed without being able to average the charges accumulated in the capacitors floating in the SSD switching elements 1214, 1215,.

  When the size of the switching element for SSD is small, the influence on the power consumption of the entire display device is small. However, when the size of the switching element is large, the power consumption corresponding to the switching element cannot be ignored. Particularly in recent years, in order to reduce the manufacturing cost of a display device, a technique for integrally forming a drive circuit in a panel using a-Si or uC-Si has been proposed. The size of the switching element used in the case becomes larger. When the size of the switching element is increased, the charge accumulated in the switching element is increased, and the power consumption is increased accordingly. Therefore, in order to apply to fields that require high reliability (high temperature range) and long life, such as in-vehicle instrument panels that are expected to become popular in the future, reduce power consumption due to switching elements for SSDs. Is desired.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to propose a configuration capable of reducing power consumption caused by an SSD switching element, particularly in an SSD active matrix liquid crystal display device. To do.

  A liquid crystal display device according to the present invention includes a plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, a pixel electrode disposed at each intersection of these signal lines, and a counter electrode disposed to face the pixel electrode And a data signal line driving circuit for outputting data signals to the plurality of data signal output lines, wherein the plurality of data signal lines are arranged continuously corresponding to the primary colors constituting the display color. And is connected to the data signal output line for each set via a selective switching element provided for each data signal line, and the data signal line driving circuit corresponds to the primary color. The data signal to be processed is time-divided within one horizontal scanning period and output to each data signal output line. In each group, the data signal line corresponding to the primary color turns on / off the selection switching element. In the liquid crystal display device in which the data signal output from the data signal line driver circuit is supplied to the data signal lines by sequentially selecting the data signal lines, each of the data signal output lines includes a first switching element. And connected to the data signal line driving circuit via the second switching element.

  A driving method of a liquid crystal display device according to the present invention includes a plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, pixel electrodes disposed at intersections of these signal lines, and opposed to the pixel electrodes. And a data signal line driving circuit for outputting data signals to a plurality of data signal output lines, and the plurality of data signal lines are continuously arranged corresponding to the primary colors constituting the display color. A set of data signal lines is configured and connected to the data signal output line for each set via a selection switching element provided for each data signal line. A data signal corresponding to the primary color is time-divided within one horizontal scanning period and is output to each data signal output line. In each set, the data signal line corresponding to the primary color is connected to the selected switching element. In the method of driving a liquid crystal display device in which the data signal output from the data signal line driving circuit is supplied to the data signal line by sequentially selecting the data signal off / off, each of the data signal output lines includes a first A data signal is connected to the data signal line driving circuit via a switching element and connected to each other via a second switching element, and a data signal is transmitted to one data signal line among the plurality of data signal lines constituting the set. The first switching element is turned off and the second switching element is turned on between the time when the first data is supplied and the time when the data signal is supplied to the next data signal line.

  According to the above configuration, the data signal output lines are electrically connected to each other, for example, by turning off the first switching element and turning on the second switching element. As a result, the charge accumulated in the capacitance floating in the selection switching element for selecting the data signal line can be averaged, so that the power consumption caused by the accumulated charge can be reduced. Therefore, particularly in a liquid crystal display device in which a drive circuit is integrally formed in the panel using a-Si or uC-Si, the charge accumulated in the selective switching element increases, so that a greater effect can be achieved with regard to reduction of power consumption. Obtainable.

  In the present liquid crystal display device, after a data signal is supplied to one data signal line among a plurality of data signal lines constituting the above set, a data signal is supplied to the next data signal line. The first switching element may be turned off and the second switching element may be turned on.

  According to the above configuration, the data signal output lines are electrically connected to each other during a period in which no data signal is supplied. Therefore, it is possible to average the charge accumulated in the capacitance floating in the selected switching element without affecting the pixel potential.

  In the liquid crystal display device, the first switching element may be in an off state at least while the second switching element is in an on state.

  Thereby, the supply of the data signal is stopped during a period in which the data signal output lines are electrically connected to each other. Therefore, it is possible to average the charge accumulated in the capacitance floating in the selected switching element without affecting the pixel potential.

  In the present liquid crystal display device, a common electrode potential can be supplied to the data signal output line when the second switching element is in an ON state.

  Thereby, the electric charge accumulated in the capacitance floating in the selective switching element can be reliably recovered.

  In the present liquid crystal display device, a data signal having the same polarity may be continuously supplied to the data signal output line at least once in one horizontal scanning period.

  As a result, the number of times of polarity inversion can be reduced, so that power consumption can be further reduced.

  In the present liquid crystal display device, at the beginning of the period in which the selection switching element is on, the second switching element is on, and the first switching element is at least the second switching element. A configuration in which the common electrode potential is supplied to the data signal output line when the second switching element is in an on state while the second switching element is in an on state may be employed.

  According to the above configuration, each time the primary color (RGB) is switched in a period in which the selection switching element is in an on state in one horizontal scanning period, that is, a period in which a data signal is supplied (writing to a pixel), The pixel potential can be fixed to the common electrode potential (Vcom) before the data signal is written to the pixel. As a result, the charge accumulated in the capacitance floating in the selective switching element can be reliably collected, and the charge accumulated in the load on the data signal line can also be collected. Therefore, the power consumption of the entire liquid crystal display device can be reduced as compared with the conventional one, and the display quality can be improved.

  A liquid crystal display device according to the present invention includes a plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, a pixel electrode disposed at each intersection of these signal lines, and a counter electrode disposed to face the pixel electrode And a data signal line driving circuit for outputting data signals to the plurality of data signal output lines, wherein the plurality of data signal lines are arranged continuously corresponding to the primary colors constituting the display color. Are connected to the data signal output line for each set via individually provided selective switching elements, and the data signal line driving circuit converts the data signal corresponding to the primary color to 1 Within the horizontal scanning period, it is time-divided and output to each data signal output line. In each set, the data signal line corresponding to the primary color is sequentially selected by turning on / off the selection switching element. Therefore, in the liquid crystal display device in which the data signal output from the data signal line driving circuit is supplied to the data signal line, the data signal having the same polarity is continuously input at least once in one horizontal scanning period. It is characterized by being supplied to a data signal output line.

  As a result, data signals having the same polarity are continuously supplied, so that the number of polarity inversions can be reduced. Since the number of times of polarity inversion is reduced, the amount of charge movement is reduced, and the charge accumulated in the data signal lines, pixels, and selection switching elements can be reduced, so that power consumption can be reduced.

  In the liquid crystal display device according to the present invention, as described above, each of the data signal output lines is connected to the data signal line driving circuit via the first switching element, and via the second switching element. Are connected to each other.

  In addition, as described above, the driving method of the liquid crystal display device according to the present invention supplies a data signal to one data signal line among the plurality of data signal lines constituting the above set, and then the next data signal. The first switching element is turned off and the second switching element is turned on until a data signal is supplied to the line.

  Therefore, the charge accumulated in the capacitance floating in the selection switching element for selecting the data signal line can be averaged, so that the power consumption caused by the accumulated charge can be reduced.

[Embodiment 1]
(Configuration of liquid crystal display device)
An embodiment of a liquid crystal display device according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the liquid crystal display device of this embodiment together with an equivalent circuit of the display portion. The liquid crystal display device is a so-called SSD type active matrix liquid crystal display device in which data signal lines for supplying video signals are bundled in a plurality of units and connected to the output of a data signal line driving circuit.

  As shown in FIG. 1, the liquid crystal display device 10 includes a data signal line driving circuit 1, a scanning signal line driving circuit 2, a switch control unit 3, and a display unit 9. The display unit 9 includes two transparent substrates, an active matrix substrate 7 and a counter substrate 8, and a liquid crystal (not shown) is filled between the active matrix substrate 7 and the counter substrate 8. The active matrix substrate 7 includes data signal lines DL11 to DLn, scanning signal lines GL1 to GLm, a first switch unit 31, a second switch unit 32, a selection switch unit 33, a pixel switch unit 5, and a pixel electrode. 6 is provided. The counter substrate 8 includes a counter electrode 11. Each switch unit is configured by a thin film transistor (TFT).

  In the active matrix substrate 7, the data signal lines DL11 to DLn and the scanning signal lines GL1 to GLm are orthogonal to each other, and the display area is divided into a matrix. Each divided area corresponds to a pixel which is a display unit of an image. At each intersection of the data signal line and the scanning signal line, a pixel switch unit 5 and a pixel electrode 6 are arranged, and a liquid crystal is provided for each pixel by the pixel electrode 6 and the counter electrode 11 provided on the counter substrate 8. A capacity is formed. In addition, liquid crystal is sealed between the pixel electrode 6 and the counter electrode 11, and light is transmitted or blocked by changing the alignment of the liquid crystal due to the influence of electrolysis between the electrodes. Light transmission / blocking is controlled for each pixel by turning on / off the pixel switch unit 5. The voltage applied to the liquid crystal capacitor changes according to the data signal, and the brightness of each pixel can be made depending on the magnitude of the applied voltage. In addition, since the color display uses a method of additively mixing the three primary colors (RGB) of light, three pixels corresponding to R, G, and B are configured as a set.

  In each pixel region, the scanning signal lines GL1 to GLm are connected to the gate terminal of the pixel switch unit 5, the data signal lines DL11 to DLn are connected to the source terminal of the pixel switch unit 5, and the pixel electrode 6 is connected to the pixel switch unit 5. Connected to the drain terminal.

  As described above, the liquid crystal display device 10 according to the present embodiment is an SSD active matrix liquid crystal display device, and the driving method thereof is to divide a source signal (data signal) into three parts and output them in one horizontal scanning period. To do. In this type of liquid crystal display device, a set of a plurality of data signal lines (in this embodiment, three data signal lines corresponding to RGB) is connected to a data output circuit (source driver) common to the plurality of data signal lines. This is a driving method driven by a chip (not shown). Therefore, the plurality of data signal lines DL11 to DLn are bundled by a set of three data signal lines arranged continuously. The data signal lines DL11 to DLn are connected to output signal lines (data signal output lines) D1 to Dn / 3 of the data signal line driving circuit 1 in a set of three. Each of the data signal lines DL11 to DLn is connected to the output signal lines D1 to Dn / 3 via the selection switch unit 33 connected individually. The gate terminal of each selection switch unit 33 connected to the data signal lines DL11 to DLn is connected to the switch control unit 3 by the data signal line selection lines GLR, GLG, and GLB. That is, the data signal line DL11 is connected to the output signal line D1 via the selection switch unit 33, and the data signal line selection line GLR is connected to the gate terminal of the selection switch unit 33. Similarly, the data signal line DL12 is connected to the output signal line D1 via the selection switch unit 33, the data signal line selection line GLG is connected to the gate terminal of the selection switch unit 33, and the data signal line DL13 is The selection switch unit 33 is connected to the output signal line D1, and the selection switch unit 33 has a gate terminal connected to the data signal line selection line GLB.

  The switch control unit 3 sequentially switches on / off of the selection switch unit 33 provided in the three data signal lines forming the set. As a result, the three data signal lines forming the set are sequentially connected to the output signal line. For example, the data signal lines DL11, DL12, DL13 form a pair and are connected to the output signal line D1, and the data signal lines DL11, DL12 are controlled by ON / OFF control of the selection switch unit 33 by the switch control unit 3. , DL13 are sequentially electrically connected to the output signal line D1.

  In the above description, the configuration in which the data signal lines are switched in the order of R, G, and B is described. However, the data signal lines may be supplied in other orders, and are not particularly limited.

(Operation example of liquid crystal display device)
Here, an operation example of a general SSD liquid crystal display device will be described. The data signal lines DL11, DL12, and DL13 are respectively connected to the three primary colors constituting the display color, that is, red (R), green (G), and blue (B) pixels. A data output circuit (source driver chip; not shown) is provided for each set of data signal lines corresponding to RGB constituting one color in the data signal line driving circuit. Drive). The data output circuit outputs data signals to the data signal lines in the order of RGB for each group. At this time, in order to secure a certain time for writing a data signal from each data signal line to the pixel while increasing the driving speed, the data signal lines of the same color in each set are driven simultaneously. That is, among each set of data signal lines connected to the output signal lines D1 to Dn / 3, first, the data signal line corresponding to R is simultaneously driven, and then the data signal line corresponding to G is simultaneously driven. Finally, the data signal lines corresponding to B are simultaneously driven.

  When driven by this method, a constant value is given to the counter electrode 11 while one scanning signal line is active.

  FIG. 2 is a timing chart showing driving in the SSD liquid crystal display device. According to FIG. 2, scanning signals are sequentially supplied to the scanning signal lines GL1 to GLm. That is, the scanning signal lines GL1, GL2 to GLm are sequentially selected by the scanning signal line driving circuit 2 and supplied with scanning signals. Then, the gate of the pixel switch unit 5 connected to the selected scanning signal line is turned on, and an active state in which a source signal (data signal) can be supplied to the pixel electrode 6 is established.

  Further, according to FIG. 2, in each period in which the scanning signal lines GL1 to GLm are selected, the data signal line selection signals are sequentially supplied to the data signal line selection lines GLR, GLG, and GLB. The data signal line selection lines GLR, GLG, and GLB are connected to data signal lines corresponding to R, G, and B pixels, respectively. Therefore, the data signal line selection signals are sequentially supplied to the data signal line selection lines GLR, GLG, and GLB, whereby the data signal lines corresponding to the R, G, and B pixels are sequentially selected.

  For example, in FIG. 2, when the scanning signal line GL1 is selected, the data signal line selection signal is sequentially supplied to the data signal line selection lines GLR, GLG, and GLB. When the data signal line selection signal is supplied, the gate of the selection switch unit 33 connected to the data signal line selection line is turned on, and the data signal line connected to the selection switch unit 33 that is turned on is turned on. Thus, the data signal from the output signal line can be supplied. As a result, the data signal from the output signal line is sequentially supplied to the data signal line corresponding to the R, G, and B pixels.

  In each period in which the scanning signal lines GL1 to GLm are selected, data signals are simultaneously supplied to the output signal lines D1 to Dn / 3. Here, each output signal line is supplied with each data signal corresponding to R, G, B by time division. For example, when the scanning signal line GL1 is selected, the data signals R11, G12, and B13 are supplied to the output signal line D1 by time division, and the data signals R14, G15, and B16 are time-divided to the output signal line D2. The data signals R1 (n-2), G1 (n-1), and B1n are supplied to the output signal line Dn / 3 by time division.

  The timing at which the R, G, and B data signals are supplied to the output signal lines D1 to Dn / 3 by time division is the data signal line corresponding to the R, G, and B pixels by the data line selection signal described above. Are synchronized with the timing at which are sequentially selected.

  For example, when the scanning signal line GL1 is selected, data signal line selection signals are sequentially supplied to the data signal line selection lines GLR, GLG, and GLB, but the data signal line selection lines GLR, GLG, and GLB are supplied. The timing at which the data signal line selection signal is supplied is synchronized with the timing at which the R, G, B data signals are supplied to the output signal lines D1 to Dn / 3 by time division.

  As a result, an R data signal is applied to the data signal line corresponding to the R pixel, a G data signal is applied to the data signal line corresponding to the G pixel, and a B data signal is applied to the data signal line corresponding to the B pixel. Each data signal can be supplied.

  Note that RGB data is written to the pixels as follows.

  First, while the scanning signal line GL1 is active and the data signal line selection line GLR is active, the data signals R11 to R1 (n−2) of the data signal lines up to the output signal lines D1 to Dn / 3 are opposed to each other. The voltage difference from the COM signal of the electrode 11 is written in the corresponding pixel (here, the pixel corresponding to R).

  Subsequently, while the scanning signal line GL1 is active and the data line selection line GLG is active, the data signals G12 to G1 (n-1) of the data signal lines D1 to Dn / 3 are opposed to each other. The voltage difference from the COM signal of the electrode 11 is written in the corresponding pixel (here, the pixel corresponding to G).

  Further, while the scanning signal line GL1 is active and the data line selection line GLB is active, the data signals B13 to B1n of the data signal lines up to the output signal lines D1 to Dn / 3, the COM signal of the counter electrode 11, and Are written in the corresponding pixels (here, the pixels corresponding to B).

  In this way, writing is performed on all the pixels connected to one scanning signal line. When writing of the pixels connected to the scanning signal line GL1 is completed, writing of the pixels connected to the scanning signal line GL2 is subsequently performed. In writing of the scanning signal line GL2, similarly to the scanning signal line GL1, writing is sequentially performed on the pixels for each pair of R, G, and B. Thereafter, similarly, scanning is performed in the vertical direction for each scanning signal line, and the same processing is repeated up to the scanning signal line GLm, and pixels for one screen of m × n are written.

  In such an SSD liquid crystal display device, when the conventional configuration shown in FIG. 15 is applied, when the scanning signal is in the on state, the charge accumulated in the capacitance floating in the selection switch section 33 is recovered. The problem of being unable to do so arises. Here, driving of a conventional liquid crystal display device will be described with reference to a timing chart of FIG.

  In FIG. 3, SWR, SWG, and SWB indicate signals supplied to the selection switch units 33 corresponding to R, G, and B through the data signal line selection lines GLR, GLG, and GLB, and LP is a data Latch pulses that define the switching timing of the signal line selection lines GLR, GLG, and GLB are shown, NET1 and NET2 show the potentials of the output signal lines D1 and D2 (see FIG. 16), and R1, G1, B1, and R2 show Each represents a pixel potential. In the driving example shown in FIG. 3, the selection switch 33 is turned on in the order of R, G, and B, and the dot inversion method (plus → minus → plus or minus → plus → minus) is adopted as the driving method. ing. Moreover, as a display pattern, the case where the black in the normally white system is displayed is shown.

  In such an SSD liquid crystal display device, when the polarity changes in NET1 and NET2 (plus → minus, or minus → plus), a large power consumption is caused by the influence of charges in the data signal line, the pixel, and the selection switch unit. Is consumed in the data signal line driving circuit. For example, since a positive charge is accumulated in the data signal line, the pixel, and the selection switch unit by writing to the pixel corresponding to R1 (plus polarity), in the writing operation to the pixel corresponding to the next G1, It is necessary to supply a negative polarity potential in consideration of the remaining positive charge. As a result, power consumption increases.

  On the other hand, in the liquid crystal display device 10 according to the present embodiment, in particular, by including the first switch unit 31, the second switch unit 32, and the switch control unit 3 that controls the on / off thereof, The power consumption can be further reduced as compared with the conventional case. Below, the concrete structure of the 1st switch part 31, the 2nd switch part 32, and the switch control part 3 is demonstrated.

  As shown in FIG. 1, the output signal lines D1 to Dn / 3 are connected to the data signal line driving circuit 1 via the first switch part 31 and electrically connected to each other via the second switch part 32. Connected to each other. And the gate terminal of each 1st switch part 31 connected to each output signal line D1-Dn / 3 is connected to terminal SW1 of the switch control part 3, and connects each output signal line D1-Dn / 3. The gate terminal of each second switch unit 32 is connected to the terminal SW <b> 2 of the switch control unit 3.

  As a result, while the ON signal is supplied from the switch control unit 3 to the first switch unit 31, the data signal line driving circuit 1 and the output signal lines D1 to Dn / 3 are electrically connected to each other and turned off. By supplying the signal, the data signal line driving circuit 1 and the output signal lines D1 to Dn / 3 are electrically disconnected from each other. Further, while the OFF signal is supplied from the switch control unit 3 to the second switch unit 32, the output signal lines D1 to Dn / 3 are electrically disconnected from each other, and the ON signal is supplied. The output signal lines D1 to Dn / 3 are electrically connected to each other.

(Operation example of the liquid crystal display device of the present invention)
Here, an operation example of the liquid crystal display device 10 according to the present embodiment will be described with reference to a timing chart of FIG. Here, the difference from the above-described operation example of the general SSD type liquid crystal drive device will be mainly described. In FIG. 4, SW <b> 1 indicates a signal supplied to the first switch unit 31, and SW <b> 2 indicates a signal supplied to the second switch unit 32. FIG. 5 is a partially enlarged view for explaining an operation example of the liquid crystal display device 10.

  As shown in FIG. 4, the first switch unit 31 (SW1) and the second switch unit 32 (SW2) are turned on / off at the Hi / Lo switching timing of the latch pulse LP. For example, when the first switch unit 31 (SW1) is on and the selection switch unit 33 (SWR) corresponding to R is on, the output signal line D1, the data signal line DL11, the output signal line D2, and the data The signal line DL21, the output signal line Dn / 3, and the data signal line DL (n / 3-2) are electrically connected to each other, and each data signal corresponding to R is connected to the scanning signal line in the active state. Supplied to each pixel.

  Thereafter, the selection switch section 33 (SWR) corresponding to R is turned off, and writing of the R data signal is completed. At this time, all the selection switch sections 33 (SWR, SWG, SWB) are turned off, and the output signal lines D1 to Dn / 3 and the data signal lines DL11 to DLn are electrically disconnected. Subsequently, using the timing of LP, the first switch unit 31 (SW1) is turned off and the second switch unit 32 (SW2) is turned on. Here, the ON / OFF timings of the first and second switch units 31 and 32 may be synchronized with each other or may be asynchronous. For example, as illustrated in FIG. 6, the first switch unit 31 can be configured to be in an off state at least while the second switch unit 32 is in an on state.

  NET1, NET2,... NETn (see FIG. 5) are electrically connected to each other (short circuit) by the operation of the first and second switch sections 31 and 32. Thereby, since the electric charges floating in NET1, NET2,... NETn are averaged, the charge / discharge current can be suppressed, and the power consumption can be reduced. Thus, according to the present embodiment, since the charge accumulated in the capacitance floating in the selection switch section 33 can be averaged, the power consumption caused by this accumulated charge can be reduced.

  Here, after NET1, NET2,... NETn are electrically connected to each other, a desired potential (for example, Vcom (common electrode potential), source center potential (1/2 VLS)) may be supplied. Thereby, it is possible to reliably collect charges (charge sharing) and fix NET1, NET2,... NETn to a desired potential.

  Further, the liquid crystal display device 10 according to the present embodiment may have the following configuration. That is, at the beginning of the ON period of each selection switch section 33, the corresponding data signal lines are electrically connected to each other and Vcom is supplied to the corresponding pixel. FIG. 7 is a timing chart showing an operation example of the liquid crystal display device 10 having this configuration. As shown in the figure, at the beginning of the ON period of the selection switch unit 33 (SWR), the first switch unit 31 (SW1) is turned off and the second switch unit 32 (SW2) is turned on. Thereby, the output signal lines D1 to Dn / 3 are electrically connected to each other, and the data signal lines DL11, DL21,... Corresponding to R are electrically connected to each other. In this state, Vcom is supplied from one end of the conductive electrode of the second switch section 32 (see FIG. 1), whereby Vcom is written to the pixel (R pixel) connected to the scanning signal line in the active state. Thereafter, the first switch unit 31 (SW1) is turned on, and the second switch unit 32 (SW2) is turned off, whereby the output signal lines D1 to Dn / 3 are electrically disconnected from each other. , R corresponding to the data signal lines DL11, DL21,... Are electrically connected to the data signal line driving circuit 1. As a result, the data signal corresponding to R is supplied to the R pixel fixed at Vcom.

  Subsequently, when the selection switch unit 33 (SWG) is turned on, the first switch unit 31 (SW1) is turned off and the second switch unit 32 (SW2) is turned on at the beginning of the on period. Accordingly, the output signal lines D1 to Dn / 3 are electrically connected to each other, and the data signal lines DL12, DL22,... Corresponding to G are electrically connected to each other. In this state, Vcom is supplied from one end of the conductive electrode of the second switch section 32 (see FIG. 1), whereby Vcom is written to the pixel (G pixel) connected to the scanning signal line in the active state. Thereafter, the first switch unit 31 (SW1) is turned on, and the second switch unit 32 (SW2) is turned off, whereby the output signal lines D1 to Dn / 3 are electrically disconnected from each other. , G corresponding to the data signal lines DL12, DL22,... Are electrically connected to the data signal line driving circuit 1. Thereby, the data signal corresponding to G is supplied to the G pixel fixed to Vcom.

  Finally, when the selection switch unit 33 (SWB) is turned on, the first switch unit 31 (SW1) is turned off and the second switch unit 32 (SW2) is turned on at the beginning of the on period. Thus, the output signal lines D1 to Dn / 3 are electrically connected to each other, and the data signal lines DL13, DL23,... Corresponding to B are electrically connected to each other. In this state, Vcom is supplied from one end of the conductive electrode of the second switch section 32 (see FIG. 1), whereby Vcom is written to the pixel (B pixel) connected to the scanning signal line in the active state. Thereafter, the first switch unit 31 (SW1) is turned on, and the second switch unit 32 (SW2) is turned off, whereby the output signal lines D1 to Dn / 3 are electrically disconnected from each other. , B are electrically connected to the data signal line driving circuit 1. As a result, the data signal corresponding to B is supplied to the B pixel fixed at Vcom.

  According to the above configuration, the data signal is switched every time RGB is switched in the period in which the selection switch unit 33 is in the on state, that is, the period in which the data signal is supplied (writing to the pixel) within one horizontal scanning period. Before writing to the pixel, the pixel potential can be fixed at Vcom. As a result, the charges accumulated in the capacitance floating in the selection switch section 33 can be reliably collected, and the charges accumulated in the loads on the data signal lines DL11, DL21,... Can be collected. Therefore, the power consumption of the entire liquid crystal display device can be reduced as compared with the conventional one, and the display quality can be improved.

  By the way, in the above description, the configuration in which the selection switch unit 33 is switched so that the data signal lines are selected in the order of R, G, B has been described. Not. For example, as shown in FIG. 8, R (+) → B (+) → G (−) → G (+) → R (−) → B so that data signals having the same polarity are continuously supplied. The selection switch unit 33 may be switched in the order of (−) → B (+) → R (+) → G (−). That is, since the data signals corresponding to R and B have the same polarity, the selection switch unit 33 can be switched so that they are continuous. As a result, the number of polarity inversions can be reduced, so that power consumption can be further reduced. Further, as shown in FIG. 9, R (+) → B (+) → G (−) → R (−) → B (−) → G (+) → R (+) → B (−) → G If the configuration is switched in the order of (-), the number of polarity inversions can be further reduced.

  Thus, in addition to the charge sharing operation, it is possible to further reduce power consumption by adopting a configuration that reduces the number of polarity inversions.

  In these configurations, since the amount of charge movement when switching between the same polarities is small, the charge sharing by the on / off switching operation of the first and second switch units 31 and 32 is performed only when the polarity is inverted. It is good. For example, in FIG. 8, at the timing of B → G, G → G, G → R, B → B, and R → G where the polarity is reversed, the first switch unit 31 is turned off and the second switch unit 32 is turned on. To charge share. As a result, the number of charge sharing operations can be reduced, so that power consumption can be further reduced.

[Embodiment 2]
(Configuration of liquid crystal display device)
An embodiment of a liquid crystal display device according to the present invention will be described with reference to the drawings. For convenience of explanation, members having the same functions as those shown in the first embodiment are given the same reference numerals, and explanation thereof is omitted. In addition, the terms defined in Embodiment 1 are used in accordance with the definitions in this embodiment unless otherwise specified.

  FIG. 10 is a block diagram showing the liquid crystal display device of this embodiment together with an equivalent circuit of the display portion. The liquid crystal display device is an SSD active matrix liquid crystal display device in which data signal lines for supplying video signals are bundled into a plurality of units and connected to an output of a data signal line driving circuit.

  As shown in FIG. 10, the liquid crystal display device 20 has a configuration in which the first and second switch portions 31 and 32 are omitted from the liquid crystal display device 10 shown in the first embodiment. That is, each of the output signal lines D1 to Dn / 3 is connected to the data signal line driving circuit 1 and is electrically disconnected from each other.

(Operation of liquid crystal display)
Here, an operation example of the liquid crystal display device 20 according to the present embodiment will be described with reference to a timing chart of FIG.

  In FIG. 11, SWR, SWG, and SWB indicate signals supplied to the selection switch units 33 corresponding to R, G, and B through the data signal line selection lines GLR, GLG, and GLB, and LP indicates data Latch pulses that define the switching timing of the signal line selection lines GLR, GLG, and GLB are shown, NET1 and NET2 show the potentials of the output signal lines D1 and D2 (see FIG. 10), and R1, G1, B1, and R2 show Each represents a pixel potential.

  The liquid crystal display device 20 according to the present embodiment is configured to reduce the number of polarity inversions by changing the selection order of the data signal lines while assuming the dot inversion driving method. Specifically, as shown in FIG. 11, R (+) → B (+) → G (−) → G (+) → R (− so that data signals of the same polarity are continuously supplied. ) → B (−) → B (+) → R (+) → G (−) in this order. Thus, since the data signals corresponding to R and B have the same polarity, the selection switch unit 33 can be switched so that they are continuous. Thereby, since the same polarity continues, the number of times of polarity inversion decreases. Since the number of times of polarity inversion is reduced, the amount of charge movement is reduced, and the charge accumulated in the data signal line, the pixel, and the selection switch unit 33 can be reduced, so that power consumption can be reduced.

  Also, as shown in FIG. 12, R (+) → B (+) → G (−) → R (−) → B (−) → G (+) → R (+) → B (−) → G If the configuration is switched in the order of (-), the number of polarity inversions can be further reduced.

  Further, as shown in FIG. 13, in FIG. 11, when the same selection switch unit 33 is continuously selected (for example, G → G, B → B), the ON period (active period) of SWG and SWB. ) Is lengthened, and the switching operation of SWG → SWG and SWB → SWB may be omitted. Thereby, since the frequency of the switching signal of SWR, SWG, and SWB can be reduced, power consumption can be further reduced.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  Finally, each block included in the liquid crystal display device, in particular, the switch control unit 3 may be configured by hardware logic, or may be realized by software using a CPU as follows.

  That is, the liquid crystal display device includes a CPU (central processing unit) that executes instructions of a control program for realizing each function, a ROM (read only memory) that stores the program, a RAM (random access memory) that expands the program, A storage device (recording medium) such as a memory for storing the program and various data is provided. An object of the present invention is to provide a recording medium in which a program code (execution format program, intermediate code program, source program) of a control program for a liquid crystal display device, which is software that realizes the functions described above, is recorded so as to be readable by a computer. This can also be achieved by supplying the liquid crystal display device and reading and executing the program code recorded on the recording medium by the computer (or CPU or MPU).

  Examples of the recording medium include tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks / hard disks, and disks including optical disks such as CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  The liquid crystal display device may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  The liquid crystal display device of the present invention can be used for a product using a liquid crystal display, and can be suitably used for a liquid crystal display such as a television, a mobile phone, and an in-vehicle instrument panel.

FIG. 2 is a block diagram showing the liquid crystal display device according to the first embodiment together with an equivalent circuit of the display unit. 6 is a timing chart showing driving in an SSD liquid crystal display device. It is a timing chart which shows the drive in the liquid crystal display device of the conventional SSD system. 3 is a timing chart showing driving in the liquid crystal display device according to the first embodiment. FIG. 6 is a partial enlarged view for explaining an operation example of the liquid crystal display device according to the first embodiment. FIG. 10 is a partial enlarged view for explaining another operation example of the liquid crystal display device according to the first embodiment. 6 is a timing chart showing another driving in the liquid crystal display device according to the first embodiment. 6 is a timing chart showing another driving in the liquid crystal display device according to the first embodiment. 6 is a timing chart showing another driving in the liquid crystal display device according to the first embodiment. It is a block diagram which shows the liquid crystal display device which concerns on this Embodiment 2 with the equivalent circuit of the display part. 10 is a timing chart showing driving in the liquid crystal display device according to the second embodiment. 12 is a timing chart showing another driving in the liquid crystal display device according to the second embodiment. 12 is a timing chart showing another driving in the liquid crystal display device according to the second embodiment. It is an equivalent circuit diagram showing the configuration of a conventional SSD active matrix liquid crystal display device. FIG. 11 is a block diagram illustrating a configuration of a display device disclosed in Patent Document 1. FIG. 16 is a partial enlarged view for explaining an operation example of the display device shown in FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data signal line drive circuit 2 Scanning signal line drive circuit 3 Switch control part 31 1st switch part (1st switching element)
32 2nd switch part (2nd switching element)
33 Selection switch (selection switching element)
5 pixel switch unit 6 pixel electrode 7 active matrix substrate 8 counter substrate 9 display unit 10, 20 liquid crystal display device 11 counter electrode GL1 to GLm scanning signal line DL11 to DLn data signal line GLR data signal line selection line GLG data signal line selection line GLB data signal line selection line D1-Dn / 3 output signal line (data signal output line)

Claims (8)

A plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, a pixel electrode disposed at each intersection of these signal lines, a counter electrode disposed opposite to the pixel electrode, and a plurality of data signal output lines A data signal line driving circuit for outputting a data signal,
The plurality of data signal lines constitute a set of data signal lines continuously arranged corresponding to the primary colors constituting the display color, and via a selection switching element provided for each data signal line. And each set is connected to the data signal output line,
The data signal line driving circuit time-divides a data signal corresponding to the primary color within one horizontal scanning period and outputs the data signal to each data signal output line,
In each of the above groups, the data signal line corresponding to the primary color is sequentially selected by turning on / off the selection switching element, whereby the data signal output from the data signal line driving circuit is transmitted to the data signal line. In the supplied liquid crystal display device,
Each of the data signal output lines is connected to the data signal line driving circuit via a first switching element, and is connected to each other via a second switching element. .   The first switching element between the time when a data signal is supplied to one data signal line and the time when the data signal is supplied to the next data signal line among the plurality of data signal lines constituting the set. The liquid crystal display device according to claim 1, wherein the second switching element is turned on while turning off.   3. The liquid crystal display device according to claim 1, wherein the first switching element is in an off state at least while the second switching element is in an on state.   4. The liquid crystal display device according to claim 2, wherein a common electrode potential is supplied to the data signal output line when the second switching element is in an ON state.   5. The liquid crystal display device according to claim 1, wherein a data signal having the same polarity is continuously supplied to the data signal output line at least once in one horizontal scanning period. . At the beginning of the period in which the selective switching element is on, the second switching element is on, and the first switching element is at least as long as the second switching element is on. Is off,
2. The liquid crystal display device according to claim 1, wherein a common electrode potential is supplied to the data signal output line when the second switching element is in an ON state. A plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, a pixel electrode disposed at each intersection of these signal lines, a counter electrode disposed opposite to the pixel electrode, and a plurality of data signal output lines A data signal line driving circuit for outputting a data signal,
The plurality of data signal lines constitutes a set of data signal lines arranged continuously corresponding to the primary colors constituting the display color, and for each set via a separately provided selection switching element. Connected to the data signal output line,
The data signal line driving circuit time-divides a data signal corresponding to the primary color within one horizontal scanning period and outputs the data signal to each data signal output line,
In each of the above groups, the data signal line corresponding to the primary color is sequentially selected by turning on / off the selection switching element, whereby the data signal output from the data signal line driving circuit is transmitted to the data signal line. In the supplied liquid crystal display device,
A liquid crystal display device, wherein a data signal having the same polarity is continuously supplied to the data signal output line at least once in one horizontal scanning period. A plurality of data signal lines and a plurality of scanning signal lines orthogonal to each other, a pixel electrode disposed at each intersection of these signal lines, a counter electrode disposed opposite to the pixel electrode, and a plurality of data signal output lines A data signal line driving circuit for outputting a data signal,
The plurality of data signal lines constitute a set of data signal lines continuously arranged corresponding to the primary colors constituting the display color, and via a selection switching element provided for each data signal line. And each set is connected to the data signal output line,
The data signal line driving circuit time-divides a data signal corresponding to the primary color within one horizontal scanning period and outputs the data signal to each data signal output line,
In each set, the data signal line corresponding to the primary color is sequentially selected by turning on / off the selection switching element, thereby supplying the data signal output from the data signal line driving circuit to the data signal line. In the liquid crystal display device driving method,
Each of the data signal output lines is connected to the data signal line driving circuit via a first switching element, and is connected to each other via a second switching element,
Among the plurality of data signal lines constituting the set, the first switching element is provided between the time when the data signal is supplied to one data signal line and the time when the data signal is supplied to the next data signal line. A method for driving a liquid crystal display device, wherein the second switching element is turned on while turning off.

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