KR100864971B1 - Method and apparatus for driving liquid crystal display device - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a liquid crystal display device to improve image quality when driving dot inversion.

The method and apparatus for driving a liquid crystal display according to the present invention generate a bit inversion signal, invert at least one bit in the digital data in response to the bit inversion signal, and then convert the at least one bit inverted digital data into an analog voltage. Will be converted.

Description

TECHNICAL AND APPARATUS FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE}             

FIG. 1 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme.

3 is a circuit diagram schematically showing a conventional liquid crystal display element driving apparatus.

FIG. 4 is a circuit diagram illustrating in detail the data driver illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating in detail a gamma voltage supply unit and a digital-analog converter shown in FIG. 4.

FIG. 6 is a circuit diagram illustrating a gamma voltage selected by the decoder illustrated in FIG. 5 when the digital data is '111111'.

7 is a waveform diagram illustrating a cause of a luminance difference between two horizontal lines to which the same polarity is applied in the conventional two dot inversion scheme.

8 is a circuit diagram schematically showing a liquid crystal display device driving apparatus according to an embodiment of the present invention.                 

FIG. 9 is a circuit diagram illustrating the bit controller shown in FIG. 8 in detail.

FIG. 10 is a waveform diagram illustrating input / output waveforms of the bit controller illustrated in FIG. 8.

FIG. 11 is a circuit diagram illustrating in detail the data driver illustrated in FIG. 8.

FIG. 12 is a circuit diagram illustrating the gamma voltage supply unit and the digital-to-analog converter shown in FIG. 11 in detail.

FIG. 13 is a circuit diagram illustrating a gamma voltage selected by the decoder illustrated in FIG. 12 when the digital data is '111111' in the method and apparatus for driving an LCD according to an exemplary embodiment of the present invention.

FIG. 14 is a waveform diagram illustrating a driving waveform of a one dot inversion method in a method and apparatus for driving an LCD according to an exemplary embodiment of the present invention.

15 is a waveform diagram illustrating a driving waveform of a two dot inversion method in a method and apparatus for driving an LCD according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1,81: Timing controller 2,82: Data driver

3,83: gate driver 4,84: gamma reference voltage generator

5,85: liquid crystal panel 21,111: data register

22,112: Shift register 23,24,113,114: Latch

25,115: DAC 26,116: output circuit

26a, 116a: buffer 27,117: gamma voltage supply unit                 

51,95,121: Inverter 52,122: Decoder

53,123: switch element 91,92: comparator

93: RS flip-flop 94: AND gate

124: exclusive OR gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method and apparatus for driving a liquid crystal display device to improve image quality when driving dot inversion.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching device used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

The liquid crystal display is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method for inverting polarities of data between adjacent liquid crystal cells in a vertical line direction, a column inversion method for inverting polarities of data between adjacent liquid crystal cells in a horizontal line direction, a vertical line direction and a horizontal line direction. There is a dot inversion method of inverting the polarity of data between adjacent liquid crystal cells.

Among the inversion schemes, the one-dot inversion scheme inverts the polarity of adjacent data in the vertical direction in one dot period as shown in FIG. 1 and inverts the polarity of the adjacent data in the horizontal direction in one dot period. In contrast to the one-dot inversion method, the two-dot inversion method inverts the polarity of adjacent data in the vertical direction in two dot periods as shown in FIG. 2 and inverts the polarity of the adjacent data in the horizontal direction in one dot period.

In order to implement the dot inversion method, the data driver 2 inverts polarities of adjacent data in the horizontal direction. At the same time, the data driver 2 inverts the polarity of data every horizontal period H in the one dot inversion method or inverts the polarity of the data every two horizontal periods H in the two dot inversion method.

In the two-dot inversion method, there is a problem in that a luminance difference occurs between adjacent horizontal lines due to a difference in the amount of data charged in two adjacent liquid crystal cells to which data of the same polarity is applied. This will be described in detail with reference to FIGS. 3 to 7.
Referring to FIG. 3, a driving apparatus of a liquid crystal display device includes a liquid crystal panel in which data lines DL1 to DLm and gate lines GL1 to GLn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at an intersection thereof. 5), a data driver 2 for supplying data to the data lines DL1 to DLm of the liquid crystal panel 5, and supplying scanning pulses to the gate lines GL1 to GLn of the liquid crystal panel 5; The gate driver 3 for controlling the gamma reference voltage generator 4 for supplying the gamma voltage to the gate driver 3, and the timing controller 1 for controlling the data driver 2 and the gate driver 3. It is provided.

delete

In the liquid crystal panel 5, liquid crystal is injected between two glass substrates. On the lower glass substrate of the liquid crystal panel 5, the data lines DL1 to DLm and the gate lines GL1 to GLn are orthogonal to each other. TFTs are formed at intersections of the data lines DL1 to DLm and the gate lines GL1 to GLn. The TFT supplies the data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. For this purpose, the gate electrodes of the TFTs are connected to the gate lines GL1 to GLm, and the source electrodes of the TFTs are connected to the data lines DL1 to DLm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc.

The timing controller 1 separates the digital video data supplied from the digital video card (not shown) into even-numbered pixel data and odd-numbered pixel data and supplies them to the data driver 2. In addition, the timing controller 1 generates a data driving control signal DDC and a gate driving control signal GDC by using the horizontal / vertical synchronization signals H and V input thereto. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the like. This data drive control signal DDC is supplied to the data driver 2. The gate driving control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like. The gate drive control signal GDC is supplied to the gate driver 3.

The gate driver 3 sequentially generates scan pulses, that is, gate high pulses, in response to the gate drive control signal GDC supplied from the timing controller 1. The gate driver 3 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the swing width of the scan pulse voltage to be suitable for driving the liquid crystal cell Clc. The TFT is turned on in response to the scan pulse from the gate driver 3. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The gamma reference voltage generator 4 supplies a predetermined number of positive gamma reference voltages GH and negative gamma reference voltages GL to the data driver 2, respectively. The positive gamma reference voltage GH and the negative gamma reference voltage GL are generated using a voltage divider resistor.

The data driver 2 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 1. After the data driver 2 samples the data RGB from the timing controller 1, the data driver 2 latches the data and converts the data into a gamma voltage. This data driver 2 is implemented by a plurality of integrated circuits (hereinafter referred to as " IC ") 2a having the configuration as shown in FIG.

Each data IC 2a includes a data register 21 into which data RGBeven and RGBodd are input from the timing controller 1, a shift register 22 for generating a sampling clock, as shown in FIG. A first latch 23, a second latch 24, and a digital-to-analog converter (Digital) connected between the shift register 22 and k (where k is an integer smaller than m) of the data lines DL1 to DLk. to Analog Converter (hereinafter referred to as " DAC ") 25, and an output circuit 26, and a gamma voltage supply part 27 connected between the gamma reference voltage generator 4 and the DAC 25.

The data register 21 temporarily stores odd pixel data RGBodd and even pixel data RGBeven separated by the timing controller 1, and supplies the stored data RGBodd and RGBeven to the first latch 23. .

The shift register 22 shifts the source start pulse SSP from the timing controller 1 in accordance with the source sampling clock signal SSC to generate a sampling signal. In addition, the shift register 22 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 22.

In response to a sampling signal sequentially input from the shift register 22, the first latch 23 samples the pixel data RGBeven and RGBodd from the data register 21, latches the data by one line, and then latches the data by one line. Output data at the same time.

The second latch 24 latches data input from the first latch 23, and then simultaneously outputs the latched data in response to the source output enable signal SOE from the timing controller 1.

The DAC 25 converts data from the second latch 24 into gamma voltages DGH and DGL from the gamma voltage supply unit 27. The gamma voltages DGH and DGL are analog voltages corresponding to the gray level values of the digital input data. For example, when the digital input data is 6 bits, 64 gamma voltages correspond to grayscale values of the digital input data.

The DAC 25 includes a multiplexer for selecting one of a positive gamma voltage and a negative gamma voltage in response to the polarity control signal POL.

The output circuit 26 includes a buffer connected to each of the data lines. The buffer of the output circuit 26 amplifies the data by its gain value to minimize signal attenuation.

The gamma voltage supply unit 27 subdivides the gamma reference voltage input from the gamma reference voltage generator 4 to supply the gamma voltage corresponding to each gray level to the DAC 25. The gamma voltage supply unit 27 is composed of a circuit for generating a gamma voltage of positive polarity and a circuit for generating a gamma voltage of negative polarity.

5 is a circuit diagram showing the gamma voltage supply unit 27 and the DAC 25 in detail.

In Fig. 5, the gamma voltage supply part 27 shows only a positive gamma voltage circuit. The negative gamma voltage circuit differs only in the polarity of the gamma reference voltage, and has a circuit configuration substantially the same as that of the positive gamma voltage circuit.

Referring to FIG. 5, the gamma voltage supply unit 27 includes 64 divided resistors R1 to R64 for subdividing the six positive polarity gamma reference voltages VH1 to VH6 into 64 gamma voltages.

The divided resistors R1 to R64 are connected in series by a predetermined number of resistors between the gamma reference voltages of which voltage levels are close, for example, between VH1 and VH2 and between VH2 and VH3. The divided resistors R1 to R64 supply the gamma voltage subdivided into 64 steps corresponding to each gray level to the DAC 25 through an output node between the resistor and the resistor.

The DAC 25 is composed of an inverter 51 for inverting data and a decoder 52 into which inverted digital data and non-inverted digital data are input.

The decoder 52 is combined with a plurality of switch elements 53 for switching signal paths in response to inverted data or non-inverted data to select a gamma voltage corresponding to a logic value of digital data. 6 shows the switch elements 53 shown in the drawing in detail. When the logic value of 6-bit digital data input from the second latch 24 to the DAC 25 is '111111', the switch elements located on the current path indicated by the dotted lines are turned on. The gamma voltage V64 for the gray value '64' is selected. The gamma voltage V64 of the gray level value '64' thus selected is supplied to the data line DL through the buffer 26a.

In the case of the 2-dot inversion method, the polarity control signal POL is inverted after maintaining the high logic value or the low logic value for 2 horizontal periods as shown in FIG. 7. The data voltage Vdata maintains the same polarity for two horizontal periods. Assuming that this data voltage Vdata rises or falls in synchronization with the nth scanning pulse VGn supplied to the nth gate line and that the voltage level is maintained for 2 horizontal periods, the liquid crystal connected to the nth gate line The voltage charged in the cell is reduced as much as the hatched portion of the desired voltage by the time when the data voltage Vdata is changed, while the data voltage Vdata is not changed in the liquid crystal cell connected to the n + 1 th gate line. Is charged. Therefore, in the two dot inversion scheme, a luminance difference occurs between two horizontal lines, thereby degrading image quality.

In addition to the two-dot inversion method, even when the polarity of the data voltage becomes large, the time for changing the voltage level increases by that much. Therefore, the liquid crystal cell voltage of the nth horizontal line and n + 1th The difference in the voltage of the liquid crystal cell of the horizontal line becomes larger. As a result, in the case of driving the liquid crystal display device by the one dot or two dot inversion method, it takes not only excessive time to charge the liquid crystal cell to the desired voltage level when the polarity is reversed, but also increases the load and noise, thereby improving image quality. Will fall.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a liquid crystal display device to improve image quality.

In order to achieve the above object, a method of driving a liquid crystal display device according to an embodiment of the present invention comprises the steps of inputting digital data, generating a bit inversion signal, at least one bit in the digital data in response to the bit inversion signal Inverting the signal, converting at least one bit inverted digital data into an analog voltage, and supplying the analog voltage to the liquid crystal cell.

In the method of driving a liquid crystal display device according to an embodiment of the present invention, the voltage supplied to the liquid crystal cell is characterized in that the polarity is reversed every horizontal period.

In the method of driving a liquid crystal display device according to an embodiment of the present invention, the voltage supplied to the liquid crystal cell is characterized in that the polarity is reversed every two horizontal periods.                     

In the method of driving a liquid crystal display device according to an embodiment of the present invention, the bit inversion signal is generated at the beginning of every horizontal period.

In the method of driving a liquid crystal display according to an embodiment of the present invention, the inverted bits in the digital data are characterized in that the most significant bit.

The driving apparatus of the liquid crystal display according to the embodiment of the present invention includes a bit controller for generating a bit inversion signal and at least one bit inverted in response to the bit inversion signal in the digital data supplied through the input line. A data driver converts the digital data in which the bits are inverted into an analog voltage and supplies the converted digital data to the liquid crystal cell.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the voltage supplied to the liquid crystal cell is characterized in that the polarity is reversed every horizontal period.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the voltage supplied to the liquid crystal cell is characterized in that the polarity is reversed every two horizontal periods.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the bit inversion signal is generated at the beginning of every horizontal period.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the bit inverted in the digital data is characterized in that the most significant bit.

In the driving apparatus of the liquid crystal display device according to an exemplary embodiment of the present invention, a plurality of data lines and a plurality of gate lines cross each other, switch elements are formed at an intersection thereof, and a liquid crystal cell is formed in a pixel region between the data line and the gate line. The LCD device further includes a liquid crystal panel, a gate driver for supplying scan pulses to the gate lines, and a timing controller for supplying digital data to the data driver and generating timing control signals required for the data driver and the gate driver.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the bit controller is characterized by delaying the source output enable signal SOE input from the timing controller to generate a bit inversion signal.

In the driving apparatus of the liquid crystal display device according to the embodiment of the present invention, the bit controller is characterized in that the monostable multivibrator.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 15.

Referring to FIG. 8, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention controls the bit controller 86, the bit controller 86, and the timing controller 81 to generate a bit inversion signal BINV. The data driver 82 for supplying data to the data lines DL1 to DLm of the liquid crystal panel 85 and the gate for supplying scanning pulses to the gate lines GL1 to GLn of the liquid crystal panel 85 by A driver 83 and a gamma reference voltage generator 84 for supplying a gamma voltage to the gate driver 83 are provided.

The timing controller 81 separates the digital video data supplied from the digital video card (not shown) into even-numbered pixel data and odd-numbered pixel data to supply the data driver 82 to the data driver 82. In addition, the timing controller 81 generates a data driving control signal DDC and a gate driving control signal GDC using the horizontal / vertical synchronization signals H and V input thereto. The data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and the like. The data drive control signal DDC is input to the data driver 82, and the source output enable signal SOE is commonly supplied to the data driver 82 and the bit controller 86. The gate driving control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like. The gate drive control signal GDC is supplied to the gate driver 83.

The bit controller 86 generates a bit inversion signal BINV for inverting the logic value of at least one bit, preferably the most significant bit MSB, of the six bit data of each of R, G, and B, and the bit inversion signal. (BINV) is supplied to the data driver 82. The bit inversion signal BINV is generated, for example, in high logic with a specific logic value at the beginning of every horizontal period so that the data voltage level can change at the beginning of every horizontal period. To this end, the bit controller 86 delays the source output enable signal SOE to generate the bit inversion signal BINV. The bit controller 86 may be integrated into the IC of the timing controller 81 or the data driver 82. A detailed description of this bit controller 86 will be given later with reference to FIGS. 9 and 10.

The gate driver 83 sequentially generates scan pulses, that is, gate high pulses, in response to the gate driving control signal GDC supplied from the timing controller 81. The gate driver 83 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the swing width of the scan pulse voltage to be suitable for driving the liquid crystal cell Clc. The TFT is turned on in response to the scan pulse from the gate driver 83. When the TFT is turned on, video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.

The gamma reference voltage generator 84 supplies a predetermined number of positive gamma reference voltages GH and negative gamma reference voltages GL to the data driver 82, respectively. The positive gamma reference voltage GH and the negative gamma reference voltage GL are generated using a voltage divider resistor.

The data driver 82 supplies data to the data lines DL1 to DLm in response to the data driving control signal DDC supplied from the timing controller 81. After the data driver 82 samples the data RGB from the timing controller 81, the data driver 82 latches the data and converts the data into a gamma voltage. Here, the data driver 82 inverts the logic value of the bit of the digital data indicated by the bit inversion signal BINV from the bit controller 86 to convert the digital data into a gamma voltage. This data driver 82 is implemented with a plurality of data ICs having the configuration as shown in FIG. A detailed description of the data IC of the data driver 82 will be described later with reference to FIGS. 11 and 12.

9 illustrates an embodiment of the bit controller 86.

)는 제3 저항(R3)을 경유하여 트랜지스터(Q1)의 베이스단자에 접속된다. 트랜지스터(Q1)의 컬럭터단자는 제1 노드(n1)에 접속되고, 트랜지스터(Q1)의 이미터단자는 기저전압원(GND)에 접속된다. Referring to FIG. 9, the bit controller 86 is implemented as a monostable multivibrator including two comparators 91 and 92, an RS flip-flop 93, and an NPN transistor Q1. The non-inverting terminal of the first comparator 91 is connected to the capacitor C1 and the second resistor R2 via the first node n1, and the inverting terminal of the first comparator 91 is connected to the second node n2. Is connected to two first resistors R1 having the same resistance value. The first resistor R1 is three resistors having the same resistance value and is connected in series between the common voltage source VCC and the ground voltage source GND. The ground voltage GND is set to 0V. The inverting terminal of the second comparator 92 is connected to two first resistors R1 having the same resistance value via the third node n3, and the non-inverting terminal of the second comparator 92 is connected to the fourth node. It is connected to the output terminal of the inverter 95 via (n4). The inverter 95 receives a source output enable signal SOE. The output terminal of the first comparator 91 is connected to the reset terminal R of the RS flip-flop 93, and the output terminal of the second comparator 92 is connected to the set terminal S of the RS flip-flop 93. The non-inverting output terminal Q of the RS flip-flop 93 is connected to one input terminal of the AND gate 94. The other input terminal of the AND gate 94 is connected to the output terminal of the inverter 95 via the fourth node n4. Inverting output terminal of RS flip-flop 93

Is connected to the base terminal of the transistor Q1 via the third resistor R3. The collector terminal of the transistor Q1 is connected to the first node n1, and the emitter terminal of the transistor Q1 is connected to the ground voltage source GND.

가 되고 제3 노드(n3) 상의 전압(VTL)이

가 되도록 그 저항값이 결정된다. The first resistor R1 is three resistors having the same resistance value and is connected in series between the common voltage source VCC and the ground voltage source GND. The first resistor R1 has a voltage VTH on the second node n2.

And the voltage VTL on the third node n3

The resistance value is determined so that.

The first comparator 91 compares the voltage VC1 on the first node n1 with the voltage VTH on the second node n2 so that the voltage VC1 on the first node n1 is equal to the second node n2. When the voltage VTH is greater than), a high logic output signal is generated, while vice versa.

)를 비교하여 제3 노드(n3) 상의 전압(VTL)이 반전된 소스출력인에이블신호(

)보다 클 때 하이논리의 출력신호를 발생하는 반면, 그 반대의 경우에 로우논리의 출력신호를 발생한다. The second comparator 92 has a voltage VTL on the third node n3 and a voltage on the fourth node n4, that is, an inverted source output enable signal (

) Is compared with the source output enable signal in which the voltage VTL on the third node n3 is inverted.

It generates a high logic output signal when is greater than), while a low logic output signal is generated in the reverse case.

When a low logic signal is input to both the reset terminal R and the set terminal S, the RS flip-flop 93 generates a low logic output signal through the non-inverting output terminal Q. In addition, if the low logic signal is input to the reset terminal R and the high logic signal is input to the set terminal S, the RS flip-flop 93 receives the high logic output signal through the non-inverting output terminal Q. On the contrary, a low logic output signal is generated through the non-inverting output terminal Q.

The second resistor R2 and the capacitor C1 connected with the first node n1 interposed therebetween are RS flip-flops 93 with RC time constants adjusted by the adjustment of the resistance value R or the capacitance value C. FIG. The pulse width of the non-inverting output Q and the bit inverting signal BINV of the &quot;

)와 RS 플립플롭(93)의 비반전 출력신호(Q)를 논리곱 연산하여 비트 반전신호(BINV)를 발생하게 된다. The AND gate 94 is an inverted source output enable signal (

) And the non-inverted output signal Q of the RS flip-flop 93 to generate a bit inversion signal BINV.

)보다 낮기 때문에 RS 플립플롭(93)의 리셋단자(R)와 셋트단자(S)에는 로우논리의 입력신호가 인가된다. 이 때, RS 플립플롭(93)의 반전 출력(

)이 하이논리이므로 트랜지스터(Q1)는 턴온(Turn-on)되어 제1 노드(n1) 상의 전압(VC1)을 OV까지 방전시키게 된다. 이어서, 소스출력인에이블신호(SOE)가 하이논리로 변하면, 제2 비교기(92)의 출력이 하이논리로 변하게 되므로 RS 플립플롭(93)의 비반전 출력(Q)은 하이논리가 되고 반전 출력(

)은 로우논리로 변하게 되어 트랜지스터(Q1)를 턴-오프(Turn-off)시키게 된다. 트랜지스터(Q1)가 오프상태를 유지하는 동안, 캐패시터(C1)는 대략 공통전압원의 전위(VCC)까지 전압을 충전하게 되며, 그 전압레벨이 제2 노드(n2) 상의 전압(VTH) 즉,

이상일 때 제1 비교기(91)의 출력이 하이논리로 변한다. 이렇게 제1 비교기(91)의 출력이 하이논리로 변할 때, RS 플립플롭(93)의 비반전 출력(Q)은 로우논리로 변하게 되고 반전 출력(Q)은 하이논리로 변하게 된다. Referring to the operation of the bit controller 86 in conjunction with the waveform diagram of FIG. 10, the first node at an initial time when the source output enable signal SOE remains low and the capacitor C1 starts to charge the voltage. The source output enable signal (V1) in which the voltage VC1 on the nn is lower than the voltage on the second node n2 and the voltage VTL on the third node n3 is reversed.

Since it is lower than), a low logic input signal is applied to the reset terminal R and the set terminal S of the RS flip-flop 93. At this time, the inverted output of the RS flip-flop 93 (

Since the transistor Q1 is turned on, the transistor Q1 is turned on to discharge the voltage VC1 on the first node n1 to OV. Subsequently, when the source output enable signal SOE changes to high logic, the output of the second comparator 92 changes to high logic so that the non-inverting output Q of the RS flip-flop 93 becomes high logic and inverted output. (

) Becomes low logic to turn off the transistor Q1. While transistor Q1 remains off, capacitor C1 charges the voltage to approximately the potential VCC of the common voltage source, whose voltage level is the voltage VTH on the second node n2, i.e.

When abnormal, the output of the first comparator 91 changes to high logic. When the output of the first comparator 91 is changed to high logic, the non-inverted output Q of the RS flip-flop 93 is changed to low logic and the inverted output Q is changed to high logic.

)와 RS 플립플롭(93)의 비반전 출력신호(Q)가 모두 하이논리를 유지하는 기간에만 하이논리의 비트 반전신호(BINV)를 출력한다. The AND gate 94 is an inverted source output enable signal (

) And a high logic bit inversion signal BINV only during a period where both the non-inverted output signal Q of the RS flip-flop 93 maintains high logic.

On the other hand, the pulse width of the bit inversion signal BINV can be adjusted by adjusting the rising time of the voltage VC1 on the first node n1 according to the RC time constant of the resistor R and the capacitor C1 as described above. have.

As a result, the bit inversion signal BINV appears to be the same as delaying the source output enable signal SOE by the pulse width of the source output enable signal SOE. The pulse width of the bit inversion signal BINV may be adjusted to a desired width by adjusting the RC time constant of the monostable multivibrator.

11 to 13 show the data driver 82 in detail.

Referring to FIG. 11, each data IC 82a of the data driver 82 includes a data register 111 to which data RGBeven and RGBodd are input from the timing controller 81, and a shift register for generating a sampling clock. 112, the first latch 113, the second latch 114, and the DAC (connected between the shift register 112 and k (where k is an integer smaller than m) are connected between the data lines DL1 to DLk. 115 and an output circuit 116 and a gamma voltage supply unit 117 connected between the gamma reference voltage generator 84 and the DAC 115.

The data register 111 temporarily stores the odd pixel data RGBodd and the even pixel data RGBeven separated by the timing controller 81 and supplies the stored data RGBodd and RGBeven to the first latch 113. .

The shift register 112 shifts the source start pulse SSP from the timing controller 81 according to the source sampling clock signal SSC to generate a sampling signal. In addition, the shift register 112 shifts the source start pulse SSP to transfer the carry signal CAR to the next stage shift register 112.

The first latch 113 samples the pixel data RGBeven and RGBodd from the data register 111 in response to the sampling signals sequentially input from the shift register 112, latches the data by one line, and then latches the data for one line. Output data at the same time.

The second latch 114 latches data input from the first latch 113, and then simultaneously outputs the latched data in response to the source output enable signal SOE from the timing controller 81.

The DAC 115 inverts the logic value of at least one bit, preferably the most significant bit, MSB, included in the digital data input from the second latch 114 in response to the bit inversion signal BINV, and then inverts the corresponding digital data. Is converted into gamma voltages DGH and DGL from the gamma voltage supply unit 117. The DAC 115 includes a multiplexer for selecting any one of a positive gamma voltage and a negative gamma voltage in response to the polarity control signal POL.

The output circuit 116 includes a buffer connected to each of the data lines. The buffer of the output circuit 116 amplifies the data by its gain value to minimize signal attenuation.

The gamma voltage supplier 117 subdivides the gamma reference voltage input from the gamma reference voltage generator 84 to supply the gamma voltage corresponding to each gray level to the DAC 115. The gamma voltage supply unit 117 is composed of a circuit for generating a gamma voltage of positive polarity and a circuit for generating a gamma voltage of negative polarity.                     

12 shows the positive gamma voltage circuit and the DAC of the gamma voltage supply unit 117 in detail. The negative gamma voltage circuit of the gamma voltage supply unit 117 differs only in the polarity of the gamma reference voltage, and the circuit configuration is substantially the same as that of the positive gamma voltage circuit.

Referring to FIG. 12, the gamma voltage supply unit 117 includes 64 divided resistors R1 to R64 for subdividing the six positive polarity gamma reference voltages VH1 to VH6 into 64 gamma voltages.

The divided resistors R1 to R64 are connected in series by a predetermined number of resistors between the gamma reference voltages of which voltage levels are close, for example, between VH1 and VH2 and between VH2 and VH3. The divided resistors R1 to R64 supply the gamma voltage subdivided into 64 steps corresponding to each gray level to the DAC 115 through an output node between the resistor and the resistor.

The DAC 115 inputs an inverter 121 for inverting data, an exclusive OR gate 124 to which a bit inversion signal BINV and a most significant bit b5 (MSB) are input, and inverted digital data and non-inverted digital data are input. Consisting of a decoder 122.

The exclusive OR gate 124 performs an exclusive OR operation on the bit inversion signal BINV and the most significant bit b5 (MSB) of the digital data so as to generate a logic value of the most significant bit b5 (MSB) when the bit inversion signal BINV occurs in high logic. Reversed. In addition, the exclusive OR gate 124 maintains the value of the most significant bit b5 (MSB) as the original value when the bit inversion signal BINV is low logic.

The decoder 122 is combined with a plurality of switch elements 123 for switching signal paths in response to inverted data or non-inverted data to select a gamma voltage corresponding to a logic value of digital data. 13 shows the switch elements 123 shown in detail.

As can be seen from Fig. 13, the output terminal of the exclusive OR gate 124 is commonly connected to the most significant bit inverting switch and the most significant bit non-inverting switch. When the logical value of the 6-bit digital data input from the second latch 114 to the DAC 115 is '111111', the most significant bit is inverted at the initial time of every horizontal period in which the bit inversion signal BINV is generated. Since the switch and the non-inverting switch for the most significant bit are turned on at the same time, a gamma voltage V32 corresponding to the gray value '32' is selected along two current paths indicated by dotted lines. In other words, at the initial time of every horizontal period in which the bit inversion signal BINV is generated, the logic value of the most significant bit b5 of the digital data '111111' corresponding to the gray scale value '64' is inverted to correspond to the gray scale value '32'. The gamma voltage V32 is selected. The selected gamma voltage V32 is supplied to the data line DL through the buffer 116a.

14 is a waveform diagram illustrating a one dot inversion method of a method and apparatus for driving an LCD according to an exemplary embodiment of the present invention.

Referring to FIG. 14, the method and apparatus for driving the liquid crystal display according to the exemplary embodiment of the present invention only the most significant bit MSB of the digital data every horizontal period in response to the polarity inversion signal BINV in the one dot inversion scheme. After the inversion, the most significant bit MSB converts the inverted digital data into a gamma voltage. The polarity of the data voltage supplied to the liquid crystal cell is reversed every one horizontal period. The data voltage supplied to the liquid crystal cell is changed to an intermediate voltage level during the period of change from negative polarity to positive polarity, that is, during bit inversion signal BINV, and then to a desired voltage level. In addition, the data voltage supplied to the liquid crystal cell is changed to an intermediate voltage level during a period of change from positive polarity to negative polarity, that is, during bit inversion signal BINV, and then to a desired voltage level. In other words, the voltage level of the data voltage supplied to the liquid crystal cell during polarity inversion is gradually changed in two steps. As a result, noise due to surge voltage or surge current, which may occur when the data voltage level changes rapidly in the one-dot inversion method, may be prevented, and the load of the liquid crystal cell due to the sudden change in the voltage level may be prevented. Can be reduced.

15 is a waveform diagram illustrating a two-dot inversion method of a method and apparatus for driving a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 15, the method and apparatus for driving the liquid crystal display according to the exemplary embodiment of the present invention are digital data every horizontal period in response to the polarity inversion signal BINV, similarly to the one dot inversion method in the two dot inversion method. After inverting only the most significant bit MSB, the most significant bit MSB converts the inverted digital data into a gamma voltage. The polarity of the data voltage supplied to the liquid crystal cell is reversed every two horizontal periods. The data voltage supplied to the liquid crystal cell is at an intermediate voltage level in response to the bit inversion signal BINV during the period of changing from negative to positive and the initial period of maintaining the positive voltage on the next horizontal line. After changing to, it changes to the desired voltage level. In addition, the data voltage supplied to the liquid crystal cell is changed to the intermediate voltage level in response to the bit inversion signal BINV during the period of changing from the positive polarity to the negative polarity and the initial period of maintaining the negative voltage. The desired voltage level is changed. In other words, the voltage level of the data voltage supplied to the liquid crystal cell gradually changes in two steps when the polarity is inverted, and then falls or rises to the desired level in the next horizontal line which maintains the polarity and then changes to the desired level. do. As a result, the noise due to the surge voltage or the surge current can be prevented in the 2-dot inversion method, and the load of the liquid crystal cell due to the sudden change in the voltage level can be reduced, and the data of the same polarity can be continuously supplied. It is possible to reduce the luminance difference between the two horizontal lines.

14 and 15, VGn and VGn + 1 represent scan pulses supplied to the n-th gate line and scan pulses supplied to the n + 1th gate line, respectively, and POL represents a polarity control signal.

14 and 15, the pulse width period T of the bit inversion signal BINV and the intermediate voltage level period of the data voltage Data-post supplied to the liquid crystal cell are the bit controllers 86 as described above. Can be optimally adjusted according to the RC time constant of

As described above, the method and apparatus for driving a liquid crystal display according to the present invention inverts at least one bit included in the digital data, and then converts the digital data into an analog gamma voltage. As a result, the method and apparatus for driving a liquid crystal display according to the present invention changes the data voltage level by two steps whenever the polarity of the data voltage is reversed in the one-dot or two-dot inversion scheme, thereby causing a sudden change in the data voltage and the liquid crystal. By preventing the sudden load change of the cell, the noise is minimized and the image quality is improved by reducing the luminance difference between two horizontal lines to which the data voltage of the same polarity is applied in the 2-dot inversion method. The method and apparatus for driving a liquid crystal display device according to the present invention can be applied not only to a liquid crystal display device but also to any display device that displays an image by converting digital data into an analog voltage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, in the exemplary embodiment of the present invention, the inversion of only one bit of the most significant bit is illustrated. However, the data voltage supplied to the liquid crystal cell may be changed in multiple steps by inverting two or more bits or other bits other than the most significant bit. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

Inputting digital data, Generating a bit inversion signal; Inverting at least one bit in the digital data in response to the bit inversion signal; Converting the at least one bit inverted digital data into an analog voltage; And supplying the analog voltage to the liquid crystal cell. The method of claim 1, The voltage supplied to the liquid crystal cell is a driving method of the liquid crystal display device, characterized in that the polarity is reversed every horizontal period. The method of claim 1, The voltage supplied to the liquid crystal cell is a driving method of the liquid crystal display device, characterized in that the polarity is reversed every two horizontal periods. The method of claim 1, And the bit inversion signal is generated at the beginning of every horizontal period. The method of claim 1, And the bit inverted in the digital data is the most significant bit. A bit controller for generating a bit inversion signal, And a data driver for inverting at least one bit from the digital data supplied through an input line in response to the bit inversion signal, and then converting the at least one bit inverted digital data into an analog voltage to supply the liquid crystal cell. A drive device for a liquid crystal display device, characterized in that. The method of claim 6, The voltage supplied to the liquid crystal cell is a driving device of the liquid crystal display device, characterized in that the polarity is reversed every horizontal period. The method of claim 6, The voltage supplied to the liquid crystal cell is a driving device of the liquid crystal display device, characterized in that the polarity is reversed every two horizontal periods. The method of claim 6, And the bit inversion signal is generated at the beginning of every horizontal period. The method of claim 6, And the bit inverted in the digital data is the most significant bit. The method of claim 6, A liquid crystal panel in which a plurality of data lines and a plurality of gate lines cross each other, switch elements are formed at intersections thereof, and the liquid crystal cell is formed in a pixel region between the data line and the gate line; A gate driver for supplying scan pulses to the gate lines; And a timing controller for supplying the digital data to the data driver and generating timing control signals required for the data driver and the gate driver. The method of claim 11, And the bit controller generates the bit inversion signal by delaying a source output enable signal (SOE) input from the timing controller. The method of claim 6, And the bit controller is a monostable multivibrator.

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