KR101070555B1 - Liquid crystal display device - Google Patents

Abstract

Disclosed are a liquid crystal display device which reduces power consumption and improves image quality.

In the liquid crystal display of the present invention, first and second charge count voltages different from each other are supplied to charge count sections between data voltages. The first and second charge count voltages may be supplied by a data driver or a gamma voltage generator. The gamma voltage generator may set some of the gamma voltages as the first and second charge count voltages. Both the first and second charge count voltages may be supplied to the charge count period, or the first and second charge count voltages may be alternately supplied to each charge count period.

Therefore, according to the present invention, since a predetermined charge count voltage is supplied to approach the data voltage before the data voltage is supplied, the current consumption can be reduced and the image quality can be improved.

LCD, Charge Counting Voltage, Charge Counting Section, Power Consumption

Description

Liquid crystal display device             

1 is a view showing a voltage waveform for driving a liquid crystal panel of a general liquid crystal display device.

2 is a block diagram showing the configuration of a liquid crystal display according to a first preferred embodiment of the present invention.

3 is a waveform diagram for driving the liquid crystal display of FIG.

4 is a block diagram showing the configuration of a liquid crystal display according to a second preferred embodiment of the present invention.

FIG. 5 is a diagram illustrating the gamma voltage generator of FIG. 4 in detail; FIG.

6 is a block diagram showing the configuration of a liquid crystal display according to a third preferred embodiment of the present invention.

FIG. 7 is a waveform diagram for driving the liquid crystal display of FIG. 6. FIG.

8 is a block diagram showing the configuration of a liquid crystal display according to a fourth preferred embodiment of the present invention.

9 is a view illustrating in detail the gamma voltage generator of FIG. 8;

<Explanation of symbols for the main parts of the drawings>                 

1, 31: control unit 3, 33: timing controller

5: SOE variable part 7: POL variable part

9, 39: gate driver 11, 19, 35, 43: data driver

13, 37, 48: Charge count voltage output part 15, 41: liquid crystal panel

17, 43: charge counting voltage generator 21, 45: gamma voltage generator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing power consumption and improving image quality.

In recent years, liquid crystal display devices having a thin shape, light weight, and low power consumption have been in the spotlight.

The liquid crystal display displays a predetermined image by controlling the light transmittance of the liquid crystals by displacing the liquid crystals between the two substrates according to the electric field according to the digital data signal.

To this end, the liquid crystal display device includes a liquid crystal panel for displaying an image, gate and data drivers for driving the liquid crystal panel, and a timing controller for controlling the drivers.

The liquid crystal panel displays an image in response to a waveform as shown in FIG.                         

1 is a view showing a voltage waveform for driving a liquid crystal panel of a general liquid crystal display device.

As shown in FIG. 1, the timing controller generates a first control signal (GSC, GSP, GOE, etc.) and a second control signal (SSC, SSP, SOE, POL, etc.) for controlling the gate and data drivers. do. The first control signal is supplied to the gate driver, and the second control signal is supplied to the data driver together with a predetermined digital data signal.

The gate driver sequentially generates a scan voltage in response to the first control signal and supplies the scan voltage to gate lines of the liquid crystal panel. For example, a first scan voltage may be supplied to the first gate line of the liquid crystal panel, and a second scan voltage may be supplied to the second gate line of the liquid crystal panel. In this case, a predetermined section having a low voltage is present by the GOE signal between the first and second scan voltages. Accordingly, each scan voltage can be correctly supplied to each gate line of the liquid crystal panel.

The data driver inverts the analog data voltage according to the digital data signal according to the second control signal according to the POL signal and supplies them to the data lines of the liquid crystal panel. Although FIG. 1 illustrates one-dot inversion driving, a data voltage may be supplied by two-dot inversion driving, line inversion driving, and frame inversion driving as needed. In the case of 1-dot inversion driving, the positive data voltage and the negative data voltage are alternately supplied.                         

In this case, a charge share voltage exists between the positive data voltage and the negative data voltage. The charge count voltage is controlled by the SOE signal to distinguish each data voltage. That is, when the SOE signal goes high, the data driver outputs a charge count instead of outputting a data voltage. The section in which the voltage is counted and output is named as the counting section. Since the charge count section in which the charge count voltage is output is not supplied with the scan voltage, the charge count voltage is only output and is not actually applied to the pixels of the liquid crystal panel.

Typically, the charge count voltage may be generated in the data driver and output under the control of the SOE signal.

Accordingly, the positive data voltage is supplied, the charge count voltage is output during the charge count period, and then the negative data voltage is supplied. Subsequently, after the charge counting voltage is outputted during the charge counting period, the positive data voltage is supplied. As such, the voltage may be counted during the charge counting period indicating between the positive data voltage and the negative data voltage or between the negative data voltage and the positive data voltage. .

The charge counting voltage generally has a voltage similar to a common voltage which is a reference for the positive data voltage and the negative data voltage.

The data voltage actually changes from time to time by representing the gray level of the data. For example, the first to fourth data voltages may be supplied at + 3.5V, -2.7V, + 5.7V, and -5.2V for a specific pixel. Therefore, to supply each data voltage, increase from +3 to + 3.5V from the charge count voltage, then decrease to charge count voltage, increase to -2.7V, then decrease to charge count voltage, increase to + 5.7V, then charge Reduce to voltage, increase to -5.2V, then decrease to charge count voltage. As described above, in order to supply each data voltage, an operation of repeatedly increasing the charge count voltage to the corresponding data voltage is repeatedly performed.

In such a case, a considerable time is required to increase from the charge counting voltage to a data voltage having a large voltage difference from the charge counting voltage. As such a considerable time is required, there is a problem in that the image quality is deteriorated because it is impossible to charge a desired gradation to the corresponding pixel of the liquid crystal panel. In other words, the gray scale lower than the desired gray scale is expressed, resulting in poor image quality.

In addition, there is a problem in that a significant current is consumed in order to increase the charge count voltage from the charge count voltage to a large data voltage, thereby increasing power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device which can reduce power consumption and improve image quality by varying the charge count voltage.

According to a preferred embodiment of the present invention for achieving the above object, the liquid crystal display market value, the liquid crystal panel for displaying an image; A gate driver for supplying a scan voltage to the liquid crystal panel; And a data driver for alternately supplying data voltages for displaying the image to the liquid crystal panel and supplying predetermined first and second charge count voltages for each charge count period between the data voltages.

According to another preferred embodiment of the present invention, a liquid crystal display device includes a liquid crystal panel for displaying an image; A gate driver for supplying a scan voltage to the liquid crystal panel; A data driver for alternately supplying data voltages for displaying the image to the liquid crystal panel; And a gamma voltage generator for supplying predetermined first and second charge count voltages in each charge count period between the data voltages.

The gamma voltage generator may set a gamma voltage of one of the positive gamma voltages as a first charge count voltage and set a gamma voltage of one of the negative gamma voltages as a second charge count voltage.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing the configuration of a liquid crystal display according to a first embodiment of the present invention.

In FIG. 2, the liquid crystal display according to the first exemplary embodiment of the present invention includes a controller 1, a charge counting voltage generator 17, a gate driver 9, a data driver 11, and a liquid crystal panel 15. Equipped.

The digital data voltage supplied from the outside (not shown) is supplied to the controller 1. The controller 1 includes a timing controller 3 for generating a predetermined timing control signal using vertical / horizontal synchronization signals Vsync and Hsync extracted from the digital data signal. The timing control signal includes first control signals (GSC, GSP, GOE, etc.) for controlling the gate driver 9 and second control signals (SSC, SSP, SOE, POL) for controlling the data driver 11. And the like). The timing controller 3 supplies the first control signal to the gate driver 9 and the second control signal together with the digital data signal to the data driver 11.

The control unit 1 uses the SOE variable unit 5 for varying the SOE signal among the second control signals, and the polarity signal POL by using the SOE signal SOE 'varied in the SOE variable unit 5. It may further include a POL variable portion 7 for varying the. The SOE signal is a signal for controlling the output of the charge count voltage during the charge count period. When the SOE signal is high, the charge count voltage is output, and when the SOE signal is low, the charge count voltage is not output. That is, when the SOE signal is low, a predetermined data voltage (having positive or negative polarity) may be output.

The SOE variable part 5 generates the variable SOE signal SOE 'by varying the SOE signal. That is, the SOE variable part 5 divides the high state section of the SOE signal in half to generate a voltage in the low state during the first section and generates the voltage in the high state during the second section.

The POL variable unit 7 generates the variable polarity signal POL 'by varying the polarity signal POL using the variable SOE signal SOE'. That is, the POL variable part 7 is variable in synchronization with the voltage of the high state of the variable SOE signal SOE '. For example, as shown in FIG. 3, the variable polarity signal POL ′ generates a high state voltage in synchronization with a variable SOE signal SOE ′ of a high state voltage, and generates a voltage of a next high state voltage. The low voltage is generated in synchronization with the variable SOE signal SOE '. Accordingly, the variable polarity signal POL 'is changed to a high state voltage or a low state voltage in the charge counting period, thereby extending the polarity signal section to the charge counting period.

The polarity signal POL ′ thus varied is supplied to the data driver 11 together with the SOE signal.

The gate driver 9 sequentially generates a scan voltage in response to the first control signal supplied from the timing controller 3 and supplies the scan voltage to the gate lines of the liquid crystal panel 15.

The charge count voltage generator 17 generates first and second charge count voltages Vsh1 and Vsh2 which are different from each other. In the present invention, the first charge count voltage Vsh1 is greater than the second charge count voltage Vsh2 for convenience of description. Importantly, the first and second charge counting voltages Vsh1 and Vsh2 have different voltages, and one of them is larger than the other voltage. For example, the first charge count voltage Vsh1 may be higher than the common voltage by a predetermined voltage, and the second charge count voltage Vsh2 may be lower than the common voltage by a predetermined voltage. In this case, the first charge count voltage and the second charge count voltage may be symmetrical with respect to the common voltage. For example, when the common voltage is 2.4V and the predetermined voltage is 2V, the first charge count voltage Vsh1 may be 4.4V and the second charge count voltage Vsh2 may be 0.4V.

The first and second charge count voltages may be generated using voltage division based on a power supply voltage VDD. Generating the first and second charge count voltages using voltage division can be easily obtained, and further description thereof will be omitted.

The first and second charge count voltages Vsh1 and Vsh2 are supplied to the data driver 11.

The data driver 11 gamma-converts the digital data signal according to the second control signal supplied from the timing controller 3 to supply a predetermined analog data voltage to the data lines of the liquid crystal panel 15. In this case, the analog data voltage is converted into a positive data voltage or a negative data voltage according to the polarity signal POL supplied from the timing controller 3 and supplied to the liquid crystal panel 15. do. In this case, there is a charge counting section in which a charge counting voltage is supplied between the positive data voltage and the negative data voltage.

To this end, the data driver 11 outputs a charge count voltage output unit for outputting the first and second charge count voltages according to a combination of the SOE signal supplied from the controller 1 and the variable polarity signal POL ′. (13) is provided.

The data driver 11 outputs a positive (+) data voltage or a negative (-) data voltage in a normal period other than the charge count period, and in the charge count period, the first and second count voltages Vsh1 and Vsh2. Outputs

The data driver 11 may include a shift register, a latch, a digital analog converter, and a buffer to output the positive data voltage or the negative data voltage. In addition, the data driver 11 may include a charge count voltage output unit 13 to output the first and second charge count voltages Vsh1 and Vsh2 during the charge count period.

After the negative data voltage is previously output, the first and second charge count voltages Vsh1 and Vsh2 may be output during the first charge count period. The output of the first and second charge count voltages may be controlled by a combination of the SOE signal and the variable polarity signal POL ′ signal.

When the negative data voltage is previously output, the SOE signal becomes' 1 'during the first period of the first charge count period, and the variable polarity signal POL' becomes' 0 '. Accordingly, the charge count voltage output unit selects and outputs the second charge count voltage Vsh2 based on a signal of '10' which is a combination of the SOE signal and the variable polarity signal POL '. On the other hand, the SOE signal becomes' 1 'and the variable polarity signal POL' becomes' 1 'during the second period of the first charge count period. Accordingly, the charge count voltage output unit selects and outputs the first charge count voltage Vsh1 based on a signal '11' which is a combination of the SOE signal and the variable polarity signal POL '.

Therefore, when the combination of the SOE signal and the variable polarity signal POL 'is' 10', the charge count voltage output unit 13 outputs the second charge count voltage Vsh2 and '11'. In this case, the first charge count voltage Vsh1 is output.

After the first charge count period has passed, a positive data voltage is output, followed by a first charge count voltage Vsh1 and a second charge count voltage during the first and second periods of the second charge count period. It can be output in the order of Vsh2). After the second charge count period passes and the negative data voltage is output, the second charge count period may be output in the order of the second charge count voltage Vsh2 and the first charge count voltage Vsh1 during the third charge count period. have.

As such, the charge count voltage output unit 13 may determine the first and second charge count voltages Vsh1 and Vsh2 depending on whether the previously output data voltage is a positive data voltage or a negative data voltage. ) May be output in the order of the second and first charge count voltages Vsh2 and Vsh1.

Accordingly, the present invention outputs the first charge count voltage Vsh1 that is greater than the common voltage before the positive data voltage is output, and the common voltage before the negative data voltage is output. By outputting the smaller second charge count voltage Vsh2, it can be easily transitioned to a desired data voltage. The present invention can be easily shifted from the positive data voltage to the first charge count voltage Vsh1 or from the negative data voltage to the second charge count voltage Vsh2. .

Therefore, the present invention can reduce the power consumption and improve the image quality by outputting the first and second charge count voltages during the charge count period.

In the present invention, the charge count voltage generator 17 generates the first and second charge count voltages, and generates the first and second charge counts according to a combination of an SOE signal and the variable polarity signal POL ′. Output voltage.                     

Meanwhile, the first and second charge count voltages may be replaced with predetermined gamma voltages generated by the gamma voltage generator.

4 is a block diagram showing the configuration of a liquid crystal display according to a second preferred embodiment of the present invention.

In FIG. 4, the liquid crystal display according to the second exemplary embodiment of the present invention includes a controller 1, a gamma voltage generator 21, a gate driver 9, a data driver 19, and a liquid crystal panel 15. do. The controller 1, the gate driver 9, the data driver 19, and the liquid crystal panel 15 are the same as in the first embodiment of the present invention, and thus detailed description thereof will be omitted.

The controller 1 generates a first control signal (GSC, GSP, GOE, etc.), a second control signal (SSC, SSP, SOE, POL, etc.), a variable polarity signal (POL '). The first control signal is supplied to the gate driver 9, the second control signal is supplied to the data driver 19, and the SOE signal and the variable polarity signal POL ′ are supplied to the gamma voltage generator ( 21).

As shown in FIG. 5, the gamma voltage supply unit 21 includes a positive gamma voltage generator 23, a negative gamma voltage generator 25, and a charge count voltage output unit 27. The positive gamma voltage generator 23 generates a plurality of positive gamma voltages. The negative gamma voltage generator 25 generates a plurality of negative gamma voltages. The plurality of positive gamma voltages and the plurality of negative gamma voltages are supplied to the data driver 19 to convert a predetermined digital data signal into an analog data voltage.

In this case, one of the plurality of positive gamma voltages may be set as a first charge count voltage, and one of the plurality of negative gamma voltages may be set as a second charge count voltage. The set first and second charge count voltages are supplied to the charge count voltage output unit 27.

The charge count voltage output unit 27 selectively outputs the first and second charge count voltages using a combination of an SOE signal having a waveform as shown in FIG. 3 and a variable polarity signal POL ′. . The first charge count voltage may be greater than the common voltage, and the second charge count voltage may be less than the common voltage. Since the charge counting voltage output unit 27 has already been described in detail, further description thereof will be omitted.

The data driver 19 converts a predetermined digital data signal into a gamma voltage supplied from the gamma voltage generator 21 according to a polarity signal POL according to the second control signal supplied from the controller 1. Output analog data voltage. For example, when the polarity signal POL is positive, a positive data voltage obtained by converting the digital data signal into a positive gamma voltage supplied from the gamma voltage generator is output, and the polarity signal ( When POL) is negative, a negative data voltage obtained by converting the digital data signal into a negative gamma voltage supplied from the gamma voltage generator is output.

In this case, the gamma voltage is generated during the charge counting period between the positive data voltage and the negative data voltage or between the negative data voltage and the positive data voltage. The first and second charge count voltages are selectively output from the charge count voltage output unit of the unit 21.                     

For example, in the charge counting period between the positive data voltage and the negative data voltage, the first and second charge count voltages are output in the order of the first and second charge count voltages. In the charge count period between the positive data voltage and the positive data voltage, the second and first charge count voltages may be output in the order of the second and first charge count voltages.

As described above, the present invention outputs the first charge count voltage Vsh1 that is greater than the common voltage before the positive data voltage is output, and before the negative data voltage is output. By outputting the second charge count voltage Vsh2 which is smaller than the common voltage, it is easily transitioned to a desired data voltage, thereby reducing power consumption and improving image quality.

In the present invention, the first and second charge count voltages are selectively output during the charge count period.

Meanwhile, only one charge count voltage of the first and second charge count voltages may be output during the charge count period. For example, a first charge count voltage greater than the common voltage is output during the first charge count period before the positive data voltage is output, and common during the second charge count period before the negative data voltage is output. The second charge counting voltage smaller than the voltage may be output. As such, the first and second charge count voltages may be alternately output in each charge count period.

6 is a block diagram showing the configuration of a liquid crystal display according to a third embodiment of the present invention.

In FIG. 6, the liquid crystal display according to the third exemplary embodiment of the present invention includes a controller 31, a gate driver 39, a charge count voltage generator 43, a data driver 35, and a liquid crystal panel 41. It is provided.

The digital data voltage supplied from the outside (not shown) is supplied to the controller 31. The controller 31 includes a timing controller 33 for generating a predetermined timing control signal using the vertical / horizontal synchronization signals Vsync and Hsync extracted from the digital data signal. The timing control signal includes first control signals (GSC, GSP, GOE, etc.) for controlling the gate driver 39 and second control signals (SSC, SSP, SOE, POL) for controlling the data driver 35. And the like). The timing controller 33 supplies the first control signal to the gate driver 39, and supplies the second control signal to the data driver 35 together with the digital data signal. In addition, the timing controller 33 charges the SOE signal and the POL signal of the second control signal to the voltage output unit 37 of the data driver 35.

The gate driver 39 sequentially generates a scan voltage in response to the first control signal supplied from the timing controller 33 and supplies the scan voltage to the gate lines of the liquid crystal panel 41.

The charge count voltage generator 43 generates first and second charge count voltages Vsh1 and Vsh2 which are different from each other. In the present invention, the first charge count voltage Vsh1 is greater than the second charge count voltage Vsh2 for convenience of description. Importantly, the first and second charge counting voltages Vsh1 and Vsh2 have different voltages, and one of them is larger than the other voltage. For example, the first charge count voltage Vsh1 may be higher than the common voltage by a predetermined voltage, and the second charge count voltage Vsh2 may be lower than the common voltage by a predetermined voltage. In this case, the first charge count voltage and the second charge count voltage may be symmetrical with respect to the common voltage.

The first and second charge count voltages may be generated using voltage division based on a power supply voltage VDD. Generating the first and second charge count voltages using voltage division can be easily obtained, and further description thereof will be omitted.

The first and second charge count voltages Vsh1 and Vsh2 are supplied to the data driver 35.

The data driver 35 gamma-converts the digital data signal according to the second control signal supplied from the timing controller 33 to supply a predetermined analog data voltage to the data lines of the liquid crystal panel 41. In this case, the analog data voltage is converted into a positive data voltage or a negative data voltage according to the polarity signal POL supplied from the timing controller 33 and supplied to the liquid crystal panel. In this case, there is a charge counting section in which a charge counting voltage is supplied between the positive data voltage and the negative data voltage.

To this end, the data driver 35 includes a charge count voltage output unit 37 for outputting the first and second charge count voltages according to a combination of the SOE signal and the POL signal supplied from the controller 31. .

The data driver 35 outputs a positive (+) data voltage or a negative (-) data voltage in a normal period other than the charge count period, and in the charge count period, the first and second count voltages Vsh1 and Vsh2. )

The data driver 35 may include a shift register, a latch, a digital analog converter, and a buffer to output the positive data voltage or the negative data voltage. In addition, the data driver 35 may include a charge count voltage output unit 37 to output the first and second charge count voltages Vsh1 and Vsh2 during the charge count period.

After the negative data voltage is previously output, the first and second charge count voltages Vsh1 and Vsh2 may be output during the first charge count period. The output of the first and second charge count voltages may be controlled by a combination of the SOE signal and the POL signal.

As illustrated in FIG. 7, when the negative data voltage is previously output, the SOE signal becomes '1' and the POL signal becomes '0' during the first charge count period. Accordingly, the charge count voltage output unit 37 selects and outputs the first charge count voltage Vsh1 based on a signal of '10', which is a combination of the SOE signal and the POL signal. After the first charge count voltage Vsh1 is output during the first charge count period, a positive data voltage is output. During the second charge counting period between the positive data voltage and the next negative data voltage, the SOE signal becomes '1' and the POL signal becomes '1'. Accordingly, the charge count voltage output unit 37 selects and outputs the second charge count voltage Vsh2 based on a signal '11' which is a combination of the SOE signal and the POL signal.

Accordingly, the charge count voltage output unit 37 outputs the first charge count voltage Vsh1 during a first charge count period in which the combination of the SOE signal and the POL signal is '10', and generates a '11'. During the second charge counting period, the second charge counting voltage Vsh2 is output. Similarly, the first charge count voltage Vsh1 may be output during the third charge count period, and the second charge count voltage Vsh2 may be output during the fourth charge count period.

As such, when the previously charged data voltage is the negative data voltage, the charge count voltage output unit 37 outputs the first charge count voltage Vsh1 and the previously output data voltage is positive. In the case of a positive data voltage, the second charge count voltage Vsh2 may be output.

Therefore, in the present invention, the second charge counting voltage Vsh2 smaller than the common voltage is output before the negative data voltage is output, and the first charge greater than the common voltage before the positive data voltage is output. By counting the output voltage Vsh1, the desired gradation can be easily obtained, so that the image quality can be improved, and the power consumption can be reduced because the current for obtaining the desired gradation is reduced.

8 is a block diagram showing a configuration of a liquid crystal display according to a fourth preferred embodiment of the present invention.

In FIG. 8, the liquid crystal display according to the fourth exemplary embodiment of the present invention includes a control unit 31, a gate driver 39, a gamma voltage generator 45, a data driver 43, and a liquid crystal panel 41. do. Since the controller 31, the gate driver 39, the data driver 43, and the liquid crystal panel 41 are the same as those in FIG. 6, further description thereof will be omitted.                     

The gamma voltage generator 45 receives the SOE signal and the POL signal from the timing controller 33 of the controller 31, and determines one of the first and second charge count voltages according to the combination of the SOE signal and the POL signal. Selective output of charge count voltage.

As shown in FIG. 9, the gamma voltage generator 45 includes a positive gamma voltage generator 46, a negative gamma voltage generator 47, and a charge count output unit 48.

The positive gamma voltage generator 46 generates a plurality of positive gamma voltages. The negative gamma voltage generator 47 generates a plurality of negative gamma voltages. The plurality of positive gamma voltages and the plurality of negative gamma voltages are supplied to the data driver 43.

In this case, one of the plurality of positive gamma voltages may be set as a first charge count voltage, and one of the plurality of negative gamma voltages may be set as a second charge count voltage. The set first and second charge count voltages are supplied to the charge count voltage output unit 48.

The charge count voltage output unit 48 selectively outputs the first and second charge count voltages using a combination of an SOE signal and a POL signal having a waveform as shown in FIG. 7. The first charge count voltage may be greater than the common voltage, and the second charge count voltage may be less than the common voltage. Since the charge counting voltage output unit 48 has already been described in detail, further description thereof will be omitted. For example, when '10' is a combination signal of the SOE signal of '1' and the POL signal of '0' during the first charge counting period, the first charge counting voltage Vsh1 is output and during the second charge counting period. In the case of '11' which is a combination signal of the SOE signal of '1' and the POl signal of '1', the second charge count voltage Vsh2 may be output.

The data driver 43 converts a predetermined digital data signal into a gamma voltage supplied from the gamma voltage generator 45 according to a polarity signal POL according to the second control signal supplied from the controller 31. Output analog data voltage. For example, when the polarity signal POL is positive, a positive data voltage obtained by converting the digital data signal into a positive gamma voltage supplied from the gamma voltage generator is output, and the polarity signal ( When POL) is negative, a negative data voltage obtained by converting the digital data signal into a negative gamma voltage supplied from the gamma voltage generator is output.

In this case, a first charge count voltage Vsh1 is selectively output during the first charge count period between the negative data voltage and the positive data voltage and the positive data voltage. The second charge count voltage Vsh2 may be selectively output during the second charge count period that is between and a next negative data voltage.

Accordingly, in the present invention, when the predetermined gamma voltage of the gamma voltage generator 45 is set to the first and second charge count voltages, the first and second charge count voltages are selectively selected according to the combination of the SOE signal and the POL signal. By outputting the power, the power consumption can be reduced and the image quality can be improved.

 As described above, according to the present invention, the first and second charge count voltages are simultaneously output for each charge count period, thereby reducing power consumption and improving image quality.

According to the present invention, the first charge count voltage or the second charge count voltage is selectively output for each charge count period, thereby reducing power consumption and improving image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

A liquid crystal panel for displaying an image; A gate driver for supplying a scan voltage to the liquid crystal panel; Alternately supplying positive and negative data voltages for displaying the image to the liquid crystal panel, and charging first and second charges higher and lower than a common voltage for each charge interval between the positive and negative data voltages. A data driver for supplying a counting voltage; And A first control signal for controlling the gate driver, a second control signal including at least an SOE signal and a first polarity signal for controlling the data driver, and a supply for controlling the supply of the first and second charge count voltages; 3 Control unit for generating control signals Including, And the third control signal comprises the SOE signal and a second polarity signal generated from the SOE signal and the first polarity signal. A liquid crystal panel for displaying an image; A gate driver for supplying a scan voltage to the liquid crystal panel; Alternately supplying positive and negative data voltages for displaying the image to the liquid crystal panel, and charging first and second charges higher and lower than a common voltage for each charge interval between the positive and negative data voltages. A data driver for supplying a charge count voltage of one of the count voltages; And A first control signal for controlling the gate driver, a second control signal including at least an SOE signal and a polarity signal for controlling the data driver, and a third control for controlling the supply of the first and second charge count voltages; Control to generate a signal Including, And the third control signal comprises the SOE signal and the polarity signal. The liquid crystal display of claim 1, wherein the first and second charge count voltages are sequentially supplied to each charge count period by a combination of the SOE signal and the second polarity signal. delete 4. The method of claim 3, wherein when the positive data voltage and the negative data voltage are supplied before and after the charge count period, the first charge count voltage greater than the common voltage and the second charge less than the common voltage during the charge count period. The liquid crystal display device, characterized in that supplied in the order of the counting voltage. 4. The method of claim 3, wherein when the negative data voltage and the positive data voltage are supplied before and after the charge count period, the second charge count voltage smaller than the common voltage and the first charge greater than the common voltage during the charge count period. The liquid crystal display device, characterized in that supplied in the order of the counting voltage. 3. The liquid crystal display of claim 2, wherein a charge count voltage of one of the first and second charge count voltages is selected and supplied for each charge count period by a combination of the SOE signal and the polarity signal. 4. The liquid crystal display of claim 7, wherein when the positive data voltage and the negative data voltage are supplied before and after the charge count period, the second charge count voltage smaller than the common voltage is supplied during the charge count period. Device. 8. The liquid crystal display of claim 7, wherein when the negative data voltage and the positive data voltage are supplied before and after the charge count period, the first charge count voltage greater than the common voltage is supplied during the charge count period. Device. The liquid crystal display of claim 1, further comprising a charge count voltage generator configured to generate the first and second charge count voltages. A liquid crystal panel for displaying an image; A gate driver for supplying a scan voltage to the liquid crystal panel; A data driver for alternately supplying positive and negative data voltages for displaying the image on the liquid crystal panel; And At least one charge count voltage of the first and second charge count voltages higher and lower than the common voltage for each charge count period between the positive and negative data voltages and generating positive gamma voltages and negative gamma voltages; Gamma voltage generator to supply Including, And the first and second charge count voltages are a positive gamma voltage of one of the positive gamma voltages and a negative gamma voltage of one of the negative gamma voltages. 12. The control circuit of claim 11, wherein the first control signal for controlling the gate driver, the second control signal including at least an SOE signal and a first polarity signal for controlling the data driver, and the first and second charge count voltages. A control unit for generating a third control signal for controlling the supply of More, And the third control signal comprises the SOE signal and a second polarity signal generated from the SOE signal and the first polarity signal. The liquid crystal display of claim 12, wherein the first and second charge count voltages are sequentially supplied to each charge count period by a combination of the SOE signal and the second polarity signal. 15. The method of claim 13, wherein when the positive data voltage and the negative data voltage are supplied before and after the charge count period, the first charge count voltage greater than the common voltage and the second charge less than the common voltage during the charge count period. The liquid crystal display device, characterized in that supplied in the order of the counting voltage. 15. The method of claim 13, wherein when the negative data voltage and the positive data voltage are supplied before and after the charge count period, the second charge count voltage smaller than the common voltage and the first charge greater than the common voltage during the charge count period. The liquid crystal display device, characterized in that supplied in the order of the counting voltage. 13. The method of claim 12, wherein a first control signal for controlling the gate driver, a second control signal including at least an SOE signal and a polarity signal for controlling the data driver, and the first and second charge count voltages are supplied. A control unit for generating a third control signal for controlling the More, And the third control signal comprises the SOE signal and the polarity signal. 17. The liquid crystal display of claim 16, wherein one charge count voltage of the first and second charge count voltages is selected and supplied for each charge count period by a combination of the SOE signal and the polarity signal. delete 18. The liquid crystal display of claim 17, wherein when the positive data voltage and the negative data voltage are supplied before and after the charge count period, the second charge count voltage smaller than the common voltage is supplied during the charge count period. Device. 18. The liquid crystal display of claim 17, wherein when the negative data voltage and the positive data voltage are supplied before and after the charge count period, the first charge count voltage greater than the common voltage is supplied during the charge count period. Device.

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