JP5100450B2 - Image display apparatus and driving method thereof - Google Patents

Description

  The present invention relates to an image display device and a driving method thereof.

  In recent years, various drive methods have been developed for image display devices such as liquid crystal display devices for the purpose of improving image quality. One driving method of an image display device (active matrix image display device) using an active element (for example, TFT: thin film transistor) is a driving method in which a gate line is activated before the timing of writing data to a pixel. This driving method is also referred to as an overlap scan driving method, and a gate pulse for activating a gate line is overlapped with each other between adjacent gate lines, so that the gate pulse width is made larger than usual to charge a pixel. The shortage has been improved. The details of the driving method are described in detail in Non-Patent Document 1.

  In Patent Document 1, the overlap scan driving method is applied to an amorphous silicon (hereinafter referred to as a-Si) gate driving circuit. In Patent Document 1, the shift register circuit of the a-Si gate driving circuit is The two clocks are operating at the same time and do not become H level at the same time. In Patent Document 1, since two clocks that do not simultaneously become H level are driven to overlap, it is necessary to make the interval time between the two clocks longer than the optimum time on the circuit. The operating margin can be secured without any problems. If the overlap scan driving is not performed as in Patent Document 1, the interval time between different clocks becomes longer as the number of clocks is increased, and the operation margin of the shift register circuit is lowered.

  On the other hand, in a liquid crystal display device, it is necessary to drive with an AC signal in order to prevent the liquid crystal from being polarized and degrading the display quality by continuing a constant voltage on the liquid crystal. In general, the signal is inverted in polarity at a constant period. The display quality and the power consumption of the source driver amplifier are in a trade-off relationship. In order to reduce the power consumption while maintaining the display quality, the inversion cycle of the source signal is generally 2-line inversion driving.

  In addition, in order to obtain a smooth moving image, the number of source lines is halved compared to the conventional display device in the case of increasing the frame frequency of the liquid crystal display device as in Patent Document 2 or in Non-Patent Document 2. When driving such that the number of gate lines is doubled, the pixel charging time is shorter than in conventional driving.

JP 2004-246358 A JP 2005-189820 A Jin Young Choi, 7 others, “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SID2006, P-218L Binn Kim, 10 others, “a-Si Gate Driver Integration with Time Shared Data Driving”, IDW05, AMDp-7

  Similarly to Patent Document 2 and Non-Patent Document 2, Non-Patent Document 1 also performs driving so that the number of source lines is one third and the number of gate lines is three times that of a conventional display device. The charging time is shorter than that of the conventional display device. For this reason, in a display device such as Non-Patent Document 1, it is easy for a pixel to be insufficiently charged depending on whether the polarity of the source signal of the previous line is the same polarity or reverse polarity, and display quality may be degraded.

  Patent Document 2 discloses that in a general liquid crystal display device driven by a gate IC or the like, the gate pulse width of each line is adjusted in order to prevent deterioration in display quality due to insufficient charging of pixels. ing. However, when the configuration of Patent Document 2 is adopted in a gate drive circuit composed of amorphous silicon TFTs, the drive signal supplied to the shift register circuit differs depending on each shift register circuit in order to adjust the gate pulse width. That is, the interval time between two clocks that are supplied to the respective shift register circuits and do not simultaneously become H level and the output period of the clock at H level are different, so that the operation margin of the circuit is lowered.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device and a driving method thereof that do not reduce the operation margin of a circuit while preventing insufficient pixel charging.

Engaging Ru resolving means to the present invention includes a plurality of pixels arranged in a matrix, a gate line and a source line connected to each pixel, a plurality of shift register circuit, the shift register circuit of each stage Driver circuit for sequentially supplying a gate signal to the gate line from the source, a source driver circuit for supplying a source signal corresponding to image data to the pixel via the source line, and a timing generation circuit for controlling the gate driver circuit and the source driver circuit A pixel of a predetermined color among the pixels of each row divided into two gate lines provided in each row, and two gates provided with pixels of other colors in each row Two pixels that are connected to only one of the lines and are located in the same row are connected to one source line.

Another solution according to the present invention includes a plurality of pixels arranged in a matrix, a gate line and a source line connected to each of the pixels, and a plurality of shift register circuits. Driver circuit for sequentially supplying a gate signal to the gate line from the source, a source driver circuit for supplying a source signal corresponding to image data to the pixel via the source line, and a timing generation circuit for controlling the gate driver circuit and the source driver circuit The pixel of a predetermined color among the pixels of each row is divided and connected to two gate lines provided in each row, and only one of the two gate lines provided with the other color pixels in each row is provided. and connect to connect to, and two pixels to the source line and the connection of one positioned in the same row, a driving method of an image display apparatus, the output period of the source signal , Together switched by a polarity change of the source signal, a gate signal sequentially supplied from the shift register circuits to the gate lines partially overlap, and adjust the output period of the gate signal to the switching timing of the source signal.

  In the image display device and the driving method thereof according to the present invention, the output period of the source signal is switched according to the polarity change of the source signal, and the output period of the gate signal is matched with the switching timing of the source signal. There is an effect that the operation margin of the circuit is not lowered while the shortage does not occur.

(Embodiment 1)
FIG. 2 is a block diagram of the image display apparatus according to this embodiment. The image display device shown in FIG. 2 is described as a liquid crystal display device in which pixels are driven by TFTs. However, the image display device according to the present invention is not limited to a liquid crystal display device, and an organic EL display device having a similar configuration. The present invention can also be applied.

  First, the pixel array 1 shown in FIG. 2 is provided with m columns × n rows of pixels 4, and each pixel is driven by a TFT. The first gate line (top row in the figure) of the pixel array 1 is G1, the last gate line (bottom row in the figure) is Gn, the leftmost source line is S1, and the rightmost source line is Sm. To do.

  The first gate driver circuit 2 shown in FIG. 2 uses the shift register circuits SRCO1 to SRCO1 that scan the odd-numbered gate lines in the direction from the start row to the end row, with the gate line G1 as the start row and the gate line Gn-1 as the end row. SRCON is provided. The first gate driver circuit 2 is composed of an amorphous silicon TFT.

  The first gate driver circuit 2 is connected so that the output SROUT1 of the shift register circuit SRCO1 is input to the shift register circuit SRCO3, and the output of the upper shift register circuit is input to the lower shift register circuit. Note that since the upper shift register circuit does not exist in the shift register circuit SRCO1, the start signal STVO is supplied from the outside. Further, clock signals CKVO and CKVBO are supplied to the shift register circuits SRCO1 to SRCON, respectively. Further, the output SROUT1 of the shift register circuit SRCO1 is supplied to the gate line G1, and the output SROUTn-1 of the shift register circuit SRCONn-1 is supplied to the gate line Gn-1, respectively, but the buffer unit for driving the gate line is omitted. Yes.

  The second gate driver circuit 3 shown in FIG. 2 includes shift register circuits SRCE2 to SRCEn + 1 that scan the even-numbered gate lines in the direction from the start row to the end row, with the gate line G2 as the start row and the gate line Gn as the end row. I have. The second gate driver circuit 3 is composed of an amorphous silicon TFT.

  In the second gate driver circuit 3, the output SROUT2 of the shift register circuit SRCE2 is connected to be input to the shift register circuit SRCE4, and the output of the upper shift register circuit is input to the lower shift register circuit. The shift register circuit SRCE2 is supplied with the start signal STVE from the outside because there is no upper shift register circuit. Further, clock signals CKVE and CKVBE are supplied to the shift register circuits SRCE2 to SRCEn + 1, respectively. Further, the output SROUT2 of the shift register circuit SRCE2 is supplied to the gate line G2, and the output SROUTn of the shift register circuit SRCEn is supplied to the gate line Gn, respectively, but the buffer unit that drives the gate line is omitted.

  The source driver circuit 5 shown in FIG. 2 switches the output polarity in synchronization with the source polarity control signal POL, and switches the source signal based on the image data DATA (including the control signal) in synchronization with the source switching control signal SSEL. . The source driver circuit 5 is connected to the source lines S1 to Sm, and a source signal is supplied to each of the source lines S1 to Sm.

  The timing generation circuit 6 shown in FIG. 2 includes gate driver control signal generation circuits 7 and 8 that generate a gate driver control signal based on a synchronization signal including a vertical synchronization signal, a horizontal synchronization signal, a dot clock signal, and a data enable signal. ing. Note that the gate driver control signals include start signals STVO and STVE and clock signals CKVO, CKVBO, CKVE, and CKVBE. The gate driver control signal generation circuit 7 is supplied with a delay amount setting signal, and the output timing is adjusted.

  Further, the timing generation circuit 6 includes a source polarity control signal generation circuit 9 that generates the source polarity control signal POL based on the synchronization signal, and a source switching control signal generation circuit 10 that generates the source switching control signal SSEL based on the synchronization signal. I have. The source switching control signal generation circuit 10 is supplied with a delay amount setting signal, and the output timing is adjusted. The timing generation circuit 6 includes an image signal processing circuit 11 that generates image data DATA based on the synchronization signal and the image data signal.

  The first gate driver circuit 2 and the second gate driver circuit 3 are configured by a shift register circuit having a plurality of stages that sequentially output outputs SROUT1 to n, which are gate signals, to each of a plurality of gate lines. Each shift register circuit of the plurality of stages activates the gate potential of a transistor (not shown) that drives the gate line in synchronization with the gate signal output from the shift register circuit of the previous stage, and synchronizes with the clock signal. As a result, a gate signal is output. Further, the transistor for driving the gate line is reset based on the gate signal output from the subsequent stage. In FIG. 2, the illustration of the supply of the gate signal output from the subsequent stage is omitted.

  2 employs a configuration in which the first and second gate driver circuits 2 and 3 are arranged on the left and right sides of the pixel array 1. However, the present invention is not limited to this, and the pixel array If the connection between the first and second gate driver circuits 2 and 3 is the same, the arrangement may be opposite to the left or right or may be arranged on either the left or right. In FIG. 2, the power supplies VDD and VSS supplied to the shift register circuit are not shown, but in the present invention, the presence or absence of the power supply VDD does not matter. Further, in the block diagram shown in FIG. 2, a power supply circuit that supplies a power supply voltage to each circuit and a level shift circuit that converts the voltage level to drive the gate driver circuit are omitted.

  Next, FIG. 3 shows the arrangement (pixel arrangement) of R (Red), G (Green), and B (Blue) of the pixel array 1 and the connection of the source lines S1 to Sm and the gate lines G1 to Gn. In FIG. 3, pixels are arranged in the order of RGB on each of the gate lines G1 to Gn, R pixel data via source lines S1 and 4, G pixel data via source lines S2 and 5, and source line S3. , 5 to supply B pixel data, respectively.

  Next, the operation of the image display apparatus according to this embodiment will be described. FIG. 1 is a timing chart of the image display apparatus according to the present embodiment. FIG. 1 illustrates a timing chart of an input image signal including a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, an image data signal, a source switching control signal, a source polarity control signal, and source signals of k and k + 1 frames. ing. Further, FIG. 1 shows gate driver control signals including start signals STVO and STVE and clock signals CKVO, CKVBO, CKVE and CKVBE, and timings of gate signals (outputs SROUT1 to 5) supplied to the gate lines G1 to G5, respectively. A chart is shown.

  The output polarity of the source signal output from the source driver circuit shown in FIG. 1 can be switched in synchronization with the source polarity control signal POL. Therefore, in the source signal supplied to the gate lines G1 and G2 in the k-th frame, as shown in the timing chart of FIG. 1, the negative polarity (NEG: negative) polarity is set in accordance with the source polarity control signal POL (thick line). It has become.

  Note that since the source polarity control signal POL is AC-driven to prevent the polarization of the liquid crystal, the polarity is inverted in units of frames in the timing chart shown in FIG. As a result, the polarity of the source signal is inverted between the kth frame and the (k + 1) th frame. Further, since the image display device according to the present embodiment has been described on the premise of dot inversion driving, the polarity is different for each source line although not shown in FIG. In the case of line inversion driving, the polarity of each source line is the same.

  Further, the output of the source signal output from the source driver circuit shown in FIG. 1 is switched in synchronization with the source switching control signal SSEL. Therefore, in the source signal supplied to the gate lines G1 and G2 of the k-th frame, as shown in the timing chart of FIG. 1, the H level period of the source switching control signal SSEL (G1: G2 = tsA: tsB) The output period is adjusted to correspond to.

  Since the image display apparatus according to the present embodiment employs overlap scan driving, the pixel connected to the nth line is once charged with the source signal of the (n−1) th line in the period before the first line. After that, the battery is charged with the source signal of the nth line. When the source signal of the (n−1) -th line and the source signal of the n-th line have opposite polarities, the pixel connected to the n-th line is charged from the state of being charged with the opposite polarity one line before to a predetermined potential. Since it will have to be, it will become insufficient charging.

  Therefore, in the image display device according to the present embodiment, as shown in FIG. 1, the charging time is lengthened when the previous line has a reverse polarity (for example, the line of the gate line G2 with respect to the line of the gate line G3). Since it is necessary, the source switching control signal generation circuit 10 lengthens the first period (tsA) of the source switching control signal SSEL based on the delay amount setting signal. Accordingly, since the charging time when the previous line has the same polarity is relatively short, the second period (tsB) of the source switching control signal SSEL is also shortened. Therefore, in the image display device according to the present embodiment, the source switching control signal SSEL is longer in the case of the reverse polarity than in the case where the source signal of the previous one line and the source signal of the current line have the same polarity. Will be output. In the timing chart shown in FIG. 1, for the sake of convenience, the first period (tsA) is set to the H level and the second period (tsB) is set to the L level. However, the present invention is not limited to this and has a reverse configuration. May be.

  In the timing chart shown in FIG. 1, data input as a pixel data signal is output as a source signal after two horizontal periods have elapsed. Specifically, in FIG. 1, after the elapse of two horizontal periods when a pixel data signal (denoted as G1 in FIG. 1) for the line of the gate line G1 is input, the source signal of the k-th frame and the (k + 1) -th frame is used as the source signal of the gate line G1. Pixel data for the line is output.

  Next, the operations of the first and second gate driver circuits 2 and 3 are basically the same overlap scan driving method as the method disclosed in Patent Document 1. Specifically, in the image display device shown in FIG. 2, the first gate driver circuit 2 provided on the left side drives the gate lines G1, G3, G5... The gate driver circuit 3 drives the gate lines G2, G4, G6.

  The gate driver control signal generated by the gate driver control signal generation circuit 7 is input to the shift register circuit of the first gate driver circuit 2. The first-stage shift register circuit SRCO1 receives the start signal STVO and outputs a gate signal, which is the output SROUT1, to the gate line G1 when the clock signal CKVO is at the H level. The shift register circuits SRCO3 to SRCONn after the second stage receive the output of the previous stage, and apply the gate signals as the outputs SROUT3 to SROUTn-1 to the respective gate lines G3 to Gn-1 at the timing of the clock signals CKVO and CKVBO. Output to.

  Similarly, the gate driver control signal generated by the gate driver control signal generation circuit 8 is input to the shift register circuit of the second gate driver circuit 3. The first-stage shift register circuit SRCE2 receives the start signal STVE and outputs a gate signal, which is the output SROUT2, to the gate line G2 when the clock signal CKVE is at the H level. The shift register circuits SRCO4 to SRCONn + 1 on and after the second stage receive the output of the previous stage and output the gate signals as the outputs SROUT4 to SROUTn to the respective gate lines G4 to Gn at the timing of the clock signals CKVE and CKVBE. Note that each of the outputs SROUT1 to SROUTn includes a buffer amplifier so that the respective capacities of the gate lines G1 to Gn can be charged within a required time (not shown in FIG. 2).

  Next, the gate driver control signals generated by the gate driver control signal generation circuits 7 and 8 are used to control the gate signals output from the gate driver circuits 2 and 3, respectively, and the clock signal clock width and the interval between the clock signals. The time is optimally adjusted. Specifically, as shown in FIG. 1, the clock width of the clock signals CKVO and CKVBO is twHO, the interval time between the clock signal CKVO and the clock signal CKVBO is tiO, the clock width of the clock signals CKVE and CKVBE is twHE, and the clock signal The interval time between CKVE and the clock signal CKVBE is tiE. The relationship is such that twHO = twHE and tiO = tiE.

  Further, the gate driver control signal generation circuit 7 adjusts the gate driver control signal based on the delay amount setting signal in response to adjusting the source signal writing period by the source switching control signal. Specifically, as shown in FIG. 1, the fall time of the clock signal CKVO is adjusted using the delay amount tdlyO in order to match the time tsA of the source switching control signal. Similarly, the fall time of the clock signal CKVE is adjusted using the delay amount tdlyE in order to match the time tsA of the source switching control signal. In an actual image display device, there is a certain amount of delay from the fall of the clock signals CKVO and CKVE to the fall of each gate signal and the turn-off of the TFT element of each pixel. The timing is such that the clock signals CKVO and CKVE fall before a certain time.

  The timing generation circuit 6 includes a circuit that holds image data for one horizontal period or more in the image processing signal circuit 11 in order to output a source signal for one horizontal period or more (not shown in FIG. 2). Further, the polarity of the source signal with respect to the gate lines G1, G2, G3, G4... Gn-1, Gn is NEG, NEG, POS, POS... POS, POS and POS, POS as shown in FIG. , NEG, NEG..., NEG, NEG has been described on the premise of switching every frame. However, the image display apparatus according to the present invention is not limited to the change in polarity of the source signal shown in FIG. 1, but NEG, POS, POS, NEG... POS, NEG and POS, NEG, NEG, POS. A configuration in which the POS is switched for each frame may be used. However, in the case of this configuration, pixels that do not become insufficiently charged pixels are switched, so the time tsA of the source switching control signal needs to be shorter than the time tsB and the delay amounts tdlyO and tdlyE need to be adjusted.

  As described above, in the image display device according to the present embodiment, when the polarities of the previous line and the current line are different, the source signal output period is adjusted by the source switching control signal SSEL and the source signal is increased. Since the gate signal for the overlap scan drive is adjusted in accordance with the change in the output period, there is an effect that the operation margin of the circuit is not lowered while preventing the pixel from being insufficiently charged.

  Next, for comparison with the timing chart of the image display device according to the present embodiment, a timing chart of a conventional image display device will be described. As shown in FIG. 9, the timing chart of the conventional image display apparatus is different from the timing chart shown in FIG. 1 in that it does not have a source switching control signal. Therefore, the output period of each line of the source signal is the same, and when the polarities are different between the previous line and the current line as shown in the timing chart of FIG. Occurs. In the timing charts shown in FIG. 1 and FIG. 1, the source signal portions having different polarities between the previous line and the current line are hatched. Corresponding to the timing chart shown in FIG. 1, the pixel shown in FIG. 3 is also hatched in the portion of the source signal whose polarity is different between the previous line and the current line.

  Further, in the present embodiment, for the sake of simplicity, the description has been given of the configuration in which the gate driver circuits 2 and 3 configured by the shift register circuit include two circuits that operate with a two-phase clock. Even if the configuration is changed to a configuration having four or eight circuits operating with a two-phase clock for the purpose of reducing power consumption, the same effect as described above can be obtained.

(Embodiment 2)
In the present embodiment, unlike the first embodiment, the image display device having the pixel arrangement shown in FIG. 5 is driven by the timing chart shown in FIG. In the image display device according to the present embodiment, as shown in FIG. 5, two gate lines are provided for pixels in the same row. Specifically, the RGB pixels in the first row in FIG. 5 include those connected to the gate line G1 (SP2, 4, 6) and those connected to the gate line G2 (SP1, 3, 5). is there. For this reason, the number of gate lines is twice that of the pixel arrangement shown in FIG. 3, but the number of source lines is halved.

  On the other hand, in the timing chart shown in FIG. 4, the number of source lines is halved, so that one horizontal period is about twice that of the timing chart shown in FIG. The source signal for the minute gate line (for example, G1, G2) is output. Further, in the timing chart shown in FIG. 4, similarly to the timing chart shown in FIG. 1, the source signal to be output is switched by the source switching control signal SSEL, and the respective output periods are adjusted. For example, in the source signal of the k-th frame shown in FIG. 4, the period for outputting to the gate line G1 is switched to tsA, and the period for outputting to the gate line G2 is switched to tsB. The period (tsA) for outputting to the line G1 is lengthened. The timing shown in FIG. 4 and the pixel shown in FIG. 5 are also hatched in the portion of the source signal whose polarity differs between the previous line and the current line.

  Other timings are the same as those in the timing chart shown in FIG. 1, and the configuration of the image display apparatus according to the present embodiment is also the same as that shown in FIG. The driving method according to the present embodiment is a driving method in which the driving method according to the first embodiment is applied to the driving method disclosed in Non-Patent Document 2. Therefore, detailed description of the same parts as those in Embodiment 1 and Non-Patent Document 2 is omitted.

  FIG. 6 shows a circuit diagram of the source driver circuit 5 according to the present embodiment. The source driver circuit 5 shown in FIG. 6 includes a Philip flop circuit 21 (FF (1) to (2j)) that operates based on image data DATA (including control signals) and a plurality of latch circuits 22 to 25 (LAT). ing. Further, in the source driver circuit 5 shown in FIG. 6, a switch 26 that operates based on the source switching control signal SSEL, a DA conversion circuit 27 (DAC) that performs DA conversion on the output of the switch 26, and DA An amplifier circuit 28 that amplifies the output of the conversion circuit 27 and a power supply circuit 29 that supplies power to the DA conversion circuit 27 and changes the polarity based on the source polarity control signal.

  The signals included in the image data DATA are supplied to the start signal XST and the clock signal XCLK supplied to each Philip flop circuit 21, the RGB data supplied to the latch circuits 22 to 24, and the latch circuit 25 at the final stage. 2nd LAT control signal.

  As described above, the image display apparatus according to the present embodiment extends the source signal output period by the source switching control signal SSEL when the polarities of the previous line and the current line are different, as in the first embodiment. And the gate signal for overlap scan driving is adjusted in accordance with the change in the output period of the source signal, so that there is an effect that the circuit operating margin is not lowered while preventing insufficient charging of the pixel. is doing.

(Embodiment 3)
The driving method disclosed in Non-Patent Document 2 is a driving method in which the source switching control signal SSEL does not exist as in the timing chart shown in FIG. 9 and the source signal always has the same output period. Therefore, when the n-1 line source signal and the n line source signal have opposite polarities, the pixel is insufficiently charged. Therefore, in the image display device according to the present embodiment, the n-1 line source signal and the n line source signal have opposite polarities, and the color of the pixel that causes insufficient charging is intentionally selected, whereby the insufficient charging is performed. This reduces display quality degradation.

  Specifically, FIG. 7 and FIG. 8 show a pixel arrangement of m columns × n rows and connection with source lines and gate lines of the image display device according to the present embodiment. In the pixel arrangement shown in FIG. 7, green pixels SP2, 5 connected to source lines S1, S3 and blue pixel SP3 connected to source line S2 are connected to odd gate lines such as gate lines G1, G3, G5. Has been. In the pixel array shown in FIG. 7, red pixels SP1, 4 connected to the source lines S1, S2 and blue pixels SP6 connected to the source line S3 are connected to the even gate lines such as the gate lines G2, G4, G6. Is connected.

  In the pixel array shown in FIG. 7, when driving according to the timing chart shown in FIG. 9, the pixels connected to the odd-numbered gate lines are insufficiently charged. For this reason, in the pixel array shown in FIG. 7, only the half of the green and blue pixels are undercharged, and the remaining half of the red and blue pixels are not charged.

  In general, insufficient charging of pixels is likely to be visually recognized as deterioration in display quality when shades of the same color occur, and even when insufficient charging occurs for all sub-pixels Although there is a change in chromaticity, it is difficult to visually recognize because unevenness of shading does not occur. In the pixel array shown in FIG. 5, unevenness due to shading occurs for all the colors of red, green, and blue, whereas the pixel array shown in FIG. By only causing unevenness due to shading, the deterioration of display quality due to insufficient charging of the pixels is most hardly recognized. Note that the change in chromaticity caused by the pixel arrangement shown in FIG. 7 can be improved by predicting in advance and adjusting the reference voltage of the source driver circuit 5, and better display performance can be obtained.

  In the present embodiment, the pixel array shown in FIG. 7 is shown as a method for improving display quality deterioration due to insufficient charging of the pixels. However, the present invention is not limited to this, and the pixel array shown in FIG. 8 may be used. In the pixel arrangement shown in FIG. 8, red pixels SP1, 4 connected to source lines S1, S2 and blue pixel SP6 connected to source line S3 are connected to odd gate lines such as gate lines G1, G3, G5. Has been. Further, in the pixel arrangement shown in FIG. 8, green pixels SP2, 5 connected to the source lines S1, S3 and blue pixels SP3 connected to the source line S2 are connected to even gate lines such as the gate lines G2, G4, G6. Is connected. In the pixel arrangement shown in FIG. 8, only the half of the red and blue pixels are undercharged, and the remaining half of the green and blue pixels are not charged. Therefore, the same effect as the pixel arrangement shown in FIG. 7 can be obtained.

  As described above, the image display device according to the present embodiment has an effect of improving the display quality deterioration (shading unevenness) due to insufficient charging of the pixels by employing the pixel arrangement shown in FIGS. is doing.

  Further, when the driving method described in the second embodiment is employed in the image display device according to the present embodiment, there is an effect that the operation margin of the circuit is not lowered while the insufficient charging of the pixels is prevented. it can. Specifically, it can be realized by driving an image display device adopting the pixel arrangement shown in FIGS. 7 and 8 according to the timing chart shown in FIG.

(Embodiment 4)
In the above-described embodiment, a configuration in which the writing time is adjusted for a pixel in which insufficient charging occurs due to a change in the polarity of the source signal while maintaining the optimal driving timing of the first and second gate driver circuits 2 and 3. explained.

  On the other hand, in the present embodiment, a pixel that is insufficiently charged due to a change in the polarity of the source signal and a pixel that is not insufficiently charged are switched in synchronization with the frame signal, thereby averaging the entire display of the image display device over time. To improve display performance.

  Specifically, the configuration of the image display apparatus according to the present embodiment will be described. First, FIGS. 10A and 10B are schematic views of an image display apparatus according to the present embodiment. 10 (a) and 10 (b), in order to simplify the description, the configuration in which the pixels 4 of RED (R: red), GREEN (G: green), and BLUE (B: blue) are made into one set has two rows × This is a three-line image display device. In the pixel array 1 shown in FIGS. 10A and 10B, each pixel is driven by a TFT. The pixel array 1 has the same configuration as that of the above-described embodiment, and two gate lines are wired for one row. The first row is a gate line G1, G2 and the second row is a gate. Lines G3 and G4 are gate lines G5 and G6 in the third row. On the other hand, the R and G pixels 4 in the first column are included in the source line S1, the B pixels 4 and the R pixels 4 in the second column are included in the source line S2, and the G pixels in the second column are included in the source line S3. And B pixel 4 are connected to each other. With the configuration shown in FIGS. 10A and 10B, the image display device according to the present embodiment has twice the number of gate lines and 1/2 the number of source lines as compared to a general image display device.

  Further, the image display device shown in FIGS. 10A and 10B has a configuration in which the gate driver control signal supplied to the first gate driver circuit 2 and the second gate driver circuit 3 is switched by the frame signal. Therefore, in the image display device according to the present embodiment, the display in FIG. 10A and the display in FIG. 10B are reversed for each frame. That is, in FIG. 10A, the red pixel SP1 and the blue pixel SP3 in the first column and the green pixel SP5 in the second column are not insufficiently written (insufficient charging), but the green pixel SP3 in the first column and the second column The red pixel SP4 and the blue pixel SP6 are displayed with insufficient writing. On the other hand, in FIG. 10B, the red pixel SP1 and blue pixel SP3 in the first column and the green pixel SP5 in the second column are insufficiently written, and the green pixel SP3 in the first column, the red pixel SP4 in the second column, and blue. The pixel SP6 is displayed with no insufficient writing. By repeating the display of FIG. 10 (a) and FIG. 10 (b) for each frame, the writing deficient period and the non-writing deficient period are switched for each frame, so that the entire display of the image display device is temporally changed. Averaging can improve display performance.

  Further, FIG. 11 shows a block diagram illustrating a detailed configuration of the image display apparatus according to the present embodiment. The first gate driver circuit 2 of the image display device shown in FIG. 11 is composed of amorphous silicon (a-Si) TFTs, and includes a start signal STVO, clock signals CKVO, CKVBO, and the like of the shift register circuit (SR-ODD-1). Are controlled by a gate driver control signal (ODD). The first gate driver circuit 2 has driver outputs connected to the gate lines G1, G3, G5, and G7, and drives the first row of green pixels SP2 and the second row of red pixels SP4 and blue pixels SP6.

  Similarly, the second gate driver circuit 3 is also composed of an amorphous silicon (a-Si) TFT, and gate driver control signals (such as a start signal STVE and clock signals CKVE and CKVBE of the shift register circuit (SR-EVEN-1)). EVEN). The second gate driver circuit 3 has driver outputs connected to the gate lines G2, G4, G6, and G8, and drives the red pixel SP1, the blue pixel SP3 in the first column, and the green pixel SP5 in the second column.

  The source driver circuit 5 switches the output polarity of the source signal in synchronization with the source output polarity control signal POL, and switches the source output in synchronization with the source switching control signal SSEL. The source driver circuit 5 is connected to the source lines S1, S2, S3.

  The timing generation circuit 6 generates a source output polarity control signal (POL) to the source driver circuit 5 and a source switching control from a double direct synchronization signal, a horizontal synchronization signal, a plurality of image data signals, a data enable signal, a dot clock signal and the like. Signals (SSEL) and timings (STVO, CKVO, CKVBO, STVE, CKVE, CKVBE) necessary for the first and second gate driver circuits 2 and 3 are generated. In particular, the gate driver control signal generation circuit (ODD side) 7 and the gate driver control signal generation circuit (EVEN side) 8 included in the timing generation circuit 6 output timings (STVO, CKVO, CKVBO, STVE, CKVE, CKVBE) as source outputs. The polarity control signal generation circuit 9 generates a source output polarity control signal (POL), and the source output switching control signal generation circuit 10 generates a source switching control signal (SSEL).

  Furthermore, in the image display device according to the present embodiment, the timing signal generation circuit 6 includes a frame signal generation circuit 12. The frame signal generation circuit 12 generates a signal for discriminating a frame from an input synchronization signal, and a gate driver control signal generation circuit (ODD side) 7, a gate driver control signal generation circuit (EVEN side) 8, and a source output polarity The control signal generation circuit 9 and the source output switching control signal generation circuit 10 are controlled to be switched for each frame.

  The configurations and operations of the first and second gate driver circuits 2 and 3 are the same as those in the above-described embodiment. The source driver circuit 5 that outputs the signals S1 to S3 has the same circuit configuration as that shown in FIG. The source driver circuit 5 shown in FIG. 6 has a latch for one row of image data, and includes a DA converter and a buffer amplifier that output an image signal in time division in synchronization with the source switching control signal SSEL.

  12, 13, 14, and 15 are timing charts of the image display device according to the present embodiment. In the timing charts shown in FIGS. 12, 13, 14, and 15, since the potential of the pixel is inverted for each frame by the AC driving of the liquid crystal, the time of k frames (FIGS. 12 and 13) and the time of k + 1 frames (FIG. 14 and FIG. 15). A frame signal generation circuit 12 generates a frame signal 16 from the input synchronization signal. The frame signal 16 may be a signal that toggles between the H level voltage and the L level voltage for each frame (not shown in FIGS. 12, 13, 14, and 15). The source signal polarity control signal POL is generated by the source output polarity control signal generation circuit 9 using the frame signal 16 and other synchronization signals. This signal determines the polarity of the source signal for the common electrode (not shown) of the liquid crystal display device.

  The source switching control signal SSEL is generated by the source output switching control signal generation circuit 10 using the frame signal 16 and other synchronization signals. With this signal, output timing of an image signal output in a time division manner in one horizontal period is controlled. In the timing charts shown in FIGS. 12, 13, 14, and 15, image data signals of the pixels 4 connected to the gate lines G1, G3, G5, and G7 are output at the H level, and G2, G4, and G6 are output at the L level. , G8 output image data signals of the pixels 4 connected to G8.

  Gate driver control signals (ODD) such as a start signal STVO and clock signals CKVO and CKVBO are generated by the gate driver control signal generation circuit (ODD side) 7 using the frame signal 16 and other synchronization signals. The start signal STVO and the clock signals CKVO and CKVBO are set with an optimum clock width and an interval time between the clock and the inverted clock for driving the first gate driver circuit 2, and are shifted in synchronization with the frame signal 16. The position of the first stage (SR-ODD-1) is controlled.

  Similarly, the gate driver control signal (EVEN) is generated by the gate driver control signal generation circuit (EVEN side) 8, and the position of the first stage (SR-EVEN-1) of the shift register is controlled in synchronization with the frame signal 16. Is done.

  12, 13, 14, and 15 are timing charts in which the start signals STVO and STVE, the clock signals CKVO and CKVE, and the clock signals CKVBO and CKVBE are switched for each frame.

  The source driver circuit 5 latches the image data signal for one row, and for two pixels connected to the same row, in synchronization with the outputs of the first gate driver circuit 2 and the second gate driver circuit 3, An analog signal corresponding to the image data signal is output in the division. Here, the timing at which insufficient charging occurs due to the source signal polarity is indicated by hatching (in FIG. 12, FIG. 13, FIG. 14, and FIG. 15, the timing of driving earlier in time division driving is the timing of insufficient charging).

  When the timing for toggling the source signal polarity control signal POL is fixed, this timing is always constant. Therefore, in the conventional configuration, the pixels driven at the hatched timing are always fixed. Therefore, if the pixel potential is different from the other pixels due to insufficient charging, the luminance differs accordingly and display unevenness occurs. There was a possibility of being visually recognized. Therefore, in the present embodiment, the driving timing of the first gate driver circuit 2 and the second gate driver circuit 3 is controlled for each frame, and the gate lines driven at the hatched timing are switched, so that the driving is performed accordingly. The pixels to be replaced are also changed every frame.

  12, 13, 14, and 15, the pixel that is insufficiently charged in the k frame is the hatched pixel in FIG. 10A, and the pixel that is insufficiently charged in the k + 1 frame is that in FIG. ) Hatched pixels. Note that the polarity (+ or−) described in parentheses in the pixels of FIGS. 10A and 10B indicates the polarity of the voltage applied to the liquid crystal.

  Therefore, the pixels that are insufficiently charged are not temporally dispersed but are temporally dispersed, so that the luminance of each pixel is averaged and is not visually recognized as display unevenness. 12, 13, 14, and 15, even when the position where the source signal polarity control signal POL is toggled is shifted by ½ horizontal period, the timing at which insufficient charging occurs is shifted by ½ horizontal period. Therefore, the same effect can be obtained. As a case where the ½ horizontal period is shifted, for example, the timing at which “−− ++ −− ++” and “++ −− ++ −−” are switched for each frame with the ½ horizontal period as one unit is “− ++-++-"and" +-++-+ ". However, in the case of the configuration of FIGS. 10A and 10B, the polarity of the voltage applied to the liquid crystal is the same in the column direction, so the timings of FIGS. 12, 13, 14 and 15 are optimal and optimal timing. It becomes.

  In order to simplify the description, it is assumed that the first and second gate driver circuits 2 and 3 are shifted in one direction, but a gate driver circuit that performs a shift operation in both directions may be used. The effect is obtained. Similarly, the first and second gate driver circuits 2 and 3 constituted by shift registers have been described as having two circuits operating with a two-phase clock. However, for the purpose of speeding up and reducing power consumption. Four circuits that operate with a two-phase clock may be used, and similar effects can be obtained. Furthermore, the same effect can be obtained even when eight circuits operating with a two-phase clock are used.

  As described above, in the image display device according to the present embodiment, the pixel that is insufficiently charged due to the change in the polarity of the source signal and the pixel that is not insufficiently charged are switched in synchronization with the frame signal. Prevents deterioration of display quality due to insufficient charge during high-speed driving caused by polarity inversion of source signal while supplying optimal timing for gate overlap scan driving that does not reduce the operating margin of the gate driving circuit composed of silicon TFT it can. In the image display device according to the present embodiment, the gate driver control signal generation circuit changes the selection order of the gate lines for each frame based on the frame signal output from the frame signal generation circuit. Further, as shown in FIG. 11, the image display device according to the present embodiment connects the pixels in each row so as to be connected to one of two gate lines provided in each row, and the same row. The two pixels located at are connected to one source line, and the two gate lines provided in each row are connected to different shift register circuits.

(Embodiment 5)
FIGS. 16A and 16B are schematic views of the image display apparatus according to the present embodiment. FIGS. 16A and 16B are substantially the same as the configurations of FIGS. 10A and 10B described in the fourth embodiment, but the output stages of the first and second gate driver circuits 2 and 3 and the pixels Only the connection method of the gate lines G1 to G8 of the array 1 is different.

  Specifically, in the first gate driver circuit 2 shown in FIG. 16A, the output of the shift register circuit SR-ODD-1 and the gate line G1, and the output of the shift register circuit SR-ODD-2 and the gate line G4. The output of the shift register circuit SR-ODD-3 is connected to the gate line G5. In the second gate driver circuit 3 shown in FIG. 16A, the output of the shift register circuit SR-EVEN-1 and the gate line G2, the output of the shift register circuit SR-EVEN-2, the gate line G3, and the shift register circuit SR- The output of EVEN-3 is connected to the gate line G6. Therefore, in the image display device according to the present embodiment, the combination of connections between the two gate lines in one row and the output stages of the first and second gate driver circuits 2 and 3 is exchanged for each row.

  17, 18, 19, and 20 are timing charts of the image display device according to the present embodiment. The timing charts shown in FIGS. 17, 18, 19, and 20 are basically the same as the timing charts shown in FIGS. 12, 13, 14, and 15, but the timing of the source switching control signal SSEL is changed. It has changed. Specifically, in the timing chart at the k-th frame shown in FIGS. 17 and 18, the source signals are the pixels of the gate line G1, the pixels of the gate line G2, and the gate lines G4, G3, G5, G6, G8, and G7. The order of writing is different from the order of G1, G2, G3, G4, G5, G6, G7, and G8 in the timing charts shown in FIGS. In the timing chart in the (k + 1) th frame shown in FIGS. 19 and 20, the source signal is written in the order of the pixel of the gate line G2, the pixel of the gate line G1, and the gate lines G3, G4, G6, G5, G7, and G8. This order is different from G2, G1, G4, G3, G6, G5, G8, and G7 in the timing charts shown in FIGS. The hatched portions in FIGS. 12, 13 and 14, 15, 15, 17, 18, 19 and 20 are timings at which insufficient charging occurs.

  Pixels that are insufficiently charged in the timing chart of the kth frame shown in FIGS. 17 and 18 are hatched pixels in FIG. 16A, and are insufficiently charged in the timing charts of the (k + 1) th frame shown in FIGS. The generated pixels are hatched pixels in FIG. In other words, in the fourth embodiment, pixels in which insufficient charging occurs are concentrated in the same column, but in this embodiment, pixels in which insufficient charging occurs are checkered and distributed. Therefore, in the image display device according to the present embodiment, in addition to the effects of the fourth embodiment, the pixels that are insufficiently charged are not concentrated in the same column but are more dispersed, so that the display performance is further improved.

3 is a timing chart of the image display device according to the first embodiment of the present invention. 1 is a block diagram of an image display device according to Embodiment 1 of the present invention. It is a figure for demonstrating the pixel arrangement | sequence and connection of the image display apparatus which concern on Embodiment 1 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the pixel arrangement | sequence and connection of an image display apparatus which concern on Embodiment 2 of this invention. It is a circuit diagram of the source driver circuit of the image display apparatus which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the pixel arrangement | sequence and connection of an image display apparatus which concern on Embodiment 3 of this invention. It is a figure for demonstrating another pixel arrangement | sequence and connection of the image display apparatus which concerns on Embodiment 3 of this invention. 3 is a timing chart of the image display apparatus as a premise of the present invention. It is the schematic of the image display apparatus which concerns on Embodiment 4 of this invention. It is a block diagram of the image display apparatus which concerns on Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 4 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 4 of this invention. It is the schematic of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention. It is a timing chart of the image display apparatus which concerns on Embodiment 5 of this invention.

Explanation of symbols

  1 pixel array, 2 first gate driver circuit, 3 second gate driver circuit, 4 pixels, 5 source driver circuit, 6 timing generation circuit, 7, 8 gate driver control signal generation circuit, 9 source polarity control signal generation circuit, 10 Source switching control signal generation circuit, 11 image signal processing circuit, 12 frame signal generation circuit, 21 Philip flop circuit, 22 to 25 latch circuit, 26 switch, 27 DA converter circuit, 28 amplifier circuit, 29 power supply circuit.

Claims (5)

A plurality of pixels arranged in a matrix;
A gate line and a source line connected to each of the pixels;
A gate driver circuit having a plurality of shift register circuits and sequentially supplying gate signals to the gate lines from the shift register circuits at each stage;
A source driver circuit for supplying a source signal corresponding to image data to the pixel via the source line;
An image display device comprising a timing generation circuit for controlling the gate driver circuit and the source driver circuit,
Of the pixels in each row, the pixel of a predetermined color is divided and connected to the two gate lines provided in each row, and one of the two gate lines provided in each row with the pixels of other colors An image display device characterized in that the two pixels connected in the same row are connected to only one source line . The image display device according to claim 1,
The timing generation circuit includes:
A gate driver control signal generating circuit for generating a gate driver control signal for controlling the gate signals supplied from the shift register circuit to the gate lines sequentially to partially overlap;
A source polarity control signal generating circuit for generating a source polarity control signal for controlling to switch the polarity of the source signal;
A source switching control signal generation circuit that generates a source switching control signal that controls to switch an output period of the source signal according to a polarity change of the source signal;
The image display device, wherein the gate driver control signal generation circuit generates the gate driver control signal so as to adjust an output period of the gate signal in accordance with a timing of the source switching control signal . The image display device according to claim 1 or 2,
The predetermined color to an image display, human visual sensitivity is characterized by a low color der Rukoto. An image display device according to any one of claims 1 to 3,
The gate driver circuit is formed on the same substrate as the pixels, an image display device comprising that you have been composed of amorphous silicon TFT. A plurality of pixels arranged in a matrix;
A gate line and a source line connected to each of the pixels;
A gate driver circuit having a plurality of shift register circuits and sequentially supplying gate signals to the gate lines from the shift register circuits at each stage;
A source driver circuit for supplying a source signal corresponding to image data to the pixel via the source line;
A timing generation circuit for controlling the gate driver circuit and the source driver circuit,
Of the pixels in each row, the pixel of a predetermined color is divided and connected to the two gate lines provided in each row, and one of the two gate lines provided in each row with the pixels of other colors A method of driving an image display device, wherein the two pixels connected in the same row are connected to one source line.
The output period of the source signal is switched according to a change in polarity of the source signal, the gate signals sequentially supplied from the shift register circuit to the gate lines partially overlap, and the output period of the gate signal is the driving method of an image display device according to claim Rukoto fit switching timing of the source signal.

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