JP4363881B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal display device that performs H / V inversion driving.
[0002]
[Prior art]
In recent years, the share of liquid crystal display devices has expanded as displays for personal computers, home televisions, and the like, and high resolution and large screen size liquid crystal display devices have become available at a relatively low price. Among them, an active matrix type liquid crystal display device (hereinafter referred to as a liquid crystal display device) in which pixel transistors are arranged in the vicinity of intersections of signal lines and scanning lines arranged in a matrix form has excellent color development and little afterimage. It is considered to become the mainstream in the future.
[0003]
Among these, liquid crystal display devices using amorphous silicon TFTs require connection wiring for inputting video signals from the TCP (Tape Carrier Package) to the signal lines on the array substrate. As a result, the number of connection wires has increased, and it has been difficult to ensure a sufficient pitch between these connection wires. On the other hand, in a liquid crystal display device using a pixel transistor made of polycrystalline silicon, the signal line driving circuit is integrally formed on the array substrate in addition to the scanning line driving circuit, thereby reducing the number of external connection parts and reducing the cost. This has the advantage that connection wiring can be reduced.
[0004]
Further, as a driving method of each signal line, that is, a video signal writing method from each signal line to each pixel, a video signal whose polarity (polarity) is reversed is written to adjacent signal lines, and one vertical scanning period. V-line inversion driving for switching between positive and negative of the video signal written to the signal line every time, and video signals whose polarity is inverted are written to adjacent signal lines within one horizontal scanning period, and the same every horizontal scanning period In general, H / V inversion driving is performed to switch between positive and negative of a video signal written to the signal line.
[0005]
In order to further reduce the cost of driving ICs that are externally connected parts, the output voltage from the driving ICs is connected to three analog switches in the signal line driving circuit formed on the array substrate. There is a display device in which three writing times are provided in one horizontal scanning period.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-109435
[Problems to be solved by the invention]
When H / V inversion driving is performed in a circuit configuration with a reduced number of driving ICs as described above, the pixel potential is affected by the coupling between the own pixel-own signal line, the own pixel-adjacent signal line, and the own signal line-adjacent signal line. Since the pixel potential varies and the pixel potential amount varies depending on the pixel, display unevenness may occur.
[0008]
Conventionally, when three writing times are provided in one horizontal scanning period, the order of writing video signals to the pixels is the order of R (red) pixels, G (green) pixels, and B (blue) pixels in the horizontal direction. It has become. On the other hand, the amount of fluctuation in the pixel potential due to the coupling is the smallest in the third written pixel, so the amount of fluctuation in the pixel potential of the B pixel is the smallest, and conversely, display unevenness is easily visible. Since the pixel potential fluctuation amount of the pixel becomes large, the display unevenness is more easily recognized.
[0009]
An object of the present invention is to provide a configuration in which one output of a driving IC is connected to three analog switches in a signal line driving circuit built in an array substrate and three writing times are provided in one horizontal scanning period. In view of the above, it is an object of the present invention to provide a liquid crystal display device capable of reducing display unevenness when performing H / V inversion driving and obtaining good display quality.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 includes a plurality of signal lines and a plurality of scanning lines that cross each other, a plurality of pixel transistors disposed at each intersection of the two lines, A liquid crystal panel having a plurality of pixel electrodes connected to each pixel transistor, red, green, and blue color filters arranged for each pixel electrode, and a scanning line driving circuit for supplying a scanning signal to each scanning line N signal line driving ICs that serially output a video signal for each signal line group when the plurality of signal lines are divided into N (N: an integer of 3 or more) signal line groups, N signal line selection circuits that output the video signal output from the signal line driving IC by switching to the corresponding signal line of each signal line group in three times within one horizontal scanning period, and the signal line The video signal is sent to a predetermined signal line by a selection circuit. A liquid crystal display device including a control signal generation circuit that generates a control signal that determines an output order when the output is switched, wherein the pixel electrode constitutes a small pixel, Large pixels of the same color arrangement composed of three small pixels colored with red, green, and blue color filters are arranged in a matrix, and the signal line driving ICs are adjacent to each other within one horizontal scanning period. A video signal whose polarity is inverted to each other is output to the signal line, and the positive / negative of the video signal output to the same signal line is switched every horizontal scanning period, and the control signal generation circuit is provided within one horizontal scanning period. Of the three writing periods, the output order of the video signals is set so that the video signal output in the third writing period is output to the signal line connected to the small pixel colored with the green color filter. Defined control signal It is characterized in that to produce a.
[0011]
According to a second aspect of the present invention, in the first aspect, the signal line selection circuit includes three analog switches for one output from the signal line driving circuit IC, and the source electrode of each analog switch is the signal line. Commonly connected to one output line from the drive circuit IC, the gate electrode of each analog switch is connected to each supply line of the control signal, and the drain electrode of each analog switch is connected to the corresponding signal line. In response to the control signal output from the control signal generation circuit, the source electrode and the drain electrode of each analog switch are electrically connected to correspond to the video signal output to one output line of the signal line driver circuit IC. It is characterized by writing to the signal line.
[0012]
According to the above configuration, since the order of writing video signals to each pixel is the order of R pixel, B pixel, and G pixel, the third is the smallest variation in pixel potential due to coupling. G pixels that are easily visible are written. As described above, since the pixel potential fluctuation amount of the G pixel in which the display unevenness is easily visible is the smallest, the display unevenness becomes difficult to be visually recognized, and a good display quality can be obtained as the entire screen.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a liquid crystal display device according to the present invention will be described below with reference to the drawings.
[0014]
In the present embodiment, an XGA (1024 × RGB × 768) standard liquid crystal panel is assumed. Here, a description will be given of a configuration in which each one output line taken out from the signal line driving IC is branched by three analog switches and connected to three signal lines.
[0015]
FIG. 2 is a circuit configuration diagram schematically showing the configuration of the liquid crystal display device according to the present embodiment.
[0016]
The pixel array unit 100 of the liquid crystal display device 1 includes an array substrate 200, a counter substrate (not shown) arranged at a predetermined interval from the array substrate 200, and a liquid crystal layer 300 held between the substrates. Further, the array substrate 200 and a counter substrate (not shown) are bonded together by a seal material (not shown) disposed around the array substrate 200.
[0017]
The array substrate 200 is wired such that a plurality of scanning lines G1 to G768 (hereinafter referred to as generic name G) and a plurality of signal lines S1 to S3072 (hereinafter referred to as generic name S) are orthogonal to each other. A pixel TFT 110 serving as a pixel transistor and a pixel electrode 120 serving as a pixel (here, RGB sub-pixels) are provided at each intersection of both lines. A plurality of pixel electrodes 120 arranged in a matrix on the array substrate 200 constitute a pixel portion 210.
[0018]
Each pixel is provided with an RGB color filter (not shown). In the following description, R pixel is a pixel colored with an R (red) color filter, G pixel is a pixel colored with a G (green) color filter, and B pixel is a B (blue) color filter. Means a pixel colored with. Each color array is repeatedly arranged in the order of RGB in each row, and pixels of the same color are arranged in each column. In this manner, in the pixel unit 210, each pixel electrode 120 constitutes a small pixel (sub pixel) serving as a drive unit, and the R pixel, G pixel, and B pixel colored with the RGB color filter serve as a display unit. A large pixel (pixel) having the same color arrangement is formed.
[0019]
The common electrode 130 disposed opposite to the pixel electrode 120 is formed on a counter substrate (not shown), and the liquid crystal layer 300 is interposed between the pixel electrode 120 and the common electrode 130 via an alignment film (not shown). Is retained.
[0020]
The pixel TFT 110 is configured by, for example, a polycrystalline silicon TFT having a polycrystalline silicon film as a semiconductor layer. The gate electrode of the pixel TFT 110 is connected to the scanning line G, and the source electrode is connected to the signal line S. The drain electrode is connected to the pixel electrode 120 and the auxiliary capacitance element 140, respectively. The pixel TFT 110 is turned on by the scanning signal supplied to the scanning line G, and the source / drain electrodes are electrically connected, whereby the video signal written to the signal line S is applied from the source electrode to the pixel electrode 120 through the drain electrode. The
[0021]
The scanning line driving circuit 150 is a circuit that supplies scanning signals to the scanning lines G1 to G768, and is integrally formed on the array substrate 200 by the same manufacturing process as that of the pixel TFT 110. The scanning line driving circuit 150 is disposed on the left side and the right side of the pixel unit 210.
[0022]
The signal line drive circuit unit 160 is a circuit that supplies a video signal with positive and negative polarities to the signal lines S1 to S3072, and the video signal corresponding to each signal line is supplied to the signal lines S1 to S3072 as three signal lines. Signal line driving ICs (TAB-ICs) 410-1, 410-2, 410-3 (hereinafter generically referred to as 410-N) that output serially by dividing each signal line group when divided into groups, and signals The video signal output from the line driving IC 410 is divided into three times within one horizontal scanning period, and the signal line selection circuit 170 is configured to switch to a predetermined signal line of each signal line group for output.
[0023]
TCPs 400-1 to 3 (hereinafter generically referred to as 400 -N) of the signal line driver circuit unit 160 have one side in the longitudinal direction connected to the array substrate 200 side and the other side connected to the external driver circuit 500 side. The signal line driving IC 410-N mounted on the TCP 400-N includes a D / A converter (not shown). The signal line driving IC 410-N converts a digital video signal input from a control IC 600, which will be described later, into an analog video signal and outputs a signal line. The data is output to the selection circuit 170.
[0024]
The signal line driving IC 410-N includes 342 output terminals (OUT). That is, in the signal line driving IC 410-1, 342 output terminals are respectively connected to three signal lines via an analog switch described later, and supply video signals R1 to B342 to the signal lines S1 to S1026. ing. Similarly, the signal line driving IC 410-2 supplies video signals R343 to B684 to the signal lines S1027 to S2052, and the signal line driving IC 410-3 supplies video signals R685 to B1024 to the signal lines S2053 to S3072, respectively. However, in the signal line driving IC 410-3, 340 output terminals are used, and the remaining two are used as remaining terminals.
[0025]
In this embodiment, the signal lines S1 to S3072 are divided into three signal line groups in the order of selection, and the signal lines S1, S4, S7,... S3070, the signal lines S2, S5, S8,. , S6, S9,... S3072.
[0026]
The above-mentioned division is a division of signal lines that are simultaneously selected within one horizontal scanning period. In FIG. 2, the signal lines S1 to S3072 divided into three signal line groups are connected to respective signal line driving ICs. It shows how it is. During driving, for example, signal lines S1, S4, S7,..., Signal lines S2, S5, S8,..., Signal lines S3, S6, S9,. A video signal is written for each signal line in order. At this time, the signal line driving IC 410-N determines the polarity of the video signal so that the video signals whose polarity is inverted are written to the adjacent signal lines within one horizontal scanning period for H / V inversion driving, and The sign of the video signal written to the same signal line is switched every horizontal scanning period.
[0027]
The signal line driving IC 410 is mounted on a flexible wiring board, and is electrically connected to the external driving circuit 500 and the array substrate 200, respectively. Further, the signal line selection circuit 170 is disposed on the array substrate 200.
[0028]
The external drive circuit 500 includes a control IC 600 serving as a control circuit that generates an analog switch control signal and the like for controlling the order when the signal line selection circuit 170 switches and outputs the video signal to the corresponding signal line, and not shown. A power circuit is mounted.
[0029]
The control IC 600 rearranges and outputs externally input digital video signals in the order of output to each signal line, and generates various control signals based on a reference clock signal input in synchronization therewith. That is, the control IC 600 supplies a start pulse and a clock signal to the scanning line driving circuit 150, and rearranged digital video signals, register control signals, clock signals, load signals, etc. to the signal line driving ICs 410-1 to 410-3. Supply. The signal line selection circuit 170 is supplied with analog switch control signals ASW1U, ASW2U, and ASW3U. In addition, the control IC 600 performs analog processing so that the video signal output in the third writing period among the three writing periods provided in one horizontal scanning period is output to the signal line S connected to the G pixel. The output order of the switch control signals ASW1U, ASW2U, and ASW3U is controlled.
[0030]
FIG. 1 is a circuit configuration diagram showing a schematic configuration of the signal line driving circuit unit 160. Among these, FIG. 1A is a circuit configuration diagram of a basic block included in the signal line selection circuit 170. Here, the basic block arranged at the left end of (B) is shown as a representative. FIG. 1B is a circuit configuration diagram showing the configuration of the signal line driving IC 410 -N and the signal line selection circuit 170.
[0031]
As shown in FIG. 1B, the signal line selection circuit 170 includes a plurality of basic blocks 180, and 171 basic blocks 180 are connected to each of the signal line driving ICs 410-N. 170 in the signal line driving IC 410-3). Further, two output terminals OUT are connected to one basic block 180 from each signal line driving IC 410 -N.
[0032]
As shown in FIG. 1A, one basic block 180 includes analog switches SW1, SW2,... SW6 (hereinafter, generic SW) composed of Pch TFTs. Among these, the source electrodes of the analog switches SW1, SW2, and SW3 are commonly connected to the output terminal (output line) OUT1 of the signal line driving IC 410-1, and the source electrodes of the analog switches SW4, SW5, and SW6 are for driving the signal line. It is commonly connected to the output terminal OUT2 of the IC 410-1. The drain electrodes of the analog switches SW1, SW2, and SW3 are connected to the signal lines S1, S2, and S3, and the drain electrodes of the analog switches SW4, SW5, and SW6 are connected to the signal lines S4, S5, and S6. Accordingly, six signal lines are driven in a time division manner in one basic block 180. On the other hand, the gate electrodes of the analog switches SW1 and SW4 are connected in common to the analog switch control signal line (supply line) ASW1, and the gate electrodes of the analog switches SW2 and SW5 are connected in common to the analog switch control signal line ASW2. The gate electrodes of the analog switches SW3 and SW6 are commonly connected to the analog switch control signal line ASW3.
[0033]
Since the analog switch SW is composed of a Pch TFT, when the analog switch control signal ASW1U becomes a low potential, the analog switches SW1, SW4, SW7,. ... when a video signal is written in S3070 and the analog switch control signal ASW2U becomes a low potential, the analog switches SW2, SW5, SW8, ... SW3071 are turned on, and the signal lines S2, S5, S8, ... When the video signal is written and the analog switch control signal ASW3U becomes a low potential, the analog switches SW3, SW6, SW9,... A signal is written.
[0034]
In addition, signal lines S1, S4, S7,... S3070 are connected to columns R1, R2,... In which R (red) video signals are written, and signal lines S2, S5, S8,. The signal lines S3, S6, S9,... S3072 are respectively connected to the columns B1, B2,... Where B (blue) video signals are written. . Therefore, video signals corresponding to R pixels in each row are written from the signal lines S1, S4, S7,... S3070, and video signals corresponding to G pixels in each row are written from the signal lines S2, S5, S8,. , And video signals corresponding to B pixels in each row are respectively written from the signal lines S3, S6, S9,.
[0035]
Next, an operation when writing a video signal to each signal line S in the liquid crystal display device 1 configured as described above will be described.
[0036]
FIG. 3 is a timing chart of analog switch control signals ASW1U, ASW2U, and ASW3U output from the control IC 600.
[0037]
As shown in the figure, three writing periods are provided within one horizontal scanning period (1H), and video signals corresponding to R, G, and B are sequentially written for each row. In FIG. 1, the 3n-2 line, the 3n-1 line, and the 3n line indicate three consecutive lines. In the present embodiment, the analog switch control signal given to each row is controlled so as to have a low potential in the order of ASW3U, ASW1U, and ASW2U. Therefore, the video signal is written to the B pixel in the first writing within one horizontal scanning period, the R pixel in the second writing, and the G pixel in the third writing. Similarly, the video signals are written in the order of analog switch control signals ASW3U → ASW1U → ASW2U in the other basic blocks 180 as well.
[0038]
Here, the H / V inversion driving will be briefly described with reference to FIG. FIG. 1 shows the polarities of the pixels divided into 6 rows and 6 columns for each frame. Further, it is assumed that pixels in 6 rows and 6 columns shown in FIG. 4 are written by one basic block shown in FIG.
[0039]
In the n frame, the polarities of the video signals supplied from the output terminal OUT1 to the R, G, and B columns are driven so that the positive and negative signs are inverted from each other in the adjacent signal lines, and from the output terminal OUT2 to the R, G, and B columns The polarity of the supplied video signal is driven so that the polarity is reversed from that of the output terminal OUT1. Further, in the n + 1 frame, the polarity of the video signal supplied to the R, G, and B columns is the reverse polarity of the n frame, and the polarity of the video signal written to the same signal line is similarly switched every one horizontal scanning period. The video signal writing order in each frame is the order of R pixel, B pixel, and G pixel in each row.
[0040]
When the H / V inversion driving as described above is performed, the pixel potential varies due to the coupling between the own pixel-own signal line, the own pixel-adjacent signal line, and the own signal line-adjacent signal line. In the present embodiment, since the order of writing video signals to each pixel is the order of R pixel, B pixel, and G pixel in the horizontal direction, the pixel potential fluctuation is the third smallest due to the influence of coupling. The pixel to be written is a G pixel in which display unevenness is easily visible. As described above, since the pixel potential fluctuation amount of the G pixel in which the display unevenness is easily visible is the smallest, the display unevenness becomes difficult to be visually recognized, and a good display quality can be obtained as the entire screen.
[0041]
In the above embodiment, the order of writing the video signal to each pixel is the order of R pixel, B pixel, and G pixel in the horizontal direction. However, if the order is the third G pixel, the R pixel The order of the B pixels may be changed.
[0042]
【The invention's effect】
As described above, according to the liquid crystal display device according to the present invention, the pixel potential fluctuation amount of the G pixel in which display unevenness is easily visible can be reduced, so that one output of the drive IC is built in the array. Even in a configuration in which three writing switches are provided in one horizontal scanning period by connecting to three analog switches in the signal line driving circuit, the influence of display unevenness is reduced and good display quality is obtained. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a schematic configuration of a signal line driver circuit unit. (A) is a circuit block diagram of the basic block which comprises a signal line selection circuit. FIG. 4B is a circuit configuration diagram illustrating a configuration of a signal line driving IC and a signal line selection circuit.
FIG. 2 is a circuit configuration diagram schematically showing a configuration of a liquid crystal display device according to an embodiment.
FIG. 3 is a timing chart of analog switch control signals ASW1U, ASW2U, and ASW3U output from the control IC.
FIG. 4 is an explanatory diagram showing polarities of pixels divided into 6 rows and 6 columns for each frame;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 100 ... Pixel array part 110 ... TFT
DESCRIPTION OF SYMBOLS 120 ... Pixel electrode 130 ... Common electrode 140 ... Auxiliary capacitance element 150 ... Scan line drive circuit 160 ... Signal line drive circuit unit 170 ... Signal line selection circuit 180 ... Basic block 200 ... Array substrate 210 ... Pixel unit 300 ... Liquid crystal layer 400 ... TCP
410... Signal line driving IC
500 ... External drive circuit 600 ... Control IC

Claims (2)

A plurality of signal lines and a plurality of scanning lines wired to cross each other, a plurality of pixel transistors arranged at each intersection of the two lines, a plurality of pixel electrodes connected to each of the pixel transistors, and the pixels A liquid crystal panel having red, green, and blue color filters arranged for each electrode, a scanning line driving circuit that supplies a scanning signal to each scanning line, and the plurality of signal lines are N (N: 3 or more) N signal line driving ICs that serially output video signals for each signal line group when divided into (integer) signal line groups, and one horizontal scan of the video signals output from the signal line driving ICs N signal line selection circuits that switch to and output the corresponding signal line of each signal line group divided into three times within a period, and the video signal is switched to a predetermined signal line and output by the signal line selection circuit A control signal that defines the output order when A liquid crystal display device and a control signal generating circuit,
In the liquid crystal panel, one pixel electrode constitutes a small pixel, and large pixels having the same color arrangement composed of three small pixels colored by the red, green, and blue color filters are arranged in a matrix,
The signal line driving IC outputs video signals whose signs are inverted to each other to the adjacent signal lines within one horizontal scanning period, and the positive / negative of the video signal output to the same signal line every horizontal scanning period. Switch
The control signal generation circuit connects the video signal output in the third writing period among the three writing periods provided in one horizontal scanning period to the small pixel colored by the green color filter. Generating a control signal that determines the output order of the video signals to be output to a signal line;
A liquid crystal display device. In the signal line selection circuit, three analog switches are arranged for one output from the signal line driving circuit IC, and the source electrode of each analog switch is commonly connected to one output line from the signal line driving circuit IC. The gate electrode of each analog switch is connected to each supply line of the control signal, the drain electrode of each analog switch is connected to the corresponding signal line, and the control signal is output from the control signal generation circuit. The video signal output to one output line of the signal line driving circuit IC is written to the corresponding signal line by conducting between the source electrode and the drain electrode of each analog switch by a signal. 2. A liquid crystal display device according to 1.

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