JP6354355B2 - Electro-optical device, electronic apparatus, and control method of electro-optical device - Google Patents

Description

  The present invention relates to an electro-optical device, an electronic apparatus, and a control method for the electro-optical device.

  2. Description of the Related Art A liquid crystal device that is one embodiment of an electro-optical device is known to include a liquid crystal panel and a flexible printed circuit (hereinafter referred to as FPC) on which a drive circuit that drives the liquid crystal panel is mounted. ing. In this configuration, for example, a semiconductor integrated circuit (hereinafter referred to as an integrated circuit) such as an IC (Integrated Circuit) chip is mounted on the FPC as a data line driving circuit by a technique called COF (Chip On Film). . As a liquid crystal device having such a configuration, for example, Patent Document 1 discloses a technique for driving one liquid crystal panel using a plurality of FPCs on which integrated circuits are mounted.

Japanese Unexamined Patent Publication No. 2011-112666 (see paragraphs 0076 to 0095)

Incidentally, a plurality of scanning lines and a plurality of data lines are formed on the liquid crystal panel, and a pixel circuit is often provided in accordance with the intersection of the scanning lines and the data lines. Further, in a liquid crystal panel that displays a high-definition image, the interval between data lines is narrowed. When the data line driving circuit is provided outside the liquid crystal panel, the pitch of the input terminals for supplying the data signal to each data line is narrowed, and a short circuit between the input terminals becomes a problem. For this reason, a distribution circuit may be provided that supplies a data signal supplied to one input terminal to one of k (k is an arbitrary natural number) data lines in accordance with a timing signal.
In such a liquid crystal device, a data line driving circuit mounted on the FPC may have a function of supplying a data signal to the liquid crystal panel and a timing signal to the liquid crystal panel. In this case, the timing signal is supplied to the distribution circuit by the wiring inside the liquid crystal panel, and the wiring has a parasitic capacitance. For this reason, the timing signal is output to a capacitive load.
When one liquid crystal panel is driven using a plurality of data line driving circuits, the timing signal is usually supplied from one of the plurality of data line driving circuits to the liquid crystal panel.
However, since the timing signal is output to a capacitive load, it is necessary to use a transistor with high driving performance for the output stage of the timing signal in the data line driving circuit. Therefore, the power required for outputting the timing signal is not small for the data line driving circuit, and the data line driving circuit that outputs the timing signal has a larger load than the data line driving circuit that does not output the timing signal, and the amount of heat generation is also large. Increase.
Here, since the transistors constituting the data line driving circuit are elements whose input / output characteristics change depending on temperature, a data line driving circuit that supplies a data signal and a timing signal to the liquid crystal panel, and only a data signal is supplied to the liquid crystal panel. The present invention has been made in view of the above-described circumstances, in which there is a difference in the output characteristics of the data signal between the other data line driving circuits and the difference in the displayed gradation. When driving one electro-optical panel using two or more integrated circuits (for example, data line driving circuit), the output resulting from the difference in load between the integrated circuits (for example, data line driving circuit) It is an object of the present invention to provide an electro-optical device, an electronic apparatus, and an electro-optical device control method that reduce a difference in characteristics.

  In order to solve the above problems, an aspect of the electro-optical device of the present invention includes a first pixel group, a second pixel group, writing of a first data signal to the first pixel group, and the second pixel group. An electro-optical panel provided with a driving circuit for writing the second data signal, a first data signal, and a first signal capable of outputting a timing signal for controlling the driving circuit to the electro-optical panel. A circuit, and a second circuit capable of outputting the second data signal and the timing signal to the electro-optical panel. In the first period, the first circuit outputs the timing signal and the first data signal to the electro-optical panel. The second circuit outputs the second data signal to the electro-optical panel and stops outputting the timing signal. In the second period, the second circuit outputs the timing signal to the electro-optical panel. No. and outputs the second data signal to said electro-optical panel, wherein the first circuit stops the output of the first data signal and outputs it to the electro-optical panel and the timing signal, it is characterized.

According to this aspect, the first data signal to be supplied to the first pixel group is output from the first circuit, and the second data signal to be supplied to the second pixel group is output from the second circuit. The timing signal supplied to the driving circuit for writing the first data signal to the first pixel group and writing the second data signal to the second pixel group is output from the first circuit in the first period. In the second period, the signal is output from the second circuit. With this configuration, the load difference between the first circuit and the second circuit is reduced as compared with the configuration in which the timing signal is output from only one of the first circuit and the second circuit throughout the entire period. . Accordingly, since a difference in heat generation between the first circuit and the second circuit is less likely to occur, an element (for example, a transistor) whose input / output characteristics change according to temperature is used for the first circuit and the second circuit. Even so, a difference in output characteristics is less likely to occur between the first circuit and the second circuit.
In this aspect, the “drive circuit” may be, for example, a distribution circuit (demultiplexer) or a scanning line drive circuit, and the first circuit and the second circuit may be, for example, a data line drive circuit. When the “driving circuit” is a distribution circuit (demultiplexer), the “timing signal” may be a selection signal for operating the distribution circuit (demultiplexer).

  Another aspect of the electro-optical device according to the aspect of the invention is the electro-optical device according to one aspect described above, in which the electro-optical panel includes a first terminal to which the timing signal is supplied from the first circuit, and the first terminal. And a second terminal to which the timing signal is supplied from two circuits, and a wiring for electrically connecting the first terminal, the second terminal, and the driving circuit.

  According to this aspect, the timing signal input from the first circuit to the electro-optical panel via the first terminal is transmitted to the drive circuit, and the input from the second circuit to the electro-optical panel via the second terminal. The route through which the timing signal is transmitted to the drive circuit is electrically connected by wiring in the electro-optical panel. As a result, if a timing signal is output from either the first circuit or the second circuit, the configuration in which the timing signal is supplied to the drive circuit in the electro-optical panel can be achieved with a simple wiring inside the electro-optical panel. Realize.

  Another aspect of the electro-optical device according to the aspect of the invention is the electro-optical device according to one aspect described above, in which the electro-optical panel includes a plurality of scanning lines and a plurality of data lines, and the first pixel group. And the pixels belonging to the second pixel group are provided corresponding to the intersections of the data lines and the scanning lines, and the drive circuit includes N pixels belonging to the first pixel group based on the timing signal. (N is a natural number of 2 or more) A first selection circuit that outputs the first data signal to one data line selected from among the data lines, and N belonging to the second pixel group based on the timing signal And a second selection circuit for outputting the second data signal to one selected data line out of the two data lines.

  According to this aspect, the drive circuit in the electro-optical panel functions as a so-called demultiplexer, and the first circuit and the second circuit function as a so-called data line drive circuit. Accordingly, it is easy to simplify the configuration of the terminals that electrically connect the first circuit and the second circuit to the electro-optical panel.

  Another aspect of the electro-optical device according to the aspect of the invention is the electro-optical device according to the above-described aspect, in which the first control signal that is active in the first period and inactive in the second period, the first Generating a second control signal, the timing signal, the first data signal, and the second data signal that are active in two periods and inactive in the first period, and that generate the first control signal and the timing signal; And a controller that outputs the first data signal to the first circuit, and outputs the second control signal, the timing signal, and the second data signal to the second circuit, and the first circuit includes: The timing signal is output to the electro-optical panel based on the first control signal, and the second circuit outputs the timing signal based on the second control signal. And it outputs the serial electro-optical panel, and wherein the.

  According to this aspect, the output of the timing signal by the first circuit is controlled by the first control signal supplied from the control unit to the first circuit, and by the second control signal supplied from the control unit to the second circuit, The output of the timing signal by the second circuit is controlled. The first data signal and the timing signal are also supplied from the control unit to the first circuit, and the second data signal and the timing signal are also supplied from the control unit to the second circuit. Therefore, these signals can be collectively transmitted from the control unit to the first circuit and the second circuit by, for example, the LVDS method (Low Voltage Differential Signaling), and various signal transmission paths can be set. It becomes easy to simplify.

  Another aspect of the electro-optical device according to the aspect of the invention is the electro-optical device according to one aspect described above, in which the first circuit is provided on a first flexible substrate, and the second circuit is a second circuit. It is provided on a flexible substrate.

  According to this aspect, the first circuit and the second circuit are each electrically connected to the electro-optical panel via the wiring on the flexible substrate, and an electro-optical device in which the configuration is simplified is provided.

  According to another aspect of the invention, there is provided an electronic apparatus including the electro-optical device according to any one of the above-described electro-optical devices.

  According to this aspect, an electronic apparatus having the same effects as the electro-optical device according to each aspect described above is provided.

  An electro-optical device control method according to an aspect of the present invention includes a first pixel group, a second pixel group, writing of a first data signal to the first pixel group, and second data to the second pixel group. An electro-optical panel provided with a control circuit for controlling signal writing; a first circuit capable of outputting the first data signal; and a timing signal for controlling the control circuit to the electro-optical panel; 2. A control method of an electro-optical device including a second circuit capable of outputting two data signals and the timing signal to the electro-optical panel, wherein the first circuit includes the timing signal and the first circuit in a first period. 1 data signal is output to the electro-optical panel, and the second circuit is controlled to output the second data signal to the electro-optical panel and stop outputting the timing signal, and during the second period, The second circuit outputs the timing signal and the second data signal to the electro-optical panel, and the first circuit outputs the first data signal to the electro-optical panel and stops outputting the timing signal. It controls so that it may do.

According to this aspect, the first data signal to be supplied to the first pixel group is output from the first circuit, and the second data signal to be supplied to the second pixel group is output from the second circuit. The timing signal supplied to the driving circuit for writing the first data signal to the first pixel group and writing the second data signal to the second pixel group is output from the first circuit in the first period. In the second period, the signal is output from the second circuit. With this configuration, the load difference between the first circuit and the second circuit is reduced as compared with the configuration in which the timing signal is output from only one of the first circuit and the second circuit throughout the entire period. . Accordingly, since a difference in heat generation between the first circuit and the second circuit is less likely to occur, an element (for example, a transistor) whose input / output characteristics change according to temperature is used for the first circuit and the second circuit. Even so, a difference in output characteristics is less likely to occur between the first circuit and the second circuit.
In this aspect, the “drive circuit” may be a demultiplexer (distribution circuit), for example, and the first circuit and the second circuit may be data line drive circuits, for example. When the “drive circuit” is a demultiplexer (distribution circuit), the “timing signal” may be a selection signal for operating the demultiplexer (distribution circuit).

  In order to solve the above problems, an aspect of the electro-optical device of the present invention includes a first pixel group, a second pixel group, writing of a first data signal to the first pixel group, and the second pixel group. An electro-optical panel provided with a driving circuit for writing the second data signal, a first data signal, and a first signal capable of outputting a timing signal for controlling the driving circuit to the electro-optical panel. A circuit, and a second circuit capable of outputting the second data signal and the timing signal to the electro-optical panel, and in the first period, the drive circuit is either the first circuit or the second circuit. The driving circuit is controlled by the timing signal output from either the first circuit or the second circuit in the second period. , Characterized in that.

According to this aspect, the first data signal to be supplied to the first pixel group is output from the first circuit, and the second data signal to be supplied to the second pixel group is output from the second circuit. A driving circuit for writing the first data signal to the first pixel group and writing the second data signal to the second pixel group is controlled by the timing signal output from the first circuit in the first period. The second period is controlled by the timing signal output from the second circuit. With this configuration, the load difference between the first circuit and the second circuit is reduced as compared with the configuration in which only one of the first circuit and the second circuit outputs the timing signal throughout the entire period. Accordingly, since a difference in heat generation between the first circuit and the second circuit is less likely to occur, an element (for example, a transistor) whose input / output characteristics change according to temperature is used for the first circuit and the second circuit. Even so, a difference in output characteristics is less likely to occur between the first circuit and the second circuit.
In this aspect, the “drive circuit” may be, for example, a distribution circuit (demultiplexer) or a scanning line drive circuit, and the first circuit and the second circuit may be, for example, a data line drive circuit. When the “driving circuit” is a distribution circuit (demultiplexer), the “timing signal” may be a selection signal for operating the distribution circuit (demultiplexer).

1 is a perspective view illustrating a configuration example of a main part of an electro-optical device according to an embodiment of the invention. The figure which shows the circuit structure of a display part. The circuit diagram of a pixel circuit. FIG. 6 is a diagram illustrating the operation of the electro-optical device. 10A and 10B illustrate how a selection signal is supplied to a display portion. FIG. 10 is a diagram for explaining timing related to the output of a selection signal by the first to fourth data line driver circuits. The figure explaining the modification of one Embodiment of this invention. The figure explaining the application example of one Embodiment of this invention.

FIG. 1 is a perspective view illustrating a configuration example of a main part of the electro-optical device 1. As shown in the figure, the electro-optical device 1 includes an electro-optical panel 150 including a display unit 100, a first flexible circuit board (hereinafter referred to as a first FPC) 300a on which a first data line driving circuit 200a is mounted. A second flexible circuit board (hereinafter referred to as a second FPC) 300a on which the second data line driving circuit 200b is mounted and a third flexible circuit board (hereinafter referred to as a third FPC) on which the third data line driving circuit 200c is mounted. .) 300c and a fourth flexible circuit board (hereinafter referred to as a fourth FPC) 300d on which the fourth data line driving circuit 200d is mounted.
Each of the first to fourth data line driving circuits 200a to 200d is constituted by, for example, a one-chip IC, and is mounted on each of the first to fourth FPCs 300a to 300d by a COF (Chip On Film) technique.

As shown in FIG. 1, the display unit 100 is divided into a first region 100a, a second region 100b, a third region 100c, and a fourth region 100d for each display region.
A wiring (not shown) for transmitting signals is provided on the first FPC 300a to the fourth FPC 300d, and one end of the wiring is connected to a signal input terminal (not shown) in the electro-optical panel 150. The other end of the wiring is connected to a substrate (not shown), and a control unit 250 (see FIG. 2) is provided on the substrate. That is, the first to fourth data line driving circuits 200a to 200d are electrically connected to the electro-optical panel 150 and the control unit 250 (see FIG. 2) via the wirings on the first FPC 300a to the fourth FPC 300d. .

  FIG. 2 is a diagram illustrating a circuit configuration of the display unit 100. Since each of the first region 100a to the fourth region 100d has the same configuration, the configuration of the first region 100a will be described here in order to avoid overlapping description.

In the pixel portion 10, M scanning lines 12 and N data lines 14 that intersect with each other are formed (M and N are natural numbers of 2 or more). In the pixel portion 10, a pixel circuit PIX is arranged corresponding to the intersection of the scanning line 12 and the data line 14. That is, the pixel circuits PIX are arranged in a matrix of vertical M rows × horizontal N columns.
The pixel circuit PIX in the pixel unit 10 is divided into one of J pixel blocks B [1] to B [J] as shown in FIG. Specifically, the N data lines 14 in the pixel unit 10 are connected to the same distribution circuit 57 [j (j is an arbitrary natural number satisfying 1 ≦ j ≦ J)] for every four consecutively arranged data lines. When connected, a set of pixels connected to the same distribution circuit 57 [j] is defined as one pixel block B [j]. Note that the relationship of J = N / 4 is established.

The distribution circuits 57 [1] to 57 [J] are connected to the first data line driving circuit 200a by J control lines 15 corresponding to the pixel blocks B [1] to B [J]. .
The jth distribution circuit 57 [j] distributes the image signal D [j] supplied to the jth control line 15 to each of the four data lines 14 corresponding to the pixel block B [j]. The circuit (demultiplexer) includes four switches 58 [1] to 58 [4] related to the data line 14 corresponding to the pixel block B [j]. The x-th switch 58 [x] of the distribution circuit 57 [j] includes the x-th data line 14 and the J control lines 15 among the four data lines 14 of the pixel block B [j]. It is interposed between the j-th control line 15 and controls electrical connection (conduction / non-conduction) between them.

  Here, a set of pixel circuits PIX driven by the first data line driving circuit 200a is referred to as a “first pixel group”, and a set of pixel circuits PIX driven by the second data line driving circuit 200b is referred to as a “second pixel”. A group of pixel circuits PIX driven by the third data line driving circuit 200c is called a “third pixel group”, and a group of pixel circuits PIX driven by the fourth data line driving circuit 200d is called a “group”. This is referred to as a “four pixel group”. That is, each of the first to fourth pixel groups includes a plurality of pixel blocks B [j]. Specifically, in the present embodiment, the pixel blocks B [1] to B [J] in the first region 100a all belong to the first pixel group, and the pixel blocks in the second region 100b all belong to the second pixel group. All the pixel blocks in the third region 100c belong to the third pixel group, and all the pixel blocks B [1] to B [J] in the fourth region 100d belong to the fourth pixel group.

  FIG. 3 is a circuit diagram of each pixel circuit PIX. As shown in FIG. 3, each pixel circuit PIX includes a liquid crystal element 42 and a selection switch 44. The liquid crystal element 42 is an electro-optical element that includes a pixel electrode 421 and a common electrode 423 facing each other and a liquid crystal 425 between the two electrodes. The transmittance of the liquid crystal 425 changes according to the voltage applied between the pixel electrode 421 and the common electrode 423. In the following description, for the sake of convenience, the voltage applied to the liquid crystal element 42 when the pixel electrode 421 has a higher potential than the common electrode 423 is expressed as positive polarity, and the pixel electrode 421 has a low potential. The applied voltage is expressed as negative polarity.

  The selection switch 44 is composed of an N-channel type thin film transistor having a gate connected to the scanning line 12, and is interposed between the liquid crystal element 42 (pixel electrode 421) and the data line 14 to electrically connect them ( (Conduction / non-conduction) is controlled. Therefore, the pixel circuit PIX (the liquid crystal element 42) displays a gradation corresponding to the potential of the data line 14 (a gradation corresponding to the image signal D [j]) when the selection switch 44 is controlled to be in the ON state. . Note that illustration of an auxiliary capacitor connected in parallel to the liquid crystal element 42 is omitted.

  Returning to FIG. The controller 250 outputs, for example, a digital transmission system signal called LVDS (Low Voltage Differential Signaling). The LVDS signals output from the control unit 250 include, for example, a vertical synchronization signal Vs, a horizontal synchronization signal Hs, selection signals S1 to S4, image signals D [1] to D [J], and control signals CTLa to CTLd. included. The controller 250 controls the first to fourth data line driving circuits 200a to 200d by supplying these various signals.

In addition, the control unit 250 generates four systems of selection signals S1 to S4 corresponding to the number of data lines 14 in each pixel block B [j] and outputs them to the first to fourth data line driving circuits 200a to 200d. To do. The selection signals S1 to S4 are timing signals that control the timing of writing data signals by the J distribution circuits 57 [1] to 57 [J] described above.
Here, the J distribution circuits 57 [1] to 57 [J] each include four switches 58 [1] to 58 [4]. The switches 58 [1] to 58 [4] include control input terminals (not shown) to which signals (selection signals S1 to S4) for switching between ON and OFF are input, and the control input terminals (not shown) ) Is switched on and off in accordance with the level of the signal input to. That is, the distribution circuits 57 [1] to 57 [J] function as drive circuits for writing data signals to a predetermined pixel group.

  Here, the selection signal S1 is a first switch 58 [1] in each of the J distribution circuits 57 [1] to 57 [J] (a total of J switches 58 [1] in the signal distribution circuit 54). This signal is supplied in parallel to a control input terminal (not shown) and controls on / off of the switch 58 [1]. Similarly, the selection signal S2 is supplied to a control input terminal (not shown) of the second switch 58 [2], and is a signal for controlling on / off of the switch 58 [2]. This signal is supplied to a control input terminal (not shown) of the third switch 58 [3] and controls on / off of the switch 58 [3], and the selection signal S4 is the fourth switch 58 [4]. ] Is a signal for controlling on / off of.

Since the selection signals S1 to S4 are common to the regions 100a, 100b, 100c, and 100d, at least one of the first to fourth data line driving circuits 200a to 200d outputs the selection signals S1 to S4. (Selection signals S1 to S4 are set to active levels) and supplied to the electro-optical panel 150.
Incidentally, since the wiring for transmitting the selection signals S1 to S4 is routed to the first region 100a to the fourth region 100d inside the electro-optical panel 150, the length of the wiring is the parasitic capacitance related to the wiring. Sometimes it is not short enough to be ignored. Therefore, the load when the electro-optical panel 150 is viewed from the output stage of the selection signals S1 to S4 in the first to fourth data line driving circuits 200a to 200d is a capacitive load. Therefore, a transistor having high driving capability is used in the signal output stage in the first to fourth data line driving circuits 200a to 200d.
Therefore, the power required for the output of the selection signals S1 to S4 is not small for the first to fourth data line driving circuits 200a to 200d, and the selection signals S1 to S4 are electrically transmitted in addition to the image signals D [1] to [J]. The data line driving circuit supplied to the optical panel 150 has a larger load and heat generation than the other data line driving circuits that supply only the image signals D [1] to [J] to the electro-optical panel 150. Increase.

Accordingly, if the selection signals S1 to S4 are output in addition to the image signals D [1] to [J] to only one specific data line driving circuit, only the image signals D [1] to [J] are output. There is a temperature difference with other data line driving circuits that output. Here, since the input / output characteristics of the transistors constituting the first to fourth data line driving circuits 200a to 200d change depending on the temperature, the image signals D [1] to [J] and the timing signal are supplied to the electro-optical panel 150. A difference in output characteristics occurs between the data line driving circuit that performs this operation and another data line driving circuit that supplies only the image signals D [1] to [J] to the electro-optical panel 150.
That is, the data line driving circuit that supplies the selection signals S1 to S4 to the electro-optical panel 150 in addition to the image signals D [1] to [J] has the same gradation as the other data line driving circuits. Even if [1] to [J] are input, there is a possibility that the image signals D [1] to [J] specifying gradations different from those of other data line driving circuits may be output.
Therefore, in the present embodiment, in order to equalize the loads of the first data line driving circuit 200a to the fourth data line driving circuit 200d, the control unit 250 performs the first data line driving circuit 200a to the fourth data line driving circuit 200d. Among them, one circuit that outputs the selection signals S1 to S4 to the electro-optical panel 150 is controlled to be switched every horizontal scanning period H.
Note that the control by the control unit 250 which outputs the selection signals S1 to S4 to any of the first to fourth data line driving circuits 200a to 200d will be described in detail later with reference to FIG.

FIG. 4 is a diagram for explaining the operation of the electro-optical device 1. In FIG. 4, the reference numerals in parentheses immediately after the selection signals S1 to S4 indicate the reference numerals of the data line driving circuit that outputs the selection signals S1 to S4. That is, in the example illustrated in FIG. 4, the first data line driving circuit 200a outputs the selection signals S1 to S4 and the second to fourth data line driving circuits 200b to 200d are controlled by the control unit 250. The output of S4 is stopped.
Note that, as shown in FIG. 4, the control unit 250 displays an image signal in which the polarity of the voltage applied to the liquid crystal element 42 is inverted every vertical scanning period (in the vertical scanning period V1 and the vertical scanning period V2 in FIG. 4). D [j] is supplied to the first to fourth data line driving circuits 200a to 200d.
Returning to FIG. The scanning line driving circuit 22 in FIG. 2 sequentially selects each of the M scanning lines 12 by supplying scanning signals G [1] to G [M] to each scanning line 12. That is, the scanning line driving circuit 22 functions as a driving circuit for writing a data signal to each pixel group.

  The scanning signal G [m] supplied to the mth (m is a natural number of 1 ≦ m ≦ M) rows of scanning lines 12 is M horizontal scanning periods in each vertical scanning period V as shown in FIG. It is set to a high level (potential meaning selection of the scanning line 12) in the m-th horizontal scanning period H of H. When the scanning line driving circuit 22 selects the m-th scanning line 12, the selection switches 44 of the N pixel circuits PIX in the m-th row are turned on.

  Here, the first data line driving circuit 200 a controls the potential of each of the N data lines 14 in synchronization with the selection of each scanning line 12 by the scanning line driving circuit 22. As shown in FIG. 2, the first data line driving circuit 200 a supplies the J system image signals D [1] to D [J] corresponding to the pixel blocks B [1] to B [J] to the control lines 15. Supply in parallel.

  Returning to FIG. Each horizontal scanning period H in which the scanning line driving circuit 22 selects the scanning line 12 includes a precharge period TPRE and a writing period TWRT. In the example shown in FIG. 4, the precharge period TPRE is provided in all the horizontal scanning periods H, but the precharge period TPRE may be provided in one or more horizontal scanning periods H. Further, in the example shown in FIG. 4, in order to focus on the features of the present embodiment without complicating the drawing, a post-charge period in which a so-called post-charge potential is supplied to each control line 15 within the horizontal scanning period H. However, it is of course possible to provide a post-charge period. Note that the post-charge period is a predetermined post-charge potential so that the potential between the pixel electrode 421 and the common electrode 423 does not vary between the pixels at the start of the next horizontal scanning period H. Is written in the control line 15.

In each of the vertical scanning periods V1 and V2, first, the first data line driving circuit 200a outputs the selection signals S1 to S4 simultaneously in the precharge period TPRE within the horizontal scanning period H. In other words, the first data line driving circuit 200a sets the selection signals S1 to S4 to the active level in the precharge period TPRE within the horizontal scanning period H.
At this time, in the precharge period TPRE in each horizontal scanning period H, all the switches 58 [1] to [4] in the signal distribution circuit 54 are turned on, and each of the N data lines 14 (and moreover A precharge potential VPRE is supplied to the pixel electrode 421) in each pixel circuit PIX.
As described above, the potential of each data line 14 is initialized to the precharge potential VPRE before the image signal D [j] is supplied to each pixel circuit PIX (before writing). Crosstalk) can be prevented.
Here, the precharge potential VPRE is set to a negative or positive potential for each vertical scanning period with respect to a predetermined reference potential VREF (for example, a potential that is the amplitude center of the image signal D [j]). .
On the other hand, in the writing period TWRT in each horizontal scanning period H, the first data line driving circuit 200a sequentially outputs the selection signals S1 to S4 (sets to the active level). Therefore, in each unit period U [k (k is a natural number satisfying 1 ≦ k ≦ 4)] in the horizontal scanning period H in which the m-th row scanning line 12 is selected, the distribution circuits 57 [1] to 57 [J ], Among the four switches 58 [1] to 58 [4], the kth switch 58 [k] (a total of J switches 58 [k] in the signal distribution circuit 54) is turned on. Then, the gradation potential of the image signal D [j] is supplied to the k-th data line 14 of each pixel block B [j].
That is, in the writing period TWRT, the gradation potential is supplied to the four data lines 14 in the pixel block B [j] in each of the J pixel blocks B [1] to B [J] in a time division manner. The In the unit period U [k] in the mth horizontal scanning period H, the gradation potential is the intersection of the mth row scanning line 12 and the kth column data line 14 in the pixel block B [j]. Is set according to the designated gradation of the pixel circuit PIX corresponding to.

  As described above, the first region 100a among the first region 100a to the fourth region 100d constituting the display unit 100 of the electro-optical panel 150 has been described with reference to FIGS. The second region 100b driven by 200b, the third region 100c driven by the third data line driving circuit 200c, and the fourth region 100d driven by the fourth data line driving circuit 200d are the same as the first region 100a. And operates in the same manner. The driving method of the second to fourth regions 100b to 100d by the second to fourth data line driving circuits 200b to 200d is the same as the driving method of the first region 100a by the first data line driving circuit 200a.

FIG. 5 is a diagram illustrating a manner of supplying the selection signals S1 to S4 to the electro-optical panel 150. The selection signals S1 to S4 generated by the controller 250 are output to the first to fourth data line driving circuits 200a to 200d. Then, under the control of the control unit 250, one of the first to fourth data line driving circuits 200a to 200d sends the selection signals S1 to S4 to the J distribution circuits 57 [1] to 57 [J]. Output.
As shown in FIG. 5, the supply paths of the selection signal S1 from the first to fourth data line driving circuits 200a to 200d are mutually in the electro-optical panel 150 at the node n1 on the transmission path of the selection signal S1. It is connected. The supply paths of the selection signal S2 from the first to fourth data line driving circuits 200a to 200d are connected to each other at the node n2 on the transmission path of the selection signal S2 in the electro-optical panel 150. The supply paths of the selection signal S3 from the first to fourth data line driving circuits 200a to 200d are connected to each other at the node n3 on the transmission path of the selection signal S3 in the electro-optical panel 150. The supply paths of the selection signal S4 from the first to fourth data line drive circuits 200a to 200d are connected to each other at the node n4 on the transmission path of the selection signal S4 in the electro-optical panel 150.

FIG. 6 is a diagram for explaining control of the timing at which the selection signals S1 to S4 are output to the first to fourth data line driving circuits 200a to 200d. In the figure, the reference numerals in parentheses immediately after the selection signals S1 to S4 indicate the reference numerals of the data line driving circuit that outputs the selection signals S1 to S4.
As described above, in this embodiment, in order to make the loads of the first to fourth data line driving circuits 200a to 200d uniform, the control unit 250 includes the first to fourth data line driving circuits 200a to 200d. Control is performed so that one circuit that outputs the selection signals S1 to S4 to the electro-optical panel 150 is switched every horizontal scanning period H. The control by the control unit 250 includes the supply of the control signal CTLa to the first data line driving circuit 200a, the supply of the control signal CTLb to the second data line driving circuit 200b, and the control signal CTLc to the third data line driving circuit 200c. And the supply of the control signal CTLd to the fourth data line driving circuit 200d.

Specifically, the first to fourth data line driving circuits 200a to 200d are in a state where the control signals CTLa to CTLd are set to the inactive level (the state where the control signals CTLa to CTLd set to the active level are not supplied). ), The output stages of the selection signals S1 to S4 are set inactive (high impedance), and the output of the selection signals S1 to S4 is stopped.
On the other hand, the first to fourth data line driving circuits 200a to 200d set the output stages of the selection signals S1 to S4 to active in the state where the control signals CTLa to CTLd set to the active level are supplied. S1 to S4 are output and supplied to the electro-optical panel 150.
The specific output modes of the selection signals S1 to S4 in the precharge period TPRE and the write period TWRT are as described with reference to FIG.

In the example illustrated in FIG. 6, the control unit 250 outputs the horizontal synchronization signal Hs and sets any one of the control signals CTLa to CTLd to an active level until the next horizontal synchronization signal Hs is output. Control signals CTLa to CTLd are maintained at an active level. Here, the control unit 250 sequentially switches the control signals CTLa to CTLd set to the active level for each horizontal scanning period H. By such control of the control unit 250, the data line driving circuit that outputs the selection signals S1 to S4 is sequentially switched every horizontal scanning period H.
Specifically, in the example shown in FIG. 6, the first data line driving circuit 200a → the second data line driving circuit 200b → the third data line driving circuit 200c → the fourth data line driving circuit 200d → the first data line driving circuit. The data line driving circuit that outputs the selection signals S1 to S4 is switched every horizontal scanning period H in the order of 200a →.

In the above-described embodiment, the data line driving circuit that outputs the selection signals S1 to S4 (set to the active level) is switched every horizontal scanning period H. However, the present invention is not limited to this mode. Of course, it may be switched every horizontal scanning period H. The first data line driving circuit 200a, the second data line driving circuit 200b, the third data line driving circuit 200c, the fourth data line driving circuit 200d, the first data line driving circuit 200a, and so on are switched in this order. It is not necessary, and it may be controlled so that the selection signals S1 to S4 are not continuously output to one specific data line driving circuit in any order.
As described above, in the present embodiment, compared to the configuration in which only one specific data line driving circuit among the first to fourth data line driving circuits 200a to 200d continues to output the selection signals S1 to S4, Since the loads of the first to fourth data line driving circuits 200a to 200d can be made uniform, it is possible to suppress a difference in output characteristics between the data line driving circuits.

<< First Modification >>
In the above-described embodiment, for convenience of explanation, each region of the first region 100a to the fourth region 100d of the display unit 100 and each data line driver circuit of the first to fourth data line driver circuits 200a to 200d are included. The display unit 100 is driven in a one-to-one correspondence. However, it is needless to say that the driving mode is not limited to this, and for example, the driving mode shown in FIG. 7 may be adopted. That is, as shown in FIG. 7, the first data line driving circuit 200a → the driving by the second data line driving circuit 200b → the third data line driving circuit in ascending order of the value of “j” of the pixel block B [j]. The first to fourth data line driving circuits 200a to 200d are connected to each pixel block in the order of driving by 200c → driving by the fourth data line driving circuit 200d → driving by the first data line driving circuit 200a →. Of course, it may be allocated as a data line driving circuit of j].
Accordingly, when x is an integer greater than or equal to zero, in this modification, the pixel block B [4x + 1] is the first pixel group driven by the first drive circuit 200a, and the pixel block B [4x + 2] is the second drive circuit 200b. The pixel block B [4x + 3] is a third pixel group driven by the third drive circuit 200c, and the pixel block B [4x + 4] is driven by the fourth drive circuit 200d. This is a fourth pixel group.

<< Second Modification >>
In the above-described embodiment, from the viewpoint of solving the problems of the prior art, the control method for equalizing the load related to the output of the selection signals S1 to S4 among the first to fourth data line driving circuits 200a to 200d. Explained. However, the control method unique to the above-described embodiment can also be applied to processing other than the processing related to the output of the selection signals S1 to S4. For example, in the same manner as in the above-described embodiment, when one electro-optical device is driven by a plurality of drive circuits and the scanning line drive circuit includes a shift register, an enable signal for operating the shift register The control method peculiar to the above-described embodiment can be applied to the control of the drive circuit that outputs the signal. In this case, the control unit controls the plurality of drive circuits so as to switch one drive circuit that outputs the enable signal, for example, every horizontal scanning period.

《Application example》
In the above-described embodiment, the liquid crystal display device has been described as an example of the electro-optical device. However, the above-described embodiment can also be applied to other types of display devices such as an organic EL display (Organic Electro-Luminescence Display: OELD).
Further, the electro-optical device according to the above-described embodiment can be used for various electronic apparatuses. FIG. 8 is a schematic diagram of a projection display device (three-plate projector) 4000 to which the electro-optical device 1 is applied. The projection display device 4000 includes three electro-optical devices 1 (1R, 1G, 1B) corresponding to different display colors (red, green, blue). The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device (light source) 4002 to the electro-optical device 1R, the green component g to the electro-optical device 1G, and the blue component b to the electro-optical device 1B. To supply. Each electro-optical device 1 functions as a light modulator (light valve) that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. The projection optical system 4003 synthesizes the emitted light from each electro-optical device 1 and projects it onto the projection surface 4004.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Pixel part, 12 ... Scan line, 14 ... Data line, 15 ... Control line, 22 ... Scan line drive circuit, 250 ... Control part, 42 ... Liquid crystal element, 44 ... Selection switch, 54 ... Signal distribution circuit 57 ... Distribution circuit 58 ... Switch 100 ... Display unit 100a ... First region 100b ... Second region 100c ... Third region 100d ... Fourth region 150 ... Electro-optical panel 200a ... First data line driving circuit, 200b ... second data line driving circuit, 200c ... third data line driving circuit, 200d ... fourth data line driving circuit, 421 ... pixel electrode, 423 ... common electrode, B ... pixel block, CTLa ... control signal, CTLa to CTLd ... control signal, PIX ... pixel circuit, S1 to S4 ... selection signal.

Claims (8)

A first pixel group and a second pixel group, and a drive circuit for writing a first data signal to the first pixel group and writing a second data signal to the second pixel group are provided. An electro-optic panel;
A first circuit capable of outputting the first data signal and a timing signal for controlling the driving circuit to the electro-optical panel;
A second circuit capable of outputting the second data signal and the timing signal to the electro-optical panel;
In the first horizontal scanning period , the first circuit outputs the timing signal and the first data signal to the electro-optical panel, the second circuit outputs the second data signal to the electro-optical panel, and Stop outputting the timing signal,
In a second horizontal scanning period that is continuous with the first horizontal scanning period , the second circuit outputs the timing signal and the second data signal to the electro-optical panel, and the first circuit outputs the first data. Outputting a signal to the electro-optical panel and stopping the output of the timing signal;
An electro-optical device. The electro-optical panel is
A first terminal to which the timing signal is supplied from the first circuit;
A second terminal to which the timing signal is supplied from the second circuit;
Wiring for electrically connecting the first terminal, the second terminal, and the drive circuit;
The electro-optical device according to claim 1, comprising: The electro-optical panel includes a plurality of scanning lines and a plurality of data lines,
The pixels belonging to the first pixel group and the second pixel group are provided corresponding to the intersection of the data line and the scanning line,
The drive circuit is
A first selection circuit for outputting the first data signal to one data line selected from N (N is a natural number of 2 or more) data lines belonging to the first pixel group based on the timing signal;
A second selection circuit that outputs the second data signal to one data line selected from the N data lines belonging to the second pixel group based on the timing signal;
The electro-optical device according to claim 1 or 2. Wherein becomes active in the first horizontal scanning period, and the first control signal becomes inactive in the second horizontal scanning period becomes active in the second horizontal scanning period, and non at the first horizontal scanning period The second control signal, the timing signal, the first data signal, and the second data signal that are activated are generated, and the first control signal, the timing signal, and the first data signal are output to the first circuit. And a control unit that outputs the second control signal, the timing signal, and the second data signal to the second circuit,
The first circuit outputs the timing signal to the electro-optical panel based on the first control signal,
The second circuit outputs the timing signal to the electro-optical panel based on the second control signal.
The electro-optical device according to any one of claims 1 to 3.   5. The first circuit according to claim 1, wherein the first circuit is provided on a first flexible substrate, and the second circuit is provided on a second flexible substrate. 6. Electro-optic device.   An electronic apparatus comprising the electro-optical device according to claim 1. An electro-optical device provided with a first pixel group and a second pixel group, and a control circuit for controlling writing of a first data signal to the first pixel group and writing of a second data signal to the second pixel group. A first circuit capable of outputting a panel, the first data signal, and a timing signal for controlling the control circuit to the electro-optical panel; and outputting the second data signal and the timing signal to the electro-optical panel. A control method for an electro-optical device comprising a second circuit capable of:
In the first horizontal scanning period , the first circuit outputs the timing signal and the first data signal to the electro-optical panel, the second circuit outputs the second data signal to the electro-optical panel, and Control to stop the output of the timing signal,
In a second horizontal scanning period that is continuous with the first horizontal scanning period , the second circuit outputs the timing signal and the second data signal to the electro-optical panel, and the first circuit outputs the first data. Control to output a signal to the electro-optical panel and stop outputting the timing signal;
A control method for an electro-optical device. A first pixel group and a second pixel group, and a drive circuit for writing a first data signal to the first pixel group and writing a second data signal to the second pixel group are provided. An electro-optic panel;
A first circuit capable of outputting the first data signal and a timing signal for controlling the driving circuit to the electro-optical panel;
A second circuit capable of outputting the second data signal and the timing signal to the electro-optical panel;
In the first horizontal scanning period , the driving circuit is controlled by the timing signal output from either the first circuit or the second circuit,
In a second horizontal scanning period that is continuous with the first horizontal scanning period , the driving circuit is controlled by the timing signal output from either the first circuit or the second circuit.
An electro-optical device.

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