JP2004309949A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a good display grade by reducing display unevenness when H/V inversion driving is performed with a liquid crystal display device provided with the time for writing three times within one horizontal scanning period by connecting one output of a driving IC to three analog switches SW in a signal line driving circuit. <P>SOLUTION: The liquid crystal display device is constituted by determining the order of output of video signals which are the signal ASW1U to ASW3U for analog switch control to be supplied to the analog switches SW in such a manner the video signals outputted in the third time of the writing periods among three times of the writing periods disposed within the one horizontal scanning period are outputted to the signal lines connected to G pixels (G1, G2). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix liquid crystal display device that performs H / V inversion driving.
[0002]
[Prior art]
2. Description of the Related Art In recent years, liquid crystal display devices have been expanding their market share as displays for personal computers, home televisions, and the like, and liquid crystal display devices with high resolution and large screen size have been available at relatively low prices. Among them, an active matrix type liquid crystal display device (hereinafter, a liquid crystal display device) in which pixel transistors are arranged in the vicinity of intersections of signal lines and scanning lines arranged in a matrix is excellent in coloring properties and has few afterimages. It is considered to become the mainstream in the future.
[0003]
Among them, a liquid crystal display device using an amorphous silicon TFT requires connection wiring for inputting a video signal from a TCP (Tape Carrier Package) to each signal line on an array substrate, which is accompanied by higher definition of pixels. As a result, the number of connection wirings increases, and it is difficult to secure a sufficient pitch between these connection wirings. On the other hand, in a liquid crystal display device using pixel transistors made of polycrystalline silicon, in addition to the scanning line driving circuit and the signal line driving circuit formed integrally on the array substrate, external connection components are reduced and cost is reduced. This has the advantage that the number of connection wirings can be reduced.
[0004]
In addition, as a method of driving each signal line, that is, a method of writing a video signal from each signal line to each pixel, a video signal whose polarity is inverted to each other is written to an adjacent signal line and one vertical scanning period V-line inversion drive for switching the polarity of a video signal written to the signal line every time, or video signals of opposite polarity are written to adjacent signal lines within one horizontal scanning period, and the same for each horizontal scanning period H / V inversion driving for switching between positive and negative of a video signal written to the signal line is general.
[0005]
Further, in order to further reduce the cost of the drive IC as an external connection component, the output voltage from the drive IC is connected to three analog switches in the signal line drive circuit formed on the array substrate. There is a display device in which three writing times are provided in one horizontal scanning period.
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-109435
[Problems to be solved by the invention]
When the H / V inversion driving is performed in the circuit configuration in which the driving ICs are reduced as described above, the pixel potential is influenced by the coupling between the own pixel and the own signal line, the own pixel and the adjacent signal line, and the own signal line and the adjacent signal line. Since the voltage fluctuates and the amount of fluctuating pixel potential differs for each pixel, display unevenness may occur.
[0008]
Conventionally, when three writing times are provided within one horizontal scanning period, the order of writing video signals to pixels is as follows: the order of R (red) pixels, G (green) pixels, and B (blue) pixels in the horizontal direction. It has become. On the other hand, the amount of change in the pixel potential due to the coupling is the smallest in the pixel to be written third, so that the pixel potential change amount of the B pixel is the smallest, and conversely, display unevenness is likely to be visually recognized. Since the fluctuation amount of the pixel potential of the pixel becomes large, the display unevenness is more easily recognized.
[0009]
An object of the present invention is to provide a configuration in which one output of a driving IC is connected to three analog switches in a signal line driving circuit built in an array substrate, and three writing times are provided in one horizontal scanning period. It is another object of the present invention to provide a liquid crystal display device capable of reducing display unevenness when performing H / V inversion driving and obtaining good display quality.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 includes a plurality of signal lines and a plurality of scanning lines that are wired to cross each other, a plurality of pixel transistors disposed at each intersection of the two lines, A plurality of pixel electrodes connected to each pixel transistor, a liquid crystal panel having red, green, and blue color filters arranged for each of the pixel electrodes, and a scanning line driving circuit for supplying a scanning signal to each of the scanning lines And N signal line driving ICs that serially output video signals for each signal line group when the plurality of signal lines are divided into N (N: an integer of 3 or more) signal lines, N signal line selection circuits for dividing the video signal output from the signal line driving IC into three times within one horizontal scanning period and switching to the corresponding signal line of each of the signal line groups, and outputting the signal lines; Selective circuit sends the video signal to a predetermined signal line A control signal generation circuit that generates a control signal that determines the output order when the output is switched and output, wherein the liquid crystal panel is configured such that one of the pixel electrodes forms a small pixel, Large pixels of the same color arrangement composed of three small pixels colored by respective color filters of red, green and blue are arranged in a matrix, and the signal line driving ICs are adjacent to each other within one horizontal scanning period. A video signal whose polarity is inverted to each other is output to a signal line, and the polarity of a video signal output to the same signal line is switched every one horizontal scanning period. The control signal generation circuit is provided within one horizontal scanning period. The output order of the video signals is changed so that the video signal output in the third writing period of the three writing periods is output to the signal line connected to the small pixel colored by the green color filter. Set control signal It is characterized in that to produce a.
[0011]
According to a second aspect of the present invention, in the first aspect, in the signal line selection circuit, three analog switches are arranged for one output from the signal line driving circuit IC, and a source electrode of each analog switch is the signal line. Commonly connected to one output line from the drive circuit IC, the gate electrode of each analog switch is connected to each supply line of the control signal, and the drain electrode of each analog switch is connected to the corresponding signal line. According to the control signal output from the control signal generation circuit, the source electrode and the drain electrode of each analog switch are made conductive to correspond to the video signal output to one output line of the signal line drive circuit IC. The writing is performed on the signal line.
[0012]
According to the above configuration, the order of writing the video signal to each pixel is the order of the R pixel, the B pixel, and the G pixel. Therefore, the variation of the pixel potential is the third due to the influence of the coupling. Are written in G pixels that are easily recognized. As described above, since the pixel potential fluctuation amount of the G pixel in which the display unevenness is easily recognized is minimized, the display unevenness is hardly recognized, and good display quality can be obtained as a whole screen.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a liquid crystal display device according to the present invention will be described with reference to the drawings.
[0014]
In the present embodiment, a liquid crystal panel conforming to the XGA (1024 × RGB × 768) standard is assumed. Here, a description will be given of a configuration in which each one output line extracted from the signal line driving IC is branched by three analog switches and connected to three signal lines, respectively.
[0015]
FIG. 2 is a circuit configuration diagram schematically showing the configuration of the liquid crystal display device according to the present embodiment.
[0016]
The pixel array unit 100 of the liquid crystal display device 1 includes an array substrate 200, a counter substrate (not shown) arranged at a predetermined interval from the array substrate 200, and a liquid crystal layer 300 held between these substrates. In addition, the array substrate 200 and an opposing substrate (not shown) are bonded to each other by a sealing material (not shown) disposed around the array substrate 200.
[0017]
In the array substrate 200, a plurality of scanning lines G1 to G768 (hereinafter, generically referred to as G) and a plurality of signal lines S1 to S3072 (hereinafter, generically referred to as S) are arranged so as to be orthogonal to each other. At each intersection of both lines, a pixel TFT 110 as a pixel transistor and a pixel electrode 120 to be a pixel (here, each sub-pixel of RGB) are provided. A plurality of pixel electrodes 120 arranged in a matrix on the array substrate 200 constitute a pixel portion 210.
[0018]
Each pixel is provided with an RGB color filter (not shown). In the following description, an R pixel is a pixel colored with an R (red) color filter, a G pixel is a pixel colored with a G (green) color filter, and a B pixel is a B (blue) color filter. Means a pixel colored with. The array of each color is repeatedly arranged in the order of RGB in each row, and pixels of the same color are arranged in each column. As described above, in the pixel unit 210, each pixel electrode 120 forms a small pixel (sub-pixel) as a drive unit, and the R, G, and B pixels colored by the RGB color filters are display units. Large pixels (pixels) having the same color arrangement are configured.
[0019]
The common electrode 130 disposed opposite to the pixel electrode 120 is formed on a counter substrate (not shown), and the liquid crystal layer 300 is disposed between the pixel electrode 120 and the common electrode 130 via an alignment film (not shown). Is held.
[0020]
The pixel TFT 110 is composed of, for example, a polycrystalline silicon TFT using a polycrystalline silicon film as a semiconductor layer. The gate electrode of the pixel TFT 110 is connected to the scanning line G, and the source electrode is connected to the signal line S. The drain electrode is connected to the pixel electrode 120 and the auxiliary capacitance element 140, respectively. The pixel TFT 110 is turned on by the scanning signal supplied to the scanning line G, and the source / drain electrode is conducted, so that the video signal written to the signal line S is applied from the source electrode to the pixel electrode 120 through the drain electrode. You.
[0021]
The scanning line driving circuit 150 is a circuit that supplies a scanning signal to the scanning lines G1 to G768, and is integrally formed on the array substrate 200 by the same manufacturing process as the pixel TFT 110. The scanning line driving circuit 150 is disposed on the left side and the right side of the pixel portion 210.
[0022]
The signal line drive circuit section 160 is a circuit that supplies a video signal while determining the positive and negative polarities of the signal lines S1 to S3072, and outputs a video signal corresponding to each signal line to three signal lines S1 to S3072. Signal line driving ICs (TAB-ICs) 410-1, 410-2, 410-3 (hereinafter collectively referred to as 410-N), which are serially output for each signal line group when divided into groups; The video signal output from the line drive IC 410 is divided into three times within one horizontal scanning period, and is switched to a predetermined signal line of each signal line group and output by switching.
[0023]
In the TCPs 400-1 to 400-3 (hereinafter collectively referred to as 400-N) of the signal line drive circuit section 160, one side in the longitudinal direction is connected to the array substrate 200 side, and the other side is connected to the external drive circuit 500 side. The signal line driving IC 410-N mounted on the TCP 400-N includes a D / A converter (not shown), converts a digital video signal input from a control IC 600 described later into an analog video signal, and Output to the selection circuit 170.
[0024]
The signal line driving IC 410-N includes 342 output terminals (OUT). That is, in the signal line driving IC 410-1, 342 output terminals are respectively connected to three signal lines via an analog switch described later, and supply the video signals R1 to B342 to the signal lines S1 to S1026. ing. Similarly, the signal line driving IC 410-2 supplies video signals R343 to B684 to the signal lines S1027 to S2052, and the signal line driving IC 410-3 supplies video signals R685 to B1024 to the signal lines S2053 to S3072. However, in the signal line driving IC 410-3, 340 output terminals are used, and the remaining two terminals are used as surplus terminals.
[0025]
In the present embodiment, the signal lines S1 to S3072 are divided into three signal line groups in the order of selection, and the signal lines S1, S4, S7,... S3070, the signal lines S2, S5, S8,. , S6, S9,... S3072.
[0026]
The above-mentioned division is a division of signal lines simultaneously selected within one horizontal scanning period. In FIG. 2, signal lines S1 to S3072 divided into three signal line groups are connected to respective signal line driving ICs. Is shown. At the time of driving, for example, signal lines S1, S4, S7, ..., signal lines S2, S5, S8, ..., signal lines S3, S6, S9, ... in three writing periods set within one horizontal scanning period. Video signals are written for each signal line in order. At this time, in the signal line driving IC 410-N, the polarity of the video signal is determined so that the video signal whose sign is inverted is written to the adjacent signal line within one horizontal scanning period because of the H / V inversion drive, and The polarity of the video signal written to the same signal line is switched every one horizontal scanning period.
[0027]
The signal line driving IC 410 is mounted on a flexible wiring substrate, and is electrically connected to the external driving circuit 500 and the array substrate 200, respectively. The signal line selection circuit 170 is provided on the array substrate 200.
[0028]
The external drive circuit 500 includes a control IC 600 as a control circuit that generates an analog switch control signal or the like that controls the order in which the video signal is switched to the corresponding signal line and output by the signal line selection circuit 170, and not shown. A power supply circuit and the like are mounted.
[0029]
The control IC 600 rearranges and outputs digital video signals input from the outside according to the output order to each signal line, and generates various control signals based on a reference clock signal input in synchronization with the digital video signals. That is, the control IC 600 supplies a start pulse and a clock signal to the scanning line driving circuit 150, and rearranges digital video signals, register control signals, clock signals, load signals, and the like to the signal line driving ICs 410-1 to 410-3. Supply. The signal line selection circuit 170 also supplies analog switch control signals ASW1U, ASW2U, and ASW3U. Further, the control IC 600 controls the analog signal so that the video signal output in the third writing period of the three writing periods provided in one horizontal scanning period is output to the signal line S connected to the G pixel. The output order of the switch control signals ASW1U, ASW2U, and ASW3U is controlled.
[0030]
FIG. 1 is a circuit configuration diagram showing a schematic configuration of the signal line driving circuit section 160. FIG. 1A is a circuit configuration diagram of a basic block included in the signal line selection circuit 170. Here, the basic block arranged at the left end of (B) is shown as a representative. FIG. 1B is a circuit diagram showing the configuration of the signal line driving IC 410-N and the signal line selection circuit 170.
[0031]
As shown in FIG. 1B, the signal line selection circuit 170 includes a plurality of basic blocks 180, and 171 basic blocks 180 are connected to each of the signal line driving ICs 410-N. 170 in the signal line driving IC 410-3). Two output terminals OUT are connected to one basic block 180 from each signal line driving IC 410-N.
[0032]
As shown in FIG. 1A, one basic block 180 includes analog switches SW1, SW2,..., SW6 (hereinafter collectively referred to as SW) each configured by a Pch TFT. Of these, the source electrodes of the analog switches SW1, SW2, and SW3 are commonly connected to the output terminal (output line) OUT1 of the signal line driving IC 410-1, and the source electrodes of the analog switches SW4, SW5, and SW6 are used for signal line driving. The common terminal is connected to the output terminal OUT2 of the IC 410-1. The drain electrodes of the analog switches SW1, SW2, and SW3 are connected to the signal lines S1, S2, and S3, and the drain electrodes of the analog switches SW4, SW5, and SW6 are connected to the signal lines S4, S5, and S6. Therefore, one basic block 180 drives six signal lines in a time-division manner. On the other hand, the gate electrodes of the analog switches SW1 and SW4 are commonly connected to an analog switch control signal line (supply line) ASW1, and the gate electrodes of the analog switches SW2 and SW5 are commonly connected to an analog switch control signal line ASW2. The gate electrodes of the analog switches SW3 and SW6 are commonly connected to an analog switch control signal line ASW3.
[0033]
Since the analog switch SW is formed of a Pch TFT, when the analog switch control signal ASW1U has a low potential, the analog switches SW1, SW4, SW7,... SW3070 are turned on, and the signal lines S1, S4, S7,. When the video signal is written in S3070 and the analog switch control signal ASW2U has a low potential, the analog switches SW2, SW5, SW8,... SW3071 are turned on, and the signal lines S2, S5, S8,. When the video signal is written and the analog switch control signal ASW3U has the Low potential, the analog switches SW3, SW6, SW9,..., SW3072 are turned on, and the video is sent to the signal lines S3, S6, S9,. The signal is written.
[0034]
The signal lines S1, S4, S7,... S3070 are connected to columns R1, R2,... Where R (red) video signals are written, and the signal lines S2, S5, S8,. Are connected to the columns G1, G2,... To which the video signals are written, and the signal lines S3, S6, S9,... S3072 are connected to the columns B1, B2,. . Therefore, video signals corresponding to the R pixels in each row are written from the signal lines S1, S4, S7,... S3070, and video signals corresponding to the G pixels in each row are written from the signal lines S2, S5, S8,. , And video signals corresponding to the B pixels in each row are written from the signal lines S3, S6, S9,... S3072.
[0035]
Next, the operation of the liquid crystal display device 1 configured as described above when writing a video signal to each signal line S will be described.
[0036]
FIG. 3 is a timing chart of analog switch control signals ASW1U, ASW2U, and ASW3U output from the control IC 600.
[0037]
As shown in the figure, three writing periods are provided in one horizontal scanning period (1H), and video signals corresponding to R, G, and B are sequentially written for each row. In FIG. 1, the 3n-2th row, the 3n-1th row, and the 3nth row show three consecutive rows. In the present embodiment, the analog switch control signal applied to each row is controlled so as to have a low potential in the order of ASW3U, ASW1U, and ASW2U. Therefore, the video signal is written to the B pixel in the first writing in the one horizontal scanning period, the R pixel in the second writing, and the G pixel in the third writing. Similarly, the video signals are written in the other basic blocks 180 in the order of the analog switch control signals ASW3U, ASW1U, and ASW2U.
[0038]
Here, the H / V inversion drive will be briefly described with reference to FIG. FIG. 1 shows the polarities of pixels divided into 6 rows and 6 columns for each frame. In addition, it is assumed that writing is performed on the pixels in 6 rows and 6 columns illustrated in FIG. 4 by one basic block illustrated in FIG.
[0039]
In the n-th frame, the polarities of the video signals supplied from the output terminal OUT1 to the R, G, and B columns are driven so that positive and negative are inverted in adjacent signal lines. The polarity of the supplied video signal is driven so that the polarity of the output terminal OUT1 is inverted from that of the output terminal OUT1. In the (n + 1) th frame, the polarity of the video signal supplied to the R, G, and B columns is opposite to that of the nth frame, and the polarity of the video signal written to the same signal line is switched every one horizontal scanning period. The writing order of the video signal in each frame is the order of R pixels, B pixels, and G pixels in each row.
[0040]
When the above-described H / V inversion drive is performed, the pixel potential fluctuates due to the influence of the coupling between the own pixel-own signal line, the own pixel-adjacent signal line, and the own signal line-adjacent signal line. In the present embodiment, the order of writing the video signal to each pixel is the order of the R pixel, the B pixel, and the G pixel in the horizontal direction. Pixels to be written are G pixels in which display unevenness is easily recognized. As described above, since the pixel potential fluctuation amount of the G pixel in which the display unevenness is easily recognized is minimized, the display unevenness is hardly recognized, and good display quality can be obtained as a whole screen.
[0041]
In the above embodiment, the order of writing the video signal to each pixel is set to the order of the R pixel, the B pixel, and the G pixel in the horizontal direction. , B pixels may be interchanged.
[0042]
【The invention's effect】
As described above, according to the liquid crystal display device of the present invention, since the pixel potential fluctuation amount of the G pixel in which display unevenness is easily recognized can be reduced, one output of the driving IC is built in the array. Even in a configuration in which three writing switches are provided in one horizontal scanning period by connecting to three analog switches in the signal line driving circuit, the influence of display unevenness is reduced and good display quality is obtained. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram illustrating a schematic configuration of a signal line driving circuit unit. 4A is a circuit configuration diagram of a basic block included in a signal line selection circuit. 3B is a circuit configuration diagram illustrating a configuration of a signal line driving IC and a signal line selection circuit.
FIG. 2 is a circuit diagram schematically illustrating a configuration of a liquid crystal display device according to an embodiment.
FIG. 3 is a timing chart of analog switch control signals ASW1U, ASW2U, and ASW3U output from a control IC.
FIG. 4 is an explanatory diagram showing polarities of pixels divided into 6 rows and 6 columns for each frame.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 100 ... Pixel array part 110 ... TFT
120 pixel electrode 130 common electrode 140 auxiliary capacitance element 150 scanning line driving circuit 160 signal line driving circuit 170 signal line selecting circuit 180 basic block 200 array substrate 210 pixel unit 300 liquid crystal layer 400 TCP
410 ... signal line driving IC
500: external drive circuit 600: control IC

Claims (2)

A plurality of signal lines and a plurality of scanning lines which are wired to cross each other, a plurality of pixel transistors disposed at each intersection of the two lines, a plurality of pixel electrodes connected to each of the pixel transistors, and each of the pixels A liquid crystal panel having red, green, and blue color filters arranged for each electrode, a scanning line driving circuit for supplying a scanning signal to each of the scanning lines, and a plurality of signal lines connected to N (N: 3 or more) N) signal line driving ICs that serially output video signals for each signal line group when divided into (integer) signal line groups, and one horizontal scan of the video signal output from the signal line driving IC. N signal line selection circuits for switching to and outputting the corresponding signal lines of each signal line group in three times during a period, and switching the video signal to a predetermined signal line for output by the signal line selection circuit Control signal that defines the output order when A liquid crystal display device and a control signal generating circuit,
In the liquid crystal panel, one pixel electrode constitutes a small pixel, and large pixels of the same color arrangement composed of three small pixels colored by the red, green, and blue color filters are arranged in a matrix,
The signal line driving IC outputs, to one adjacent signal line, a video signal whose polarity is inverted in one horizontal scanning period, and outputs a video signal output to the same signal line every one horizontal scanning period. Switch,
The control signal generation circuit connects a video signal output in a third writing period of the three writing periods provided in one horizontal scanning period to a small pixel colored by the green color filter. Generating a control signal that determines the output order of the video signal so as to be output to a signal line;
A liquid crystal display device characterized by the above-mentioned. In the signal line selection circuit, three analog switches are arranged for one output from the signal line drive circuit IC, and a source electrode of each analog switch is commonly connected to one output line from the signal line drive circuit IC. The gate electrode of each analog switch is connected to each supply line of the control signal, and the drain electrode of each analog switch is connected to the corresponding signal line, respectively, and the control signal output from the control signal generation circuit is provided. A signal is applied between the source electrode and the drain electrode of each analog switch to write a video signal output to one output line of the signal line drive circuit IC to the corresponding signal line. 2. The liquid crystal display device according to 1.

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