JP4302816B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device, and more particularly to a large, high-definition liquid crystal display device that drives each signal line by V line inversion driving.
[0002]
[Prior art]
A polysilicon TFT (Thin Film Transistor) liquid crystal display (hereinafter referred to as p-Si TFT LCD) has higher TFT mobility than an amorphous silicon TFT liquid crystal display (hereinafter referred to as a-Si TFT LCD). In addition, a driving circuit of a liquid crystal display device can be formed over a glass substrate, and the size of a TFT in a pixel portion can be reduced, which is suitable for high definition. For this reason, it has recently been used as a display unit for mobile computers.
[0003]
In a-Si TFT LCD, each signal line is driven in the same timing during one horizontal scanning period. In p-Si TFT LCD, each signal line is (one horizontal scanning period / signal line). A dot sequential driving is used in which the driving is performed in order of time. However, in general, high definition, that is, a large number of pixels shortens the writing time per signal line. Therefore, block sequential driving in which video signals are simultaneously written to a plurality of signal lines is used.
[0004]
This block sequential drive will be described. First, the scanning line driving circuit sets the first scanning line to the H (high) level, and the pixel TFTs commonly connected to the first scanning line are turned on. Next, a video signal corresponding to each signal line of 1 to a (a is a natural number of 2 or more) columns is supplied to the pixel electrode through each signal line by the signal line driving circuit. At this time, the video signal is supplied so that the polarity is different from the common common potential Vcom. For each adjacent signal line (V line inversion drive). In the next selection period, video signals are written to the pixel electrodes via the signal lines such as a + 1 to 2a columns, and in the next selection period, 2a + 1 to 3a columns.
[0005]
A potential difference between the pixel electrode potential and the counter electrode potential is applied to the liquid crystal layer, and an image is displayed by light modulation. This operation is repeated until the last row is reached. When video signal writing is completed up to the signal line of the last column, the scanning line in the first row is set to L (low) level, and all the pixel TFTs commonly connected to the scanning line in the first row are turned off. Next, the scanning line in the second row is set to the H level, and the video signal is written in the same manner as the pixel electrode in the first row described above. This is performed until the last line, and the display for one screen (one frame) is completed.
[0006]
Here, it is considered to display a pixel checkered pattern, particularly a halftone-black pixel checkered pattern. When the voltage amplitude is 4 V and the counter electrode potential is 5 V, the signal line potential at the time of writing in the (n−1) th row, the nth row, and the n + 1th row is as shown in FIG.
[0007]
FIG. 7 shows an example having R, G, and B color filters. The total of R (Red) signal lines, G (Green) signal lines, and B (Blue) signal lines is shown in FIG. Three signal lines are alternately arranged adjacent to each other, and display of each pixel is performed by these three signal lines.
[0008]
Hereinafter, the R signal line is referred to as a Red line, the G signal line is referred to as a Green line, and the B signal line is referred to as a Blue line. In FIG. 7, the Red line, Green line, and Blue line in the first column are R1, G1, and B1, respectively.
[0009]
As shown in the figure, for the pixel checkered display, the signal line potentials of the Red line and the B1ue line fluctuate by the same potential width in the same direction as 9V → 7V → 9V or 3V → 1V → 3V. At this time, the potential of the Green line varies in the opposite direction from 1V → 3V → 1V or 7V → 9V → 7V.
[0010]
[Problems to be solved by the invention]
However, when the signal line potential fluctuates, coupling occurs between the signal line and the Cs line, whereby the Cs line potential is swung in the same direction as the Red line and the Blue line. At this time, the signal line potential of the block in which the video signal has already been written fluctuates according to the fluctuation of the Cs line potential. At this time, the deviation of the signal line potential of the block in which the video signal has already been written is shifted in the direction approaching the common electrode potential in the Red line and the Blue line, that is, in the direction in which the display image is whitened. The potential shifts in the direction away from the electrode potential, that is, in the direction in which the display image becomes dark.
[0011]
FIG. 8 is a potential diagram for explaining the deviation of the signal line potential due to such variation of the Cs line potential. As shown in the figure, the first block is affected by the video signal writing from the second block to the last block (32 block in the example shown in FIG. 8). The second block is affected from the third block to the last block. For this reason, it can be seen that the error voltage from the predetermined potential is larger toward the first stage side.
[0012]
Therefore, at the halftone level, even a slight potential deviation is visually recognized as a display, and the closer to the first stage side, the more magenta is obtained. Conversely, the closer to the final stage side, the greener the pixel potential of the previous frame is due to a voltage error due to the influence of the Cs line potential fluctuation.
[0013]
Thus, since the pixel checkered display screen is a specific display pattern, according to the conventional p-Si TFT LCD and its driving method, when a video signal is written to the signal line, the Cs line potential is generated by the signal line-Cs coupling. As a result, the signal line potential of the pixel for which writing has already been completed fluctuates and a potential different from the desired potential is written to the pixel. There is a problem in that a display defect occurs in which the side is colored magenta and the last side is colored green.
[0014]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a liquid crystal display device capable of obtaining uniform and good image quality over the entire surface.
[0015]
[Means for Solving the Problems]
The present invention aims to solve the above problems by the following means.
[0016]
That is, the liquid crystal display device according to the present invention is formed in the vicinity of each intersection of the signal lines and the scanning lines, the signal lines and the scanning lines arranged in a matrix , each drain is connected to the signal line, A plurality of pixel display transistors whose sources are connected to the scanning line, a Cs line arranged in parallel to the scanning line, and a lattice-shaped window formed by the signal line and the Cs line in response to arranged, and a pixel electrode each are connected to the signal lines constituting the sub-pixels through the pixel display transistors, an array substrate having the array substrate and opposed to each other via the liquid crystal A counter substrate having a counter electrode formed on an inner main surface thereof, and a color filter layer of three colors periodically arranged corresponding to the column of sub-pixels, and a polarity with respect to a common potential applied to the counter electrode Is adjacent Driving voltage alternately reversed for each serial signal line, the liquid crystal display device applied to sequentially said signal lines in each block consisting of a plurality of said signal lines disposed adjacent, out of the color filter layers of three colors , wherein the most low layer of visibility, and arranged corresponding to the center sub-pixel of the sub-pixels constituting one pixel.
[0017]
According to the liquid crystal display device according to the present invention, among the three color filter layers, the layer having the lowest visibility is arranged corresponding to the central sub-pixel among the sub-pixels constituting one pixel, Color unevenness in the halftone-black pixel checkered display can be reduced.
[0018]
Since the driving voltage for each block consisting of a plurality of the signal lines disposed adjacent can shorten the write time per signal line by being sequentially applied, it is possible to increase the number of pixels, further high definition Can be displayed.
[0019]
Moreover, it is preferable that the signal line driving circuit for applying the driving voltage to the signal line is integrally formed on the array substrate. Thereby, a liquid crystal display device with high reliability and lower cost can be provided.
[0020]
The color filter layer may be formed on either the array substrate or the counter substrate.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, some embodiments of the present invention will be described with reference to the drawings.
[0022]
First, a first embodiment of a liquid crystal display device according to the present invention will be described.
[0023]
FIG. 1 is a circuit diagram illustrating a schematic configuration of a liquid crystal display device 30 integrated with a drive circuit according to the present embodiment. FIG. 2 is a schematic pattern diagram illustrating a pixel portion of the liquid crystal display device 30 illustrated in FIG. FIG. 3 is a diagram in which the alignment film is omitted from the AA ′ cross-sectional view of the array substrate 10 specifically formed based on the pattern diagram of FIG. 2.
[0024]
As shown in FIG. 1, the liquid crystal display device 30 of this embodiment has a structure formed by disposing an array substrate 10 and a counter substrate so as to face each other through liquid crystal. Pixel electrodes 105 are arranged in a matrix on the array substrate 10, and color filter layers 312 a to 312 c made of organic insulating layers that transmit R, B, and G light are arranged in the column direction on each pixel electrode 105. Each pixel electrode constitutes a sub-pixel. Then, one pixel is constituted by three RBG subpixels in order from the end column (see FIG. 3). As described above, the feature of this embodiment is that the color arrangement in the color filter layer is not the conventional arrangement of R, G, B, but B, which is the color with the lowest visibility, is arranged in the center.
[0025]
Each pixel electrode 105 is connected to the auxiliary capacitor 106 and the source electrode of the pixel TFT 104, and a counter electrode 107 (not shown) is provided on the counter substrate corresponding to the pixel electrode 105. The liquid crystal capacitor _CLC is formed by disposing the pixel electrode 105 of the array substrate 10 and the counter electrode 107 on the counter substrate so as to face each other through the liquid crystal, and the auxiliary capacitor 106 includes the semiconductor layer of the pixel TFT 104 and the Cs electrode. 103 is arranged so as to face each other.
[0026]
The scanning lines 102 are connected in common to the gate electrodes of the pixel TFTs 104 arranged in the row direction, and a scanning signal is supplied by a scanning line driving circuit 108 formed integrally on the array substrate 10. In addition, a red line 101a, a blue line 101b, and a green line 101c are commonly connected to the drain electrode of the pixel TFT 104 in the column direction corresponding to each color filter layer, and are integrally formed on the same substrate as the array substrate 10. The image signal is supplied from the signal line driving circuit 109 that has been processed.
[0027]
As shown in the pattern diagram of FIG. 2, the array substrate 10 is provided with red lines 201a, blue lines 201b, and green lines 201c in the column direction, and scanning lines 202 are arranged in the row direction orthogonal to these signal lines. The Cs wiring 203 is disposed in parallel with the scanning line 202. A pixel TFT 204, which is a pixel display switching element, is formed in the vicinity of the intersection with the signal lines 201a to 201c, its gate electrode 204G is connected in common to the scanning line 202, and its drain electrode. 204D is connected to each of signal lines 201a to 201c, and its source electrode 204S is connected to a Cs electrode 207 having a substantially T-shaped planar shape. Further, in the interlayer insulating film 310 (see FIG. 3), a portion sandwiched between the Cs wiring 203 and the Cs electrode 207 forms an auxiliary capacitor 206.
[0028]
The pixel electrodes 205a to 205c are arranged substantially corresponding to the lattice-shaped window formed by the signal lines 201a to 201c and the Cs wiring 203, and one pixel is formed by these three pixel electrodes adjacent in the row direction. Is done.
[0029]
As shown in the schematic cross-sectional view of FIG. 3, in the liquid crystal display device 30 of the present embodiment, color filter layers 312a to 312c made of organic insulating layers are formed on the array substrate 10, and Red 312a, B1ue 312b, and Green 312c are formed from the left side of the drawing. The B1ue color filter layer 312b having the lowest visibility among the three color filter layers is formed so as to be positioned corresponding to the central sub-pixel among the sub-pixels constituting one pixel.
[0030]
Next, a case where the liquid crystal display device 30 of the present embodiment performs halftone-black pixel checkered display will be described. The writing of the video signal to each pixel is performed by the block sequential driving method by the V line inversion driving similar to the above-described prior art.
[0031]
As in the conventional technique described above, when the voltage amplitude is 4V and the counter electrode potential is 5V, the signal line potentials at the time of writing in the (n−1) th row, the nth row, and the n + 1th row are the Red line and the Blue line. , Assuming that the first column of the Green line is R1, B1, and G1, the result is as shown in FIG.
[0032]
As shown in the figure, for the pixel checkered display, the signal line potentials of the Red line and the Green line are changed by 9 V → 7 V → 9 V or 3 V → 1 V → 3 V by the same potential width in the same direction. At this time, the potential of the Blue line varies in the opposite direction from 1V → 3V → 1V or 7V → 9V → 7V, and the Red line and the Green line.
[0033]
When the signal line potential fluctuates, coupling occurs between the signal line and the Cs line, whereby the Cs line potential is swung in the same direction as the Red line and the Green line. At this time, the signal line potential of the block in which the video signal has already been written fluctuates according to the fluctuation of the Cs line potential. At this time, the deviation of the signal line potential of the block in which the writing of the video signal has already been completed is shifted in the direction approaching the common electrode, that is, the direction in which the display image is whitened in the Red line and the Green line. On the other hand, in the B1ue signal line located at the center, the potential shifts in the direction away from the common electrode potential, that is, in the direction in which the display image becomes dark.
[0034]
FIG. 5 is a time chart for explaining the shift of the signal line potential due to the fluctuation of the Cs line potential in the liquid crystal display device 30 shown in FIG.
[0035]
As shown in the figure, the first block is affected by writing from the second block to the final block, and the second block is from the third block to the final block. Influenced by block of steps. For this reason, the deviation (ERROR) voltage from the predetermined potential is larger toward the first stage side.
[0036]
At the halftone level, a slight potential shift is visually recognized as a display, so the closer to the first stage side from the last stage side, the more yellow the color that is complementary to Blue. On the other hand, the closer to the final stage side, the more the pixel potential of the previous frame becomes blue due to the voltage error caused by the Cs line potential fluctuation.
[0037]
As described above, according to the liquid crystal display device of the present embodiment, among the three color filter layers, the blue color filter layer having the lowest visibility corresponds to the central sub-pixel among the sub-pixels constituting one pixel. By arranging in this manner, the influence on the visibility can be reduced, so that the influence of the uneven coloring generated on the first stage side and the final stage side on the visual feeling can be reduced.
[0038]
Next, a second embodiment of the liquid crystal display device according to the present invention will be described. This embodiment is different from the liquid crystal display device 30 described above in that the color filter is formed not on the array substrate side but on the counter substrate side. The other points are substantially the same as those of the liquid crystal display device 30, and the circuit diagrams and the schematic pattern diagrams thereof are the same as those of FIGS. This will be described using a cross-sectional view corresponding to the line.
[0039]
FIG. 6 is a cross-sectional view showing a pixel portion of the liquid crystal display device 40 of the present embodiment. In the figure, the same parts as those in FIG. 3 are denoted by the same reference numerals and the description thereof is omitted. As apparent from comparison with FIG. 3, the difference between the array substrate 20 shown in FIG. 6 and the array substrate 10 shown in FIG. 3 is formed between the pixel electrodes 305a to 305c and the protective film 311. The organic insulating layer 406 is colorless and does not constitute a color filter. In the liquid crystal display device 40 of the present embodiment, a color filter layer is provided on the counter substrate 416 side, and a red color filter 412a, a blue color filter 412b, and a green color filter 412c are arranged in this order from the left side of the paper, and a B1ue color filter. The layers are arranged so as to be in the center of the three-color arrangement.
[0040]
Since the operation in the halftone-black pixel checkerboard display of the liquid crystal display device 40 of this embodiment is the same as the operation of the liquid crystal display device 30 described above, detailed description thereof is omitted.
[0041]
Also in the liquid crystal display device of the present embodiment, the blue color filter layer having the lowest visibility among the three color filter layers is arranged corresponding to the central sub-pixel among the sub-pixels constituting one pixel. Therefore, it is possible to reduce the influence that the shift of the signal line potential caused by the fluctuation of the Cs line potential has on the user's visual perception. Thereby, it is possible to reduce the influence of uneven coloring that occurs in the first-stage block and the final-stage block.
[0042]
【The invention's effect】
As described above in detail, the present invention has the following effects.
[0043]
That is, according to the present invention, the three-color color filter layer periodically arranged corresponding to the sub-pixel columns of the liquid crystal display device driven based on the block sequential driving by the V line inversion driving has the highest visibility. Since the lower layer is arranged corresponding to the central sub-pixel among the sub-pixels constituting one pixel, the color generated in the first-stage block and the final-stage block due to the shift of the signal line potential caused by the Cs line potential fluctuation. The influence of Kimura can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a schematic configuration of a first embodiment of a drive circuit integrated liquid crystal display device according to the present invention;
2 is a schematic pattern diagram showing a pixel portion of the array substrate shown in FIG. 1. FIG.
FIG. 3 is a schematic cross-sectional view taken along the line AA ′ of the array substrate specifically formed based on the pattern diagram of FIG. 2;
4 is a potential diagram showing an example of a signal line potential in the liquid crystal display device shown in FIG. 1. FIG.
5 is a time chart for explaining a shift in signal line potential due to a change in Cs line potential in the liquid crystal display device shown in FIG.
FIG. 6 is a schematic cross-sectional view showing a second embodiment of the liquid crystal display device according to the present invention. FIG. 7 is a potential diagram showing an example of a signal line potential in the liquid crystal display device according to the prior art.
FIG. 8 is a time chart for explaining a shift in signal line potential due to a change in Cs line potential in a liquid crystal display device according to a conventional technique.
[Explanation of symbols]
10 Array substrates 30, 40 Liquid crystal display devices 101a, 201a, 301a Red line signal lines 101b, 201b, 301b B1ue line signal lines 101c, 201c, 301c Green line signal lines 102, 202, 302 Scan lines 103, 203 Cs wiring 104, 204,304 pixel TFT
105, 205a to 205c, 305a to 305c Pixel electrodes 106, 206 Auxiliary capacitors 107, 415 Counter electrode 108 Scan line drive circuit 109 Signal line drive circuit 308 Substrate 309 Gate insulation layer 310 Interlayer insulation layer 311 Passivation layer 312a Organic insulation layer (Red) )
312b Organic insulating layer (B1ue)
312c Organic insulation layer (Green)
406 Organic insulation layer (colorless)
412a Color filter layer (Red)
412b Color filter layer (Blue)
412c Color filter layer (Green)
413 Black matrix 414 Overcoat layer 416 Counter substrate

Claims (5)

Signal lines and scanning lines arranged in a matrix;
A plurality of pixel display transistors formed near the intersections of the signal line and the scanning line , each drain connected to the signal line, and each source connected to the scanning line ;
A Cs line arranged in parallel with the scanning line;
The signal lines and the Cs lines are arranged so as to substantially correspond to the lattice-shaped window portions, and are connected to the signal lines via the pixel display transistors, and each constitutes a sub-pixel. An array substrate having a pixel electrode;
A counter substrate disposed opposite to the array substrate via liquid crystal and having a counter electrode formed on the inner main surface;
A color filter layer of three colors periodically arranged corresponding to the column of sub-pixels,
A drive voltage in which the polarity with respect to the common potential applied to the counter electrode is alternately inverted for each adjacent signal line is sequentially applied to the signal line for each block including a plurality of adjacent signal lines. In liquid crystal display devices,
Among the color filter layers of three colors, most low layer of visibility, a liquid crystal display device, characterized in that arranged in correspondence with the center of the sub-pixel of the sub-pixels constituting one pixel. 2. The liquid crystal display device according to claim 1 , wherein a signal line driving circuit for applying the driving voltage to the signal lines is integrally formed on the array substrate . 3. The liquid crystal display device according to claim 1, wherein a scanning line driving circuit for supplying a scanning signal to the scanning lines is integrally formed on the array substrate . The color filter layer, the liquid crystal display device according to any one of claims 1 to 3, characterized in that formed on the array substrate. The color filter layer, the liquid crystal display device according to any one of claims 1 to 3, characterized in that formed on the counter substrate.

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