JP4407464B2 - Electro-optical device and electronic apparatus - Google Patents

Description

The present invention relates to an electro-optical device and an electronic apparatus, and more particularly to a device structure suitable for application to an active matrix electro-optical device.

In general, in an active matrix electro-optical device, a non-linear element is provided for each pixel, and a data line for supplying a predetermined potential is connected to each non-linear element. A data potential for realizing a predetermined gradation state is supplied to each pixel according to display data from a driver circuit that operates in accordance with a control signal. In addition, a scanning line for selecting a pixel row and a scanning line driving circuit for driving the scanning line are provided, and each of the pixels is configured corresponding to an intersection of the scanning line and the data line. The data line supplies the data potential to the plurality of pixels belonging to the pixel row selected by the scanning line via the nonlinear element.

In general, the data lines are connected to a plurality of output lines provided in the driver circuit in a one-to-one relationship, and the output of the driver circuit is supplied to the corresponding data line as it is. However, in this case, when the electro-optical device is highly refined and the pixel density is increased, the data line formation pitch is reduced, so that it is necessary to reduce the output line formation pitch of the driver circuit. For this reason, when the driver circuit is composed of an IC, it becomes difficult to mount the IC due to the miniaturization of the formation pitch of the output pins of the IC, or the increase in the number of output pins corresponding to the increase in the number of pixels of the electro-optical device causes the IC to There is a problem of increasing the size.

Thus, as a method for reducing the number of output pins of the driver IC and ensuring the pitch between the output pins, a liquid crystal display device using a so-called time-division driving method has been proposed. In this time-division driving method, a plurality of data lines are set as one set, and one output line is provided in the driver circuit for each set of data lines, and the driver circuit applies the above set of data to each output line. It is configured to output a plurality of data potentials applied to the line in time series, and a time division switch is provided between the output line and a plurality of data lines in one set. In this driving method, the output is time-divided and the data potential is sequentially distributed to a plurality of data lines in one set.

In the electro-optical device as described above, since the data potential is distributed from one output line to a plurality of data lines, switching between the data lines becomes necessary and the writing time to the data lines is shortened. For this reason, the instability of the data potential is likely to be caused, so that proposals for ensuring the stability of the data potential have been made conventionally.

For example, in a liquid crystal display device, in a data line driving system including a sample hold circuit for holding a data potential in order to prevent crosstalk caused by inputting signals having different phases and amplitudes between data lines, It has been proposed to provide shield wiring for a selection signal line, an output line, a data line, and the like (for example, see Patent Document 1 below).

In order to reduce overshoot and undershoot of the data potential during time-division driving, it has also been proposed to connect a load capacitor to the output line or the data line (see, for example, Patent Document 2 below).
Japanese Patent Laid-Open No. 06-11684 (in particular, FIGS. 1 and 2 and explanations thereof) JP-A-11-249620 (in particular, FIGS. 1 and 4 and explanations thereof)

However, in the liquid crystal display device having the above-described shield wiring, the parasitic capacitance between adjacent wirings can be reduced by providing the shield wiring along each wiring, and crosstalk and the like can be prevented. Since the capacitance between the signal line and the shield line of the output line (input bus line) increases, the selection signal waveform for performing the time-division driving is lost, and particularly, a high level such as compatible with a full standard HDTV. A fine liquid crystal display device having a high driving frequency has a problem in that the accuracy of writing a data potential to a data line is affected. Further, providing shield wirings for the selection signal line, the output line, and the data line respectively complicates the wiring structure, and there is a problem that it is difficult to achieve high definition display for structural reasons.

On the other hand, in the liquid crystal display device having the load capacitance described above, the output potential and the data potential can be stabilized by connecting the load capacitance to the output line and the data line. In order to reduce this effect, it is necessary to increase the load capacity.However, in the time-series output mode by the time-division driving method and the short writing time to the data line, the load capacity Is increased, the accuracy of the data potential cannot be ensured due to the increased charging time.

Therefore, the present invention solves the above-described problems, and the problem is that the complexity of the wiring structure can be suppressed while maintaining the writing accuracy of data potential by time-division driving and the stability against noise. It is to realize a novel electro-optical device and electronic apparatus.

An electro-optical device according to an embodiment of the invention includes a plurality of pixels, a first data line provided corresponding to each of the plurality of pixels, and a second data line adjacent to the first data line. Including a plurality of data lines, a data output circuit that outputs a plurality of data potentials defining gradations of the plurality of pixels to the output line in time series, and the plurality of data potentials of the output lines that are output A time division circuit that time-divisionally writes the data lines in time series, and an electro-optical device that electrically controls an optical state of the plurality of pixels, the reference potential supplying a predetermined potential A first connection electrode electrically connected to the first data line, a second data line, and a second data line. A second connection electrode electrically connected to the cross section; And between the first data line and the first connection electrode and between the second data line and the second connection electrode, and the first data line, the second data line, The counter electrode disposed opposite to the first connection electrode and the second connection electrode, and disposed between the first data line and the second data line in plan view, and opposed to the reference potential line A shield line for conductively connecting an electrode; a first load capacitor configured between the counter electrode and the first connection electrode; and between the counter electrode and the first data line; the counter electrode; And a second load capacitor configured between the second connection electrode and between the counter electrode and the second data line.
The electro-optical device according to an embodiment of the invention is characterized in that the shield line is provided between the time division circuit and a driving region in which the plurality of pixels are arranged.
In the electro-optical device according to one embodiment of the invention, the first load capacitor and the second load capacitor are provided between the time division circuit and a drive region in which the plurality of pixels are arranged. It is characterized by being.
In the electro-optical device according to one embodiment of the invention, the time division circuit includes switching elements provided between the output line and the plurality of data lines corresponding to the output line,
The plurality of switching elements include an input-side electrode portion that is conductively connected to the output line, and an output-side electrode portion that is conductively connected to the data line, and the plurality of switching elements include a first switching element and A second switching element adjacent to the first switching element, and a third switching element adjacent to the second switching element, and the input side electrode portions of the first switching element and the second switching element are The output side electrode portions of the second switching element and the third switching element are arranged adjacent to each other.
In addition, an electro-optical device according to an embodiment of the present invention includes a pixel electrode provided corresponding to the pixel, a nonlinear element conductively connected between the pixel electrode and the data line, and the nonlinear element And a scanning line connected to the control electrode, wherein the first load capacitor and the second load capacitor each have the same layer as the control electrode as one electrode, and the semiconductor layer of the nonlinear element, The same layer is used as the other electrode, and the same layer as the insulating film provided between the control electrode and the semiconductor layer is used as a dielectric.
The electro-optical device according to an embodiment of the invention further includes a storage capacitor provided in parallel with the pixel, and the first load capacitor and the second load capacitor are a plurality of the storage capacitors. Each element is formed by the same layer.
An electronic apparatus according to an embodiment of the invention includes the electro-optical device described above.
An electro-optical device according to an embodiment of the present invention includes a plurality of pixels, a plurality of data lines provided corresponding to each of the plurality of pixels, and a plurality of data potentials defining the gradation of the pixels. A data output circuit that outputs to the output line in time series; and a time division circuit that time-divides and writes the data potential of the output line to the plurality of data lines in time series. In an electro-optical device that electrically controls an optical state of a pixel, a shield line disposed at least in part between the plurality of data lines and conductively connected to a predetermined potential, the plurality of data lines, and the shield line, And a load capacity each configured between the two.

According to the present invention, the shield line arranged at least in part between the plurality of data lines can reduce the influence on the data potential based on the parasitic capacitance between the adjacent data lines, and each data line Since the data potential can be stabilized by the provided load capacitance, the stability of the data potential can be improved, and high controllability for the electro-optic effect can be ensured. Further, since the load capacitance is configured between the data line and the shield line, it is possible to suppress the complexity of the wiring structure and to easily cope with the high definition of the electro-optical device.

In the present invention, it is preferable that the shield line is provided between the time division circuit and a driving region in which the plurality of pixels are arranged. In order to obtain the shielding effect between the data lines, it is only necessary to arrange the shield lines between the data lines. However, if a shield line is provided in the time division circuit, it is caused by capacitive coupling between the time division circuit and the shield line. On the contrary, there is a risk that a problem may occur, and if a shield line is provided in the drive region, the wiring structure in the drive region may be complicated and the aperture ratio of the pixel may be reduced. Compared to these, the shield line provided between the time division circuit and the drive region has an effective shielding effect on the data line and does not have a structural and optical adverse effect on the drive region. In the present invention, the shield line only needs to be formed between the data lines between the time division circuit and the drive region, and the shield line is not formed in the time division circuit or the drive region. Not what you want.

In the present invention, it is preferable that the load capacitor is provided between the time division circuit and a driving region in which the plurality of pixels are arranged. In order to ensure the potential stability of the data line, it is only necessary to connect the load capacitance to the data line. However, if a shield line is provided in the time division circuit, the capacitive coupling between the time division circuit and the shield line is required. On the contrary, there is a risk of malfunction,
Further, if a load capacitor is provided in the drive region, the structure in the drive region becomes complicated and there is a risk that the aperture ratio of the pixel is lowered. Compared to these, the load capacitance provided between the time division circuit and the drive region has an effective potential stabilizing effect on the data line and does not have a structural and optical adverse effect on the drive region. In the present invention, since the load capacitance is connected between the data line and the shield line, it is most desirable that both the shield line and the load capacitance are formed between the time division circuit and the drive region.

In the present invention, the time division circuit includes a switching element provided between the output line and the plurality of data lines, and the plurality of switching elements are input-side electrode portions that are conductively connected to the output line. And an output side electrode portion that is conductively connected to the data line, and the plurality of switching elements are arranged in such a manner that the input side electrode portions and the output side electrode portions are adjacent to each other. It is preferable. According to this, since the plurality of switching elements are arranged in the time division circuit in such a manner that the input side electrode parts and the output side electrode parts are adjacent to each other, the input between the adjacent switching elements is performed. Since the capacitive coupling between the side electrode portion and the output side electrode portion is weak, fluctuations in the data potential based on the electrical influence between the switching elements can be suppressed.

In the present invention, a pixel electrode provided corresponding to the pixel, a non-linear element conductively connected between the pixel electrode and the data line, and a scanning line connected to a control electrode of the non-linear element The load capacitance is provided between the control electrode and the semiconductor layer, with the same layer as the control electrode as one electrode and the same layer as the semiconductor layer of the nonlinear element as the other electrode. It is preferable that the same layer as the insulating film to be formed is configured as a dielectric. According to this, it becomes possible to manufacture the electro-optical device without increasing the number of manufacturing steps.

In the present invention, it is preferable that a storage capacitor provided in parallel with the pixel is further provided, and the load capacitor is formed of the same layer as a plurality of elements constituting the storage capacitor. Also in this case, the electro-optical device can be manufactured without increasing the number of manufacturing steps.

The electro-optical device according to the invention is mounted on various electronic devices. Examples of such an electronic device include a mobile phone, a portable information terminal, an electronic timepiece, a television device, and a monitor device that use an electro-optical device as a display means. Further, it may be a projection display device using the above electro-optical device as light modulation means such as a liquid crystal light valve.

In each of the above inventions, the pixels are arranged in a matrix corresponding to the intersections of the data lines and scanning lines orthogonal to the data lines, and are written from the output lines to a plurality of data lines by the time division circuit. The data potential is preferably supplied to a pixel belonging to a row selected by the scanning line via a non-linear element (for example, a transistor such as a TFT (thin film transistor)).

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, a basic configuration example of the present embodiment will be described. In each drawing referred to below, each layer and each member have different scales so that each layer and each member can be recognized on the drawing. Different.

[Basic configuration example]
FIG. 1 is a block diagram illustrating a basic configuration example of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel in which a liquid crystal element is driven by a switching element such as a TFT (thin film transistor). This display unit 1 has m dots ×
N lines of pixels 2 are arranged in a matrix (two-dimensional plane). Further, the display unit 1 includes n scanning lines Y1 to Yn = Yj each extending in the row direction (X direction) and m lines each extending in the column direction (Y direction). Data lines X1 to Xm = Xk are provided, and the pixels 2 are arranged corresponding to these intersections. In the following description, when a certain pixel 2 in the display unit 1 is specified, the subscript k = 1 to m of the data line Xk and the subscript j = 1 to n of the scanning line Yj are used to correspond to these intersections. The pixel 2 to be expressed is expressed as (k, j). For example, the upper left pixel 2 is (1, 1), and the lower right pixel 2 is (m, n).

FIG. 2 is an equivalent circuit diagram of the pixel 2 using liquid crystal. One pixel 2 includes a TFT 21 which is a nonlinear element, a liquid crystal capacitor 22, and a storage capacitor (storage capacitor) 23. T
The source of FT21 is connected to one data line Xk, and its gate is connected to one scanning line Yj. Regarding the pixels 2 arranged in the same column, the sources of the respective TFTs 21 are connected to the same data line Xk. Further, regarding the pixels 2 arranged in the same row, each T
The gate of FT21 is connected to the same scanning line Yj. The drain of the TFT 21 is commonly connected to a liquid crystal capacitor 22 and a holding capacitor 23 provided in parallel. The liquid crystal capacitor 22 includes a pixel electrode 22a, a counter electrode 22b, and a liquid crystal layer sandwiched between these electrodes 22a and 22b. The storage capacitor 23 is formed between the pixel electrode 22 a and a common capacitor electrode (not shown), and the potential Vcs is supplied to a terminal opposite to the side connected to the TFT 21. The storage capacitor 23 suppresses the influence of leakage of charges accumulated in the liquid crystal.

On the other hand, a data potential V or the like is applied from the data line Xk to the pixel electrode 22a via the TFT 21, and the liquid crystal capacitor 22 and the storage capacitor 23 are charged and discharged according to this potential level. Thereby, the transmittance of the liquid crystal layer is controlled in accordance with the potential difference between the pixel electrode 22a and the counter electrode 22b (applied potential of the liquid crystal), so that a predetermined gradation corresponding to the data potential V is obtained in the pixel 2. It has become.

Here, the driving of the pixel 2 is performed by AC driving in which the potential polarity is inverted every predetermined period in order to extend the life of the liquid crystal. The potential polarity is defined based on the direction of the electric field acting on the liquid crystal layer, in other words, based on the forward and reverse of the applied potential of the liquid crystal layer. In the present embodiment, common DC driving, which is one type of alternating drive, that is, the potential Vlcom applied to the counter electrode 22b and the potential Vcs applied to the common capacitor electrode are maintained constant, and the pixel electrode 22a side is maintained. A drive system that reverses the polarity is adopted.

The control circuit 5 includes a vertical synchronization signal Vs and a horizontal synchronization signal H input from a host device (not shown).
s, the scanning line driving circuit 3, the data line driving circuit 4, and the frame memory 6 are synchronously controlled based on external signals such as the dot clock signal DCLK. Under this synchronization control, the scanning line driving circuit 3 and the data line driving circuit 4 perform display control of the display unit 1 in cooperation with each other. In the present embodiment, in order to suppress the occurrence of flicker by high-speed display, double speed driving is adopted in which the refresh rate (vertical synchronization frequency) is set to 120 [Hz] corresponding to twice the normal rate. In this case, one frame (1/60 [sec]) defined by the vertical synchronization signal Vs is composed of two fields, and two line sequential scans are performed in one frame.

The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit, and the like, and corresponds to a period in which one scanning line Yj is selected by outputting a scanning signal SEL to each of the scanning lines Y1 to Yn. The scanning lines Y1 to Yn are sequentially selected every one horizontal scanning period (1H). Scanning signal S
EL takes a binary level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and the scanning line Y corresponding to a pixel row to which data is to be written.
j is set to the H level, and the other scanning lines Yj are set to the L level. This scanning signal S
The pixel rows to be written with data are sequentially selected by EL, and the data written in the pixels 2 is held over one field.

The frame memory 6 has at least an m × n-bit memory space corresponding to the resolution of the display unit 1, and stores and holds display data input from the host device in units of frames. Writing of data to the frame memory 6 and reading of data from the frame memory 6 are controlled by the control circuit 5. Here, the display data D defining the gradation of the pixel 2 is, for example, 64 gradation data composed of 6 bits D0 to D5. Frame memory 6
The display data D read out is serially transferred to the data line driving circuit 4 through a 6-bit bus.

The data line driving circuit 4 provided in the subsequent stage of the frame memory 6 cooperates with the scanning line driving circuit 3 to simultaneously supply data to be supplied to the pixel rows to which data is written to the data lines X1 to Xm. Output. As shown in FIG. 1, the data line driving circuit 4 includes a driver IC 41 and a time division circuit 42. The driver IC 41 is provided separately from the display panel in which the pixels 2 are formed in a matrix. The i output pins PIN1 to PINi are connected to the output line D.
O1 to DOi are connected. The time division circuit 42 is integrally formed on the display panel by polysilicon TFTs or the like in order to reduce manufacturing costs.

The driver IC 41 simultaneously outputs data for a pixel row to which data is written this time and performs dot-sequential latching of data relating to a pixel row to which data is to be written next time. FIG. 3 is a block configuration diagram of the driver IC 41. The driver IC 41 includes an X shift register 4
Main circuits such as 1a, a first latch circuit 41b, a second latch circuit 41c, a changeover switch group 41d, and a D / A conversion circuit 41e are incorporated. The X shift register 41a transfers the start signal ST supplied at the beginning of the horizontal scanning period 1H in accordance with the clock signal CLX, and any one of the latch signals S1, S2, S3,. Set to level. The first latch circuit 41b includes latch signals S1, S2, S3,.
At the fall of m, m pieces of 6-bit data D supplied as serial data are sequentially latched. The second latch circuit 41c simultaneously latches the data D latched by the first latch circuit 41b when the latch pulse LP falls. The latched m pieces of data D are output in parallel from the second latch circuit 41c as data signals d1 to dm, which are digital data, in the next horizontal scanning period 1H.

As an example, the data signals d1 to dm are m / 3 pieces (== 3 data line units).
i) switch groups 41d are grouped as time-series data for three pixels. Here, in FIG. 3, the single changeover switch group 41d is illustrated as a set of four switches, but actually, there are four 6-bit switch groups. At this time, since the six switches in the same system always operate in the same manner, the following description will be made assuming that the six switches are one switch.

In addition to the data signals (for example, d1 to d3) for three pixels output from the second latch circuit 41c, correction data damd is also input to each changeover switch group 41d. The correction data damd is digital data that defines a potential level of a correction potential Vamd described later. The four switches constituting the changeover switch group 41d are conductively controlled by any one of the four control signals CNT1 to CNT4, and are sequentially turned on alternately at the offset timing. As a result, the correction data damd in the horizontal scanning period 1H.
And the data signals d1 to d3 for three pixels are in this order (damd, d1, d2, d
3) and output in time series from the changeover switch group 41d.

The D / A conversion circuit 41e performs D / A conversion on a series of digital data output from each changeover switch group 41d, and generates a potential as analog data. As a result, the correction data damd is converted into the correction potential Vamd, and the data signals d1 to dm time-series in units of three pixels are converted into data potentials and then output in time series from the output pins PIN1 to PINi. The

As shown in FIG. 1, the output pins PIN1 to PINi of the driver IC 41 are connected to the output line D.
One of O1 to DOi is connected. One output line DO is associated with three adjacent data lines Xk-1, Xk, and Xk + 1 grouped together, and the data line Xk-1 grouped with one output line. , Xk, and Xk + 1 are time division circuits 42.
Are provided for each output line. Each time division circuit 42 has three selection switches corresponding to the number of grouped data lines Xk−1, Xk, and Xk + 1, and each selection switch receives a selection signal from the control circuit 5. The conduction is controlled by any of SS1 to SS3. The selection signals SS1 to SS3 define an ON selection period (that is, a writing period described later) of the selection switch in the same group, and are synchronized with a time-series signal output from the driver IC 41. The i time division circuits 42 have the same configuration,
And since all operate | move simultaneously simultaneously, in the following description, it demonstrates paying attention only to the output line DO1 type | system | group from which data potential V1-V3 is output.

Of the above basic configuration examples, another basic configuration example of the driver IC shown in FIG. 3 is shown in FIG. FIG. 5 is a block diagram of a driver IC 41 according to another configuration example. 3 differs from the configuration shown in FIG. 3 in that a changeover switch group 41d is provided in the subsequent stage of the D / A conversion circuit 41e. Note that, since the input of the single changeover switch group 41d is an analog potential, unlike the case of FIG. 3, it is composed of only four switches as shown. Since points other than this are the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted here.

A data potential (for example, V1 to V3) for three pixels output from the D / A conversion circuit 41e is input to a certain changeover switch group 41d, and a correction potential Vamd is also input. The four switches constituting the changeover switch group 41d have four control signals CNT1 to CNT.
The conduction is controlled by any one of 4 and sequentially turned on alternately at the offset timing. Accordingly, in the horizontal scanning period 1H, the correction potential Vamd and the data potentials V1 to V3 for three pixels are time-series in this order (in order of Vamd, V1, V2, and V3),
The data is serially output from the corresponding output pin PIN1.

[Operation of basic configuration example]
FIG. 4 shows the operation of the basic configuration example configured as described above. FIG. 4 is a timing chart of time division driving according to the basic configuration example. The leftmost time division circuit 42 connected to the output line DO1
Supplies the correction potential Vamd output to the output line DO1 to the three data lines X1 to X3,
In addition, the time-series data potentials of three pixels are time-divided, and the individual data potentials obtained thereby are distributed to any one of the data lines X1 to X3. Specifically, in the first horizontal scanning period 1H in one field, the scanning signal SEL1 becomes H level and the uppermost scanning line Y1 is selected. In the horizontal scanning period 1H, the output line DO1 is first supplied with the correction potential Vamd.
Is output, and subsequently, data potentials V (1,1), V (2,1), V (3,1) for three pixels corresponding to the intersections of the data lines X1 to X3 and the scanning line Y1. ) Are output sequentially.

In a state where the correction potential Vamd is output to the output line DO1, the three selection signals SS
1 to SS3 are simultaneously set to the H level, and the three switches constituting the time division circuit 42 are simultaneously turned on. As a result, the correction potential Vamd output to the output line DO1 is changed to the data lines X1 to X1.
X3 is supplied all at once. That is, the data potentials V (1,1), V (2,1), V (3,
Prior to the supply of 1), the data lines X1 to X3 are charged and discharged by the correction potential Vamd.
The correction potential Vamd is a potential for reducing the influence of vertical crosstalk, and is set to a constant value 0 [V] in the present embodiment. However, the correction potential Vamd may be supplied to the three data lines in time series in an appropriate order instead of simultaneously.

Next, in a state where the data potential V (1, 1) is output to the output line DO1, only the selection signal SS1 becomes H level, and the data line X of the switches constituting the time division circuit 42 is selected.
Only the switch corresponding to 1 is turned on. As a result, the data potential V (1,1) output to the output line DO1 is supplied to the data line X1, and data is written to the pixel (1,1) according to the data potential V (1,1). Done. The data potential V (1,1
) Is being output, the switches corresponding to the data lines X2 and X3 remain off.
The potentials on the data lines X2 and X3 are maintained at the correction potential Vamd (exactly, the potential level decreases with time due to leakage).

Subsequently, in a state where the data potential V (2, 1) is output to the output line DO1, only the selection signal SS2 becomes H level, and the data line X of the switches constituting the time division circuit 42 is selected.
Only the switch corresponding to 2 is turned on. As a result, the data potential V (2,1) output to the output line DO1 is supplied to the data line X2, and data is written to the pixel (2,1) according to the data potential V (2,1). Done. The data potential V (2,1
) Is output, the switches corresponding to the data lines X1 and X3 remain off.
The data line X1 is maintained at the data potential V (1, 1), and the data line X3 is maintained at the correction potential Vamd.

Finally, in a state where the data potential V (3, 1) is being output to the output line DO1, only the selection signal SS3 becomes H level, and the data line X
Only the switch corresponding to 3 is turned on. As a result, the data potential V (3, 1) output to the output line DO1 is supplied to the data line X3, and data is written to the pixel (3, 1) according to the data potential V (3, 1). Done. The data potential V (3, 1
) Is output, the switches corresponding to the data lines X1 and X2 remain off.
The data line X1 is maintained at the data potential V (1, 1), and the data line X2 is maintained at the data potential V (2, 1).

In the next horizontal scanning period 1H, the scanning signal SEL2 becomes H level, and the second scanning line Y2 from the top is selected. In the horizontal scanning period 1H, the correction potential Vamd is first output to the output line DO1, and subsequently, the data potential V (3) for three pixels corresponding to each intersection of the data lines X1 to X3 and the scanning line Y2. 1, 2), V (2, 2), V (3, 2) are sequentially output. The process in the horizontal scanning period 1H is the same as that in the previous horizontal scanning period 1H except that the polarity of the potential output to the output line DO1 is inverted. The data potentials V (1,2), V (2,2), and V (3,2) are sorted. The same applies to the subsequent steps, 1H until the lowermost scanning line Yn is selected.
While the polarity is inverted every time, the supply of the correction potential Vamd to each pixel row and the subsequent distribution of the data potential are performed line-sequentially. 4 shows an example in which the polarity of the potential output to the output line DO1 is inverted every 1H period, the same applies to the case where the polarity is inverted every field or every frame. Operate.

For the output line DO2 system, the data line to be distributed becomes X4 to X6, and the same process as the above-described output line DO1 system is performed except that the potential to be distributed is different accordingly. Are performed in parallel. This also applies to each system up to the output line DOi.

In the above-described embodiment, the correction potential Vamd is set to 0 [V], which is an almost intermediate value of the data potential V (drive voltage), but the liquid crystal off potential (0 V) and the on potential (5 V or −
5V), ON potential (5V or -5V), intermediate potential between ON and OFF potential,
Alternatively, it may be a correction potential Vamd that is approximately the average of the data potentials applied to the data lines to which the correction potential Vamd is applied at the same time, and the specific value is appropriately set according to the characteristics of the display panel and the TFT. That's fine. In consideration of the complexity of the circuit configuration and the like, the correction potential Vamd is
The potential is preferably independent of the gradation of the pixel 2 to be displayed, but can be variably set according to the average value of the display data D or the like. Further, 0 [V] and 5 [V] may be alternately switched every predetermined period (for example, 1H). This also applies to each embodiment described later.

Note that, unlike the above operation, the data potential V is changed to the data lines X1, X2, and X2 by changing the selection order of switches constituting the time division circuit 42 every predetermined period (for example, 1H).
The order of distribution to X3 can also be changed. As a result, each output line DO1
The order of supplying the data potential V supplied to .about.DOi is reversed every 1H. Further, the order in which the data potential V is distributed to the data line X is not changed every period (1H) in which one scanning line Yj is selected, but in a period (one field) in which all the scanning lines Y1 to Yn are selected. It may be switched every time, and it is also possible to replace every 1H and every field.

[Embodiment]
Next, an embodiment according to the present invention will be described with reference to FIG. The basic configuration of the present embodiment can be configured in the same manner as in the above basic configuration example, and the driving method is basically the same as in each of the above-described operation examples. The description of this part is omitted.

In the present embodiment, as shown in FIG. 6, a main body 100 </ b> P having the display unit 1, and the main body 10.
A circuit board (for example, a flexible circuit board directly mounted on the main body 100P or a board indirectly installed in the electronic device) 100F directly or indirectly connected to 0P. The main body 100P is provided with the display unit 1, the scanning line driving circuit 3, the data line driving circuit 4, and an inspection circuit 7 for inspecting the display unit 1. here,
The scanning line driving circuit 3, the data line driving circuit 4, and the inspection circuit 7 are each configured by a semiconductor integrated circuit chip, for example, and may be mounted on the main body 100P or directly on the main body 100P (for example, on a substrate). It may be formed.

The circuit board 100F is provided with the control circuit 5 and the frame memory 6. The circuit board 100F is provided with a control terminal 5a derived from the control circuit 5 and a data terminal 6a derived from the frame memory 6, and these are connected to the data line driving circuit 4 on the main body 100P. . The circuit board 100F is provided with a reference terminal 8 for supplying a reference potential such as a ground potential, and the reference terminal 8 is conductively connected to a reference potential line 9 provided on the main body 100P.

In the main body 100 </ b> P, a reference potential line 11 that is conductively connected to the reference potential line 9 is provided on the outer edge of the display unit 1, and the reference potential line 11 is formed to extend along the outer periphery of the display unit 1. Yes. Further, a plurality of shield lines 12 are formed along the data lines X1 to Xm between the data line driving circuit 4 and the display unit 1, and these shield lines 12 are conductively connected to the reference potential line 11. Yes. These shield lines 12 are arranged between the plurality of data lines X1 to Xm. The shield line 12 is formed between the data line drive circuit 4 and the display unit 1 along the data lines X1 to Xm extending from the data line drive circuit 4 toward the display unit 1.

Further, between the data line driving circuit 4 and the display unit 1, data lines X1 to Xm (specifically, the data lines X1 to Xm and connection electrodes 14 (to be described later) electrically connected to these lines (FIGS. 7 to 9). The counter electrode 13 that forms a load capacitance is formed between the reference electrode 13) and the reference electrode 13). This counter electrode 13 is
The shield wire 12 is conductively connected.

FIG. 7 is a schematic plan view schematically showing a structure from the time division circuit 42 of the data line driving circuit 4 to the outer edge of the display unit 1 in the present embodiment. The time division circuit 42 includes a plurality of selection signal lines S.
S1 to SS8 are introduced, and switching elements SW1 to SW8 connected to these selection signal lines and output lines DO1 to DOi derived from the driver IC 41 are provided. Here, in the example shown in FIG. 7, unlike FIG. 1, eight data lines X1 to X8 are configured to correspond to the output lines DO1 to DOi, respectively. Selection signal lines SS1 to SS8 are provided, and eight switching elements SW1 to SW8 are provided for each output line and eight data lines. However, like the basic configuration example shown in FIG.
It is possible to appropriately set how many data lines correspond to one output line. In the following description, only one output line DO1 and the corresponding data lines X1 to X8 will be described, and the output line DO2 and the corresponding data lines X9 to X16 and thereafter, the output line DOi and the corresponding line. Since the data lines Xm-7 to Xm are all configured in the same manner, description thereof is omitted.

The switching elements SW1 to SW8 include a semiconductor layer 15, a source electrode 16 conductively connected to the source region of the semiconductor layer 15, a drain electrode 17 conductively connected to the drain region of the semiconductor layer 15, and a channel of the semiconductor layer 15. A gate electrode 18 is provided opposite to the region through an insulating film 19 shown in FIG. The source electrode 16 is conductively connected to the output line DO1, and the drain electrode 17 is conductively connected to any of the data lines X1 to X8.
The gate electrode 18 is conductively connected to any one of the selection signal lines SS1 to SS8.

These switching elements SW1 to SW8 are arranged in a line along the outer edge of the display unit 1, and are formed so that the source electrodes 16 and the drain electrodes 17 are always adjacent to each other between adjacent switching elements. ing. This can reduce the degree of capacitive coupling between the switching elements due to the adjacent of the source electrode 16 of one switching element and the drain electrode 17 of the other switching element between adjacent switching elements. Variation in data potential due to the capacitive coupling can be suppressed. In the present embodiment, eight switching elements are provided for each time division circuit 42. However, these 8 × i switching elements are all arranged in a line as described above, and all adjacent ones are adjacent to each other. The source electrodes and the drain electrodes are adjacent to each other between the switching elements.

In the present embodiment, the shield line 12 disposed between the data lines X1 to Xm is provided between the data line driving circuit 4 (specifically, the time division circuit 42) and the display unit 1, and the shield. A load capacitance conductively connected to the line 12 is provided. This load capacity includes the counter electrode 13 conductively connected to the shield line 12 and the connection electrode 1 conductively connected to the data lines X1 to Xm.
4 is configured in such a manner that an insulating film 19 shown in FIG. Here, in the case of the illustrated example, the counter electrode 13 has a structure sandwiched from above and below by the data lines X1 to X8 and the connection electrode 14, so that the load capacitance is only between the counter electrode 13 and the connection electrode 14. Instead, it is also formed between the data line and the counter electrode 13. This is effective in securing a sufficient capacitance value of the load capacitance even when the connection electrode 14 is formed of a semiconductor layer as will be described later.

In the present embodiment, the counter electrode 13 is conductively connected to the shield line 12, and as a result, is held at the same potential as the reference potential lines 9 and 11. As a result, the reference potential of the load capacitance becomes substantially constant, so that the potential stability of the data lines X1 to X8 can be reliably obtained.
In particular, the drive voltage-transmittance characteristics of the liquid crystal element have the steepest slope in the intermediate gradation, and therefore extremely high potential stability is required in the intermediate gradation. The stability of the data potential that can be fully satisfied can be realized.

In addition, since the counter electrode 13 constituting the load capacitor is connected to the reference potential via the shield line 12, it is possible to suppress the complexity of the wiring structure around the load capacitor, so that layout design and manufacture are easy. At the same time, it becomes possible to easily cope with higher definition of the electro-optical device.

In the case of the illustrated example, the counter electrode 13 is integrally configured for all the load capacities provided for each data line. As a result, it is possible to further stabilize the reference potential of each load capacitor, such as suppressing the potential fluctuation of the counter electrode 13 when performing line inversion driving, and to increase the area of the counter electrode 13. Thus, there is an advantage that a necessary capacity value can be easily secured as a load capacity.

In the vicinity of the display unit 1, the shield line 12 is connected to the reference potential line 11. This state is shown in the cross-sectional structure of FIG. As shown in the drawing, the reference potential line 11 extends so as to overlap the shield line 12 and the data lines X1 to X8, and each shield line 12 is conductively connected to the reference potential line 11 directly below, so that the potential of the shield line 12 is stabilized. As a result, the shielding effect can be further enhanced, and as a result, the parasitic capacitance between adjacent data lines can be substantially reduced.

Next, a more specific structure of the present embodiment will be described with reference to FIG. FIG. 9 is an enlarged partial cross-sectional view showing both an enlarged cross-section inside the display unit 1 and a marked cross-section of the data line and shield line formation region outside the display unit 1 of the present embodiment.

As shown in FIG. 9, in the display unit 1, the first substrate 110 and the second substrate 120 are fixed to each other at a predetermined interval of about 1 to 10 μm with a sealing material (not shown), and the liquid crystal 103 is enclosed therebetween. Has a structured. Here, the main body 100P shown in FIG. 6 has the first substrate 1 as described above.
An extended region in which the first substrate 110 protrudes outside the outer shape of the second substrate 120 is provided around the display unit 1 having a cell structure in which the liquid crystal 103 is arranged between the second substrate 120 and the second substrate 120. Various wiring circuit structures are formed on the projecting region, and ICs constituting other circuits are mounted. Note that an arrangement region of a sealing material (not shown) for bonding and fixing the first substrate 110 and the second substrate 120 to form the main body 100P is, for example, an introduction portion of the selection signal lines SS1 to SS8 in the time division circuit 42. , Switching element SW
1 to SW8 forming portion.

In the first substrate 110, the light shielding layer 110 </ b> B is formed in the element formation region arranged in the inter-pixel region on the transparent substrate 111. This light shielding layer 110B is a layer for blocking light entering from the transparent substrate 111 side from entering the inside. In this embodiment, the light shielding layer 110B is made of tungsten silicide (WSi) having a film thickness of 150 nm to 300 nm, for example.

An insulating layer 112 is formed on the transparent substrate 111 and the light shielding layer 110B. Insulating layer 11
In the present embodiment, 2 is made of silicon dioxide (SiO ₂ ) having a film thickness of 0.7 μm to 1.1 μm, for example. Then, in the position facing the light shielding layer 110B on the insulating layer 112 (right side in the figure), in this embodiment, an island-shaped semiconductor layer 114 having a film thickness of 30 nm to 60 nm made of polycrystalline silicon (polysilicon). Is formed. The semiconductor layer 114 preferably has an LDD structure in which a high concentration source region, a low concentration source region, a channel region, a low concentration drain region, and a high concentration drain region are formed in order from the left side in the drawing.

A gate insulating film 115 is formed over the semiconductor layer 114. This gate insulating film 115
In this embodiment, for example, it is made of silicon dioxide (SiO ₂ ) having a film thickness of 40 nm to 1000 nm. A gate electrode 116 is formed on the gate insulating film 115 at a position facing the channel region of the semiconductor layer 114. This gate electrode 1
In the present embodiment, 16 is made of, for example, polycrystalline silicon (polysilicon) having a film thickness of 300 to 400 nm. The gate electrode 116 is not shown in the scanning lines Y1 to Y.
connected to n.

A first interlayer insulating layer 113 is formed on the insulating layer 112, the gate insulating film 115, and the gate electrode 116. The first interlayer insulating layer 113 is, for example, 400 to 1000 nm.
Silicon dioxide having a thickness of which is composed of (SiO _2). A data line 117 (for example, X1 described above) is formed at a predetermined position on the first interlayer insulating layer 113. This data line 1
17 is made of a conductive material such as a laminate of aluminum (Al) and titanium nitride (TiN) having a thickness of about 300 nm to 700 nm. This data line 117
Is, for example, polycrystalline silicon (conductively connected to the high concentration source region of the semiconductor layer 114).
A source electrode formed of polysilicon or the like is conductively connected through a contact hole penetrating the first interlayer insulating layer 113.

A second interlayer insulating layer 118 is formed on the data line 117. This second
The interlayer insulating layer 118 is made of, for example, silicon dioxide (SiO 2 having a thickness of 400 to 1000 nm.
₂ ). A pixel electrode 119 made of a transparent conductor such as ITO (indium tin oxide) is formed on the second interlayer insulating layer 118. This pixel electrode 11
9 is conductively connected to a drain electrode formed on the high concentration drain region of the semiconductor layer 114 through a contact hole penetrating the first interlayer insulating layer 113 and the second interlayer insulating layer 118. The semiconductor layer 114, the gate insulating film 115, the gate electrode 116, and the source and drain electrodes constitute the TFT 21 that is a nonlinear element.

On the insulating layer 112, a connection electrode 24 that is formed of the same layer as the semiconductor layer 114 and is conductively connected to the high concentration drain region of the semiconductor layer 114 is provided.
An insulating film 25 composed of the same layer as the gate insulating film 115 is formed on the insulating film 25, and a capacitor line (not shown) (for example, parallel to the scanning line) is formed on the insulating film 25. )) Is formed in the same layer as the gate electrode 116. The connection electrode 24, the insulating film 25, and the connection electrode 26 constitute a storage capacitor (storage capacitor) 23 (see FIG. 2) provided in parallel with the liquid crystal capacitor for each pixel.

An alignment film 110R made of polyimide resin or the like is formed on the second interlayer insulating layer 118 and the pixel electrode 119, and the alignment film 110R regulates the liquid crystal 103 to a predetermined initial alignment state.

On the other hand, in the second substrate 120, a light shielding layer 120B is formed in the inter-pixel region on the transparent substrate 121 similar to the above. The light shielding layer 120B is for shielding light emitted from the liquid crystal 103 side, and is made of, for example, a black resin or a low-reflection chrome film. A common electrode 122 made of a transparent conductor such as ITO is formed on the transparent substrate 121 and the light shielding layer 120B.
Is formed. The common electrode 122 generates a predetermined electric field with the pixel electrode 119, and controls the alignment state of the liquid crystal 103 by the electric field. Here, the pixel electrode 11
9 and the common electrode 122 are planarly overlapped, and a region not covered with the light shielding layers 110B and 120B is a pixel region. Further, the alignment film 1 similar to the above is formed on the common electrode 122.
20R is formed.

The data lines X1 to Xm, the shield line 12, and the load capacity outside the display unit 1 according to this embodiment are as follows.
As shown in FIG. 9, it is composed of the same layers as those constituting the internal structure of the display unit 1 (TFTs, storage capacitors, etc., which are nonlinear elements). For example, the connection electrode 14 includes the semiconductor layer 1.
14 and the same layer as the connection electrode 24. The insulating film 19 is composed of the same layer as the gate insulating film 115 and the insulating film 25. Further, the counter electrode 13 is formed of the same layer as the gate electrode 116 and the connection electrode 26. Further, the data lines X1 to Xm and the shield line 12 are configured in the same layer as the data line 117.

As described above, since the shield wire 12 and the load capacity, which are the features of the present embodiment, are configured by the same layer as the internal structure of the original electro-optical device, man-hours in the manufacturing process are not increased, and almost no It becomes possible to manufacture an electro-optical device at the same manufacturing cost as in the prior art.

As described above, according to the present embodiment, the following effects can be obtained.
(1) By providing a shield line between data lines, capacitive coupling between the data lines can be reduced, so that fluctuations in the data potential can be suppressed.
(2) By connecting a load capacitor to the data line, fluctuations in the data potential due to capacitive coupling can be reduced.
(3) Since the load capacitance is connected to the shield wire, the complexity of the wiring structure can be suppressed, layout design and manufacturing can be easily performed, and high definition can be easily handled.
(4) Since the capacitive coupling between the switching elements can be reduced by devising the arrangement of the switching elements, fluctuations in the data potential can be suppressed.
(5) By configuring the shield line and the load capacity with the same layer as the nonlinear element and the holding capacity (storage capacity), it is possible to suppress an increase in manufacturing cost without increasing the number of manufacturing steps.

In addition, said embodiment is only an example in the case of comprising this invention, and this invention is not limited to the said embodiment. For example, in the above embodiment, the shield line 12 is formed only between the time division circuit 42 and the display unit 1, but the shield line 12 can be formed in the time division circuit 42 or the display unit 1. Further, the shield line 12 may be provided between the display unit 1 and the inspection circuit 7.

In the above embodiment, the load capacitance is formed between the time division circuit 42 and the display unit 1 (specifically, the end of the data line on the time division circuit 42 side). A load capacitor may be provided at the end of the opposite data line (opposite the display unit 1), or may be provided at both ends of the data line.

Furthermore, in the above-described embodiment, the case where a liquid crystal element is used has been described as an example, but the present invention is not limited to this, and an organic EL element, a digital micromirror device (DMD)
Or, FED (Field Emission Display) and SED (Surface-Conduction Electron-
(Emitter Display) etc.

The electro-optical device according to each embodiment described above can be mounted on various electronic devices including, for example, a television device, a projector device, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. If the above-described electro-optical device is mounted on these electronic devices, the product value of the electronic device can be further increased, and the product appeal of the electronic device in the market can be improved.

FIG. 3 is a block diagram illustrating a basic configuration example of an electro-optical device. FIG. 3 is an equivalent circuit diagram of a pixel using liquid crystal. The block block diagram of driver IC. 4 is a timing chart of time division driving in a basic configuration example. The block block diagram of a different driver IC. The schematic plan view which shows the whole structure of embodiment. The schematic plan view which shows the detailed structure from the time division circuit in an embodiment to a display part outer edge. The schematic sectional drawing (a) of the formation area of the switching element in embodiment, the schematic sectional drawing (b) of the formation area of a load capacity, and the schematic sectional drawing (c) of the connection part of a shield line and a reference potential line. The schematic partial longitudinal cross-sectional view which shows both the schematic cross section in the display part in embodiment, and the schematic cross section of the formation area of a shield wire and load capacitance.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display part, 2 ... Pixel, 3 ... Scanning line drive circuit, 4 ... Data line drive circuit, 5 ... Control circuit, 6
... Frame memory, 21 ... TFT, 22 ... Liquid crystal capacitor, 23 ... Retention capacitor, 41 ... Driver I
C, 42 ... time division circuit, DO1-DOi ... output line, SS1-SS8 ... selection signal line, X1-
Xm ... data line, Y1-Yn ... scanning line, SW1-SW8 ... switching element, 9, 11 ...
Reference potential line, 12 ... shield wire, 13 ... counter electrode, 14 ... connection electrode, 15 ... semiconductor layer, 1
6 ... Source electrode, 17 ... Drain electrode, 18 ... Gate electrode, 19 ... Insulating film

Claims (7)

A plurality of pixels, a plurality of data lines provided corresponding to each of the plurality of pixels, including a first data line, a second data line adjacent to the first data line, and the plurality of pixels. A data output circuit for outputting a plurality of data potentials defining a gradation to the output line in a time series, and a time division of the plurality of data potentials of the output line to the plurality of data lines and a dividing circuit when writing to the optical state of the plurality of pixels comprising an electro-optical device for electrically controlling,
A reference potential line for supplying a predetermined potential;
A first connection electrode disposed opposite to the first data line and electrically connected to the first data line;
A second connection electrode disposed opposite to the second data line and electrically connected to the second data line;
In cross-sectional view, the first data line and the second data line are disposed between the first data line and the first connection electrode and between the second data line and the second connection electrode. A counter electrode disposed opposite to the first connection electrode and the second connection electrode;
In plan view, and a shield line which connects conductively disposed Rutotomoni, and the reference potential line the counter electrode between the second data line and the first data line,
A first load capacitance configured between the counter electrode and the first connection electrode and between the counter electrode and the first data line ;
A second load capacitance configured between the counter electrode and the second connection electrode and between the counter electrode and the second data line;
An electro-optical device comprising:   The electro-optical device according to claim 1, wherein the shield line is provided between the time division circuit and a driving region in which the plurality of pixels are arranged. 3. The first load capacitor and the second load capacitor are provided between the time division circuit and a driving region in which the plurality of pixels are arranged. Electro-optic device. The time division circuit includes switching elements provided between the output line and the plurality of data lines corresponding thereto,
A plurality of said switching element includes a conductive-connected input electrode unit to the output line, and a conductive output coupled side electrode portions on the data line,
A plurality of said switching element includes a first switching element, and a second switching element adjacent to the first switching element, a third switching element adjacent to the second switching element, said first switching element The input side electrode portions of the second switching element and the output side electrode portions of the second switching element and the third switching element are arranged in an adjacent manner. Item 4. The electro-optical device according to any one of Items 1 to 3. And pixel electrodes provided corresponding to said pixel further comprises a non-linear element is conductively connected between the pixel electrode and the data lines, and a scanning line connected to the control electrode of the non-linear element ,
Each of the first load capacitor and the second load capacitor has the same layer as the control electrode as one electrode, the same layer as the semiconductor layer of the nonlinear element as the other electrode, and the control electrode and the semiconductor. The electro-optical device according to claim 1, wherein the same layer as an insulating film provided between the layers is configured as a dielectric. A storage capacitor provided in parallel with the pixel;
The said 1st load capacity | capacitance and the said 2nd load capacity | capacitance are each formed by the same layer as the some element which comprises the said storage capacity | capacitance, The Claim 1 thru | or 4 characterized by the above-mentioned. Electro-optic device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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