JP3839460B2 - Hold-type display device and parts thereof - Google Patents

Description

  The present invention relates to a hold-type display device suitable for a display panel that emits hold-type light emission, such as a liquid crystal display panel or an organic EL display panel, and its components, and in particular, pseudo impulse generation by so-called “black insertion technology”. The present invention relates to a hold-type display device and its components.

  In recent years, various proposals have been made in the field of large-sized liquid crystal display panels suitable for large screen televisions and the like for the purpose of eliminating so-called “moving image blur”. The cause of the “moving image blur” on the LCD panel is that when the viewpoint moves following the object in the video, the hold-type light emission is integrated with the luminance between the frames for the human eye, and the image corresponds to the jump distance between frames. It is known that deterioration occurs. Therefore, it is considered that blurring of moving images can be eliminated by correcting the hold type display to pseudo impulse type light emission by using a so-called “black insertion technique”.

As a conventional black insertion technique, while driving a gate driver and a source driver with a double speed clock, one frame of image data is written to the display panel in the first half frame time, and the latter half frame is written. It is known to write black data of one frame on a display panel over time (for example, FIG. 4 (a), FIG. 4 (b) on page 131 of the electronic journal separate volume 2003 FPD Technology and its description (March 25, 2003)). Japan, e-journal publication))).
E-journal separate volume 2003 FPD Technology Encyclopedia (Figs. 4 (a) and 4 (b) on page 131 and its explanation)

  The “black data” used in this specification is a general term for dark color data to dark color data used for painting and erasing image data, and is not limited to black.

  In this conventional black insertion technique, the black and image writing time is ½ horizontal period each because of the relationship of displaying two frames of black and image within one frame time. It has been pointed out that the pixel capacity cannot be fully charged within the period, leading to a decrease in contrast and a deterioration in image quality.

  Here, as a result of diligent research, the inventors of the present invention are that not only the image data but also the black data has a half horizontal period for each of a plurality of horizontal pixel columns. Therefore, if black data is written to a plurality of horizontal pixel columns at the same time by utilizing the fact that the data contents of black data are the same, the black data is written to the plurality of pixel columns. Time can be significantly reduced, and if the extra time is used, both the black writing time and the image writing time are increased without significantly increasing the clock speed. The knowledge that the deterioration of the can be improved.

  By the way, assuming a shift register type gate driver (horizontal scanning line driving circuit) that is most commonly used at present, sequential writing of image data to a plurality of horizontal pixel columns and black data to a plurality of horizontal pixel columns are performed. In order to alternately perform simultaneous batch writing, the scanning line selection data for writing image data and the scanning line selection data for writing black data are both present and shifted in a series of stages in the shift register. And control to output them to the horizontal scanning line as a scanning signal without conflict with each other at a necessary timing must be realized.

  However, considering that most of the shift registers built in the conventional gate drivers are composed of several shift register devices connected in series due to restrictions in the manufacturing process and manufacturing cost, In order to avoid output competition between the scan signal for writing data and the scan signal for writing black data, the scan line selection data for writing image data and the scan line selection data for writing black data are always It has been found that moving on different shift register devices significantly restricts the design freedom of the so-called “black insertion rate”, which is an important factor in this type of pseudo-impulse technique.

  This point will be described more specifically. State transition diagrams (first state to fourth state) showing the operation of the conventional gate driver are shown in FIGS. In the figure, 9A is a gate driver, G1 to G256 are output enable gates, 2-1 to 2-768 are horizontal scanning lines, 3 is the leftmost vertical scanning line, 91A to 93A are shift register devices, and 911A to 931A are A shift register element in the device.

  As is apparent from these drawings, the gate driver 9A includes three shift register devices 91A, 92A, and 93A. In addition to the shift register elements 911A, 921A, and 931A, device enable gates G1 to G256 are incorporated in each of the shift register devices 91A, 92A, and 93A. The shift register elements 911A, 921A, and 931A are connected in series via the conductor pattern on the substrate, for example, outside the device. The control input terminals of the device enable gates G1 to G256 in each of the devices 91A, 92A, and 93A are connected in common on a device basis, and then led to the device enable control terminals EN1, EN2, and EN3. CPV is a vertical shift clock signal, and STV is a vertical start signal. In this example, the number of horizontal scanning lines of the display panel is 768, and the shift register elements 911A, 921A, and 931A in each device have 256 stages for storing data.

  In the first state shown in FIG. 44, the first stage of the first-stage shift register element 911A has scanning line selection data for image writing (denoted as image STV in the figure. The same applies hereinafter). ) Is stored in the first and second stages of the second-stage shift register element 921A, respectively, for scanning line selection data for black writing (denoted as black STV in the figure, the same applies hereinafter). . In this state, the device enable control terminal EN2 of the second-stage shift register device 92A is active ("H") as black data is output from the source driver (not shown) onto the vertical signal line 3. Then, a scanning signal is output only to the horizontal scanning lines 2-257 and 258, and black data is written in the corresponding two horizontal pixel columns. At this time, since the device enable terminal EN1 of the first-stage shift register device is inactive (“L”), a scanning signal is not output to the horizontal scanning line 2-1.

  In the second state shown in FIG. 45, the scanning line selection data for image writing is also stored in the first stage of the first-stage shift register element 911A, and the first stage of the second-stage shift register element 921A. In the second stage, scanning line selection data for black writing is stored. In this state, the device enable control terminal EN1 of the first-stage shift register device 91A is active (“H”) as image data is output from the source driver (not shown) onto the vertical signal line 3. Then, the scanning signal is output only to the horizontal scanning line 2-1, and the image data is written into the corresponding one horizontal pixel column. At this time, since the device enable terminal EN2 of the second-stage shift register device 92A is inactive (“L”), black data is stored in the two horizontal pixel columns corresponding to the horizontal scanning lines 2-257 and 258. Never written.

  In the third state shown in FIG. 46, the input of one vertical shift clock (CPV) shifts the position of each scanning line selection data by one stage. That is, scanning line selection data for image writing is used for the second stage of the first-stage shift register element 911A, and black writing scanning is used for the second and third stages of the second-stage shift register element 921A. Each of the line selection data is stored. In this state, the device enable control terminal EN1 of the first-stage shift register device 91A is active (“H”) as image data is output from the source driver (not shown) onto the vertical signal line 3. Then, a scanning signal is output only to the horizontal scanning line 2-2, and image data is written to the corresponding one horizontal pixel column. At this time, since the device enable terminal EN2 of the second-stage shift register device 92A is inactive ("L"), black data is stored in the two horizontal pixel columns corresponding to the horizontal scanning lines 2-258 and 259. Never written.

  In the fourth state shown in FIG. 47, when one more vertical shift clock (CPV) is input, the position of each scanning line selection data is shifted by one stage. That is, scanning line selection data for image writing is used for the third stage of the first-stage shift register element 911A, and black writing scanning is used for the third and fourth stages of the second-stage shift register element 921A. Each of the line selection data is stored. In this state, the device enable control terminal EN2 of the second-stage shift register device 92A is active ("H") as black data is output from the source driver (not shown) onto the vertical signal line 3. Then, a scanning signal is output only to the horizontal scanning lines 2-259 and 260, and image data is written into the corresponding two horizontal pixel columns. At this time, since the device enable terminal EN1 of the first-stage shift register device 91A is inactive ("L"), black data is written to one horizontal pixel column corresponding to the horizontal scanning line 2-3. There is nothing.

  In the examples shown in FIGS. 44 to 47, since output enable can only be applied in units of shift register devices, the scanning line selection data for writing black data and the scanning line for writing image data are used. It must be avoided that the selected data is on the same shift register device. For this reason, a space of at least 256 stages is required between these dots, and from this, the black insertion rate is limited to a range of 256/768 (= 33%) to 512/768 (= 66%). Recognize.

  In general, the value of the black insertion rate required for each display panel is defined by the response of rising and falling between white and black of the display panel. The response of rising and falling is determined by the display panel. It varies considerably depending on the device structure (for example, TN, IPS, MVA, OCB, etc.). With black insertion technology, the reduction in brightness caused by inserting black on the screen becomes a fatal problem in image quality, so the black insertion rate is reduced to the minimum that can achieve blurring improvement effects according to the difference in response of these panels. Therefore, it is necessary to suppress a decrease in luminance. In the above-described method, the black insertion rate is limited to a range of 33% to 66%. If the insertion rate is less than 33% and finely set, the number of scanning lines per gate driver is reduced, and the gate driver is reduced. Increase the number of costs, resulting in increased costs. In addition, if the number of gate drivers has to be changed each time in accordance with the difference in panel responsiveness, there is a problem that it cannot be practically used as a general-purpose display panel driving device.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to simulate a hold-type display panel by applying a black insertion technique without causing a decrease in contrast or image quality. A highly versatile hold-type display device and its components that can achieve impulseization and that can easily be applied to display panels having various device structures while ensuring a wide degree of freedom in setting the black insertion rate. It is to provide.

Another object of the present invention is to provide a hold-type display device and its components that enable application of the pseudo-impulse technique to a TFT- on-gate TFT liquid crystal display panel.

  Another object of the present invention is to provide a hold type display device and its components capable of suppressing the occurrence of gradation even when the number of simultaneous writing lines of black data is increased. .

  Other objects and operational effects of the present invention will be easily understood by those skilled in the art by referring to the description of the following specification.

  The hold-type display device of the present invention has a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines. A hold type display panel, a source driver that outputs display data to each vertical signal line of the hold type display panel, and a scanning signal to a horizontal scanning line selected from the horizontal scanning lines of the hold type display panel It has an output gate driver and a video / timing controller.

  The gate driver is provided on each of a scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages and a parallel output line of the scanning shift register. And an output enable gate for opening and closing a scanning signal to each horizontal scanning line.

  These output enable gates are {kM + 1} -th, {kM + 2} -th,... {KM + M} -th, where k is an integer of 0, 1, 2,. An integer) is divided into M groups, and the output enable gates can be collectively opened and closed in units of groups corresponding to control signals given to each group from the outside.

  The video / timing control unit includes vertical direction control means and horizontal direction control means.

  The vertical direction control means receives (M-1) image data and one black data from the source driver every period corresponding to (M-1) horizontal scanning periods (H) of the video signal. The output of the display data from the source driver to the vertical signal line is controlled so as to be output to the vertical signal line.

  The horizontal direction control means captures the scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for black data writing into the first stage of the shift register at predetermined timings, respectively. In addition, the shift register is controlled so as to be shifted in accordance with the display data being output from the source driver to the vertical signal line. Further, when the image data is output from the source driver to the vertical signal line, the horizontal direction control means outputs only the scanning signal generated by the scanning line selection data for writing the image data to the corresponding horizontal scanning line. In addition, when black data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing black data for (M−1) lines corresponds. The output enable gate is controlled to be opened and closed for each group so that the signals are output simultaneously to the horizontal scanning line.

  Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. Thus, the pseudo-impulse of the hold type display panel is realized, and the black insertion rate can be changed in units of M (M−1) H.

  According to the above configuration, every time (M−1) pieces of image data are written into (M−1) horizontal pixel columns, black (M−1) horizontal pixel columns different from them are simultaneously black. By writing data, pseudo-impulse of the hold type display panel is realized and the black insertion rate can be changed in M (M-1) H units. While reducing the contrast, it is possible to avoid degradation of contrast and image quality as much as possible, and to ensure a wide degree of freedom in setting the black insertion rate, making it easy to apply to display panels with various device structures. can do.

  In a preferred embodiment of the present invention, the scan data shift register is formed by connecting a plurality of shift register devices having the same configuration in series, and output enable control for each group derived from each shift register device. The terminals may be interconnected so that the continuity of the group order of the output enable gates is maintained at the serial connection locations of the shift register devices. According to such a configuration, the cost can be further reduced by advancing standardization of the shift register device while ensuring versatility for various display panel devices.

In a preferred embodiment of the present invention, the hold-type display panel is a TFT- on-gate TFT liquid crystal display panel, and (M-1) horizontal pixel columns to which black data is simultaneously written are The relationship may be such that one or more horizontal pixel columns are separated from each other. According to such a configuration, even in a Cs on Gate type TFT liquid crystal display panel in which writing to a plurality of continuous scanning lines is difficult, it is possible to realize pseudo impulse by the black insertion technique.

  In a preferred embodiment of the present invention, the video data writing order for each of the (M−1) horizontal pixel columns may be changed for each frame. According to such a configuration, in order to increase the writing time of black data or image data, the number of black data simultaneous writing lines is increased, so that the interval between the image data writing start line and the end line is increased. Even when gradation occurs due to a difference in hold time, this can be canceled by image data between adjacent frames.

  The present invention viewed from another aspect can be grasped as a drive control device for a hold type display panel. That is, this device has a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch disposed corresponding to each intersection of the vertical signal lines and the horizontal scanning lines. Fits the panel.

  This apparatus outputs a scanning signal to a horizontal scanning line selected from among a source driver that outputs display data to each vertical signal line of the hold type display panel and each horizontal scanning line of the hold type display panel. A gate driver and a video / timing control unit;

  The gate driver is provided on each of a scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages and a parallel output line of the scanning shift register. And an output enable gate for opening and closing a scanning signal to each horizontal scanning line.

  These output enable gates are {kM + 1} -th, {kM + 2} -th,... {KM + M} -th, where k is an integer of 0, 1, 2,. An integer) is divided into M groups, and the output enable gates can be collectively opened and closed in units of groups corresponding to control signals given to each group from the outside.

  The video / timing control unit includes vertical direction control means and horizontal direction control means.

  The vertical direction control means receives (M-1) image data and one black data from the source driver every period corresponding to (M-1) horizontal scanning periods (H) of the video signal. The output of the display data from the source driver to the vertical signal line is controlled so as to be output to the vertical signal line.

  In the horizontal direction control means, the scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively taken into the first stage of the shift register at a predetermined timing. In addition, the shift register is controlled so as to be shifted in accordance with the display data being output from the source driver to the vertical signal line. Further, when the image data is output from the source driver to the vertical signal line, the horizontal direction control means outputs only the scanning signal generated by the scanning line selection data for writing the image data to the corresponding horizontal scanning line. In addition, when black data is output from the source driver to the vertical signal line, only the scanning signal generated by the scanning line selection data for writing black data for (M−1) lines corresponds. The output enable gate is controlled to be opened and closed for each group so that the signals are output simultaneously to the horizontal scanning line.

  Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. Thus, the pseudo-impulse of the hold type display panel is realized, and the black insertion rate can be changed in units of M (M−1) H.

  From another aspect, the present invention can be grasped as a video / timing control device for a display panel with a driver.

  That is, this video / timing control device includes a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines. A hold-type display panel, a source driver that outputs display data to each vertical signal line of the hold-type display panel, and a scanning signal to a horizontal scanning line selected from the horizontal scanning lines of the hold-type display panel And a gate driver that outputs a scanning signal, a scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages, and scanning. And an output enable gate provided on each of the parallel output lines of the shift register for opening and closing the scanning signal to each horizontal scanning line of the display panel. These output enable gates are {kM + 1} -th, {kM + 2} -th,... {KM + M} -th, where k is an integer of 0, 1, 2,. The output enable gates are divided into M groups, each of which is an integer), and their output enable gates are equipped with drivers that can be collectively opened and closed in groups corresponding to control signals given to each group from the outside. It is suitable for display panels.

  This video / timing control device includes vertical direction control means and horizontal direction control means.

  The vertical direction control means receives (M-1) image data and one black data from the source driver every period corresponding to (M-1) horizontal scanning periods (H) of the video signal. The output of the display data from the source driver to the vertical signal line is controlled so as to be output to the vertical signal line.

In the horizontal direction control means, the scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively taken into the first stage of the shift register at a predetermined timing. When the shift register is controlled so that the display data is shifted from the source driver to the vertical signal line and the image data is output from the source driver to the vertical signal line, When black data is output from the source driver to the vertical signal line so that only the scanning signal generated by the scanning line selection data for data writing is output to the corresponding horizontal scanning line, (M− 1) Each group unit is set so that only a scanning signal generated by scanning line selection data for writing black data for a line is simultaneously output to the corresponding horizontal scanning line. The output enable gate is controlled to open and close at the position.

  Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. As a result, pseudo hold of the hold-type display panel is realized, and the black insertion rate can be changed in units of M (M−1) H.

The present invention viewed from another aspect constitutes the video / timing control device for the display panel with driver described above.
For every period corresponding to (M−1) horizontal scanning periods (H) of the video signal, (M−1) image data and one black data are output from the source driver to the vertical signal line. Vertical direction control means for controlling the output of the display data from the source driver to the vertical signal line,
The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively fetched into the first stage of the shift register at a predetermined timing, and are perpendicular to the source driver. The shift register is controlled so that it is shifted in accordance with the output of display data to the signal line, and when image data is output from the source driver to the vertical signal line, scanning for writing image data is performed. When the black data is output from the source driver to the vertical signal line so that only the scanning signal generated by the line selection data is output to the corresponding horizontal scanning line, black for (M-1) lines. The output enable signal is output for each group so that only the scanning signal generated by the scanning line selection data for data writing is simultaneously output to the corresponding horizontal scanning line. Horizontal direction control means for controlling the opening and closing of the gate,
It can also be grasped as an FPGA (Field Programmable Gate Array), an ASIC (Application Specific IC), or an ASSP (Application Specific Standard Products).

  Further, according to another aspect of the present invention, the present invention reads source code to be read by a computer having a compiler function for generating and outputting a netlist necessary for producing the above-described FPGA, ASIC, or ASSP. It can also be understood as a recording medium recorded in a possible format.

  According to the display panel driving apparatus of the present invention, every time (M−1) pieces of image data are written into (M−1) horizontal pixel columns, (M−1) horizontal pixels different from them are written. By simultaneously writing black data into the pixel column, the hold-type display panel can be pseudo-impulsed and the black insertion rate can be changed in M (M-1) H units. While achieving pseudo-impulse application, it is possible to avoid deterioration of contrast and image quality as much as possible, and to secure a wide degree of freedom in setting the black insertion rate, to a display panel with various device structures Can be easily applied.

  In the following, a preferred embodiment of the present invention is described in detail with reference to the accompanying drawings. It should be noted that the embodiments described below show only a part of the present invention, and it is needless to say that the gist of the present invention is specified only by the description of the scope of claims.

  A block diagram showing the overall configuration of an embodiment of the apparatus of the present invention is shown in FIG. As shown in the figure, the display panel driving apparatus includes a TFT liquid crystal panel 1 as a display panel, a source driver 8, a gate driver 9, and a video / timing control unit 10. The source driver 8 and the gate driver 9 may be built in the display panel 1 by a semiconductor process, or a substrate on which the drivers 8 and 9 are mounted may be mounted on the display panel 1 with an adhesive or a screw.

  The liquid crystal panel 1 includes a pixel array formed by arranging pixels vertically and horizontally. Each pixel constituting the pixel array is provided with a thin film transistor (TFT) as a switching element. In the TFT array, the gate terminal of the TFT belonging to each pixel column in the horizontal direction is connected to the scanning line 2. Similarly, the drain terminal of the TFT belonging to each pixel column extending in the vertical direction is connected to the signal line 3. ing.

  FIG. 2 and FIG. 3 are explanatory diagrams showing the connection relationship between each TFT and the scanning line 2 and the signal line 3. As is well known to those skilled in the art, this type of TFT-type liquid crystal panel is classified into a Cs on Common type and a Cs on Gate type. Are known. An equivalent circuit diagram of the Cs on common system is shown in FIG. In the figure, 2 is a horizontal scanning line, 3 is a signal line, 4 is a TFT, 5 is a liquid crystal capacitor, 6 is a storage capacitor, and 7 is a common electrode.

  As is apparent from the figure, in the liquid crystal panel of the Cs-on-common method, after one end of the liquid crystal capacitor 5 and one end of the storage capacitor 6 are connected in common, each signal line is connected via the TFT 4 serving as a switching element. 3 is connected. The other end of the liquid crystal capacitor 5 and the other end of the storage capacitor 6 are connected to the common electrode 7. As described above, in the liquid crystal display panel of the SX on common type, the liquid crystal capacitor 5 and the storage capacitor 6 are connected in parallel between the signal line 3 and the common electrode 7. Therefore, the pixel columns existing on the adjacent scanning lines N and N + 1 can be driven simultaneously by making those scanning lines active.

  On the other hand, FIG. 3 shows an equivalent circuit diagram of the CS on gate system. In the figure, the same components as those in FIG. 2 described above are denoted by the same reference numerals, and description thereof is omitted. As can be seen from the figure, in the case of the Cs-on-gate method, the other end of the storage capacitor 6 is not the common electrode 7 but the scanning line (N−) before the scanning line (N) to which the pixel belongs. 1), that is, connected to the gate of TFT4. Therefore, if the pixels belonging to the adjacent scanning lines (N, N + 1) are simultaneously driven, the other end of the storage capacitor 6 belonging to the scanning line N + 1 cannot be maintained at “L”, which is sufficient for the storage capacitor. Charges are not accumulated and normal images are not displayed. As a result, there arises an inconvenience that pixels belonging to two adjacent scanning lines N and N + 1 cannot be driven simultaneously. This point has been found by the present inventors through intensive studies.

  Returning to FIG. 1, the source driver 8 is well known to those skilled in the art, not shown, and includes, for example, a shift register that takes in and shifts a horizontal start signal (STH), and a shift register. A first register group for serial-parallel conversion that sequentially captures image data for one horizontal scanning line of an image from a video source (for example, a DVD player, a computer, a TV tuner, etc.) and one horizontal cycle In response to the latch pulse (LP) at the end of each, the second register group that captures the image data captured in the first register group in parallel and the series of images captured in the second register group. Each of the data is converted into a gradation voltage having a polarity specified by the polarity instruction signal (POL) and output to each of the vertical signal lines 3, 3,... It can be configured to include, and A converter group.

  On the other hand, the gate driver 9 is a main part of the present invention and has a characteristic circuit configuration. The details of the gate driver will be described later in detail with reference to FIGS.

  Next, the configuration of the video / timing control unit 10 will be described. As shown in FIG. 1, the video / timing control unit 10 includes a scaler 11, a timing controller 12, and a black insertion circuit 13.

  As is well known to those skilled in the art, the function of the scaler 11 is intended to match the format on the video source side and the format on the display panel side. Examples of the format to be matched include a screen size and a scanning format. A signal line group 11a indicated by a thick arrow drawn from the scaler 11 includes various signals output from the scaler 11. Examples of these signals include RGB data (Data), dot clock signal (DCLK), horizontal synchronization signal (HSYNC), vertical synchronization signal (VSYNC), and data enable signal (DE).

  Next, the configuration of the timing controller 12 will be described. The timing controller 12 generates a data string and a signal group suitable for the source driver 8 and a signal group suitable for the gate driver 9 based on various signals coming from the scaler 11 via the signal line 11a group. . As the timing controller 12, a conventional timing controller 12 can be used as it is.

  More specifically, in the timing controller 12, the source driver is synchronized with the dot clock (DCLK) based on the horizontal synchronization signal (HSYNC), the vertical synchronization signal (VSYNC), and the data enable signal (DE). A horizontal control signal is generated. This horizontal control signal includes a horizontal direction start signal (STH), a dot clock signal (DCLK), a latch pulse (LP), a polarity designation signal (POL), and the like. Further, the timing controller 12 synchronizes with the dot clock signal (DCLK) based on the horizontal synchronization signal (HSYNC), vertical synchronization signal (VSYNC), and data enable signal (DE) sent from the scaler 11, Generate vertical control signals for the driver. This vertical control signal includes a vertical start signal (STV), a gate driver shift clock signal (CPV), and an output enable signal (OE) which is a main part of the present invention. The details of the vertical start signal (STV), the gate driver shift clock signal (CPV), and the output enable signal (OE) generated in this way will be described later in connection with the operation description. The bold arrow 12a includes the horizontal and vertical control signals described above.

  Next, details of the black insertion circuit 13 will be described. In the following description, in order to simplify the description, a circuit when the number of output enable control signals OE is three is taken as an example. Further, it is assumed that the frequency of the second system dot clock (CLKN) is set to 3/2 times the frequency of the first system dot clock (DCLK).

  The black insertion circuit 13 corresponds to a main part of the present invention, and by inserting black into a screen displayed by data supplied from an image source, the hold type display panel device is converted into a pseudo impulse, It solves the problem of afterimages when displaying moving images.

  A block diagram showing details of the black insertion circuit is shown in FIG. As shown in the figure, the black insertion circuit 13 includes a phase locked loop circuit (PLL) 131, a data generation circuit 132, a horizontal direction control circuit 133, a vertical direction control circuit 134, and a timing adjustment circuit 135. Contains.

  The phase-locked loop circuit (PLL) 131 generates a first system dot clock signal (DCLK) and a second system dot clock signal (CLKN) based on the dot clock signal (DCLKIN) output from the timing controller 12. Output. Here, the frequency of the first-system dot clock signal (DCLK) is set to one time the input-side dot clock signal (DCLKIN), and the frequency of the second-system dot clock signal (CLKN) is the input-side dot clock. It is set to M / (M−1) times the signal (DCLKIN). The dot clock signal (DCLK) of the first system obtained in this way is supplied to the data generation circuit 132 and the horizontal direction control circuit 133 provided in the subsequent stage. Similarly, the dot clock signal (CLKN) of the second system is supplied to each of the data generation circuit 132, the horizontal direction control circuit 133, the vertical direction control circuit 134, and the timing adjustment circuit 135 provided in the subsequent stage. Is done.

  Next, the data generation circuit 132 will be described. A block diagram showing details of the data generation circuit is shown in FIG. As shown in the figure, the data generation circuit 132 includes a FIFO (First In First Out processing unit) 1321, a selector 1322, a flip-flop 1323, and a black data generation circuit 1324.

  The FIFO 1321 writes the video signal (DATA) to a memory (not shown) in the FIFO in synchronization with the first system dot clock signal (DCLK) while the FIFO write enable signal (FIFO_WE) is active. Further, during the period when the FIFO read enable signal (FIFO_RE) is active, the video signal (DATA) is read from the memory inside the FIFO in synchronization with the second system dot clock signal (CLKN).

  The black data generation circuit 1324 generates black or dark-color to dark-color video data necessary for the painting process of the present invention. The selector 1322 is selected and controlled by the FIFO read enable signal obtained by delaying the second system dot clock by one clock in the flip-flop 1323, and the video signal (DATA) signal read from the FIFO 1321 and the black data generation circuit 1324. One of the output black data (BLACK) is selected and output as a video signal (DATA_bit).

  Next, returning to FIG. 4, the horizontal direction control circuit 133 will be described. A block diagram showing details of the horizontal control circuit is shown in FIG. As shown in the figure, the horizontal direction control circuit 133 includes a FIFO write enable signal generation circuit 1331, a horizontal direction start signal generation circuit 1332, a FIFO read enable signal generation circuit 1333, a horizontal counter 1334, and a latch pulse. A signal generation circuit 1335 and a polarity designation signal generation circuit 1336 are included.

  As shown in FIG. 7, the FIFO write enable signal generation circuit 1331 includes an enable generation circuit 1331a and a counter 1331b. The counter 1331b is counted up by the dot clock signal (DCLK) and is reset at the leading edge of the horizontal direction start signal (STH). On the other hand, the enable generation circuit 1331a includes a flip-flop (not shown) that is set to “H” at the leading edge of the horizontal start signal (STH) and is reset when the count value of the counter 1331b reaches a certain value. Yes. The output of this flip-flop is output as a FIFO write enable signal (FIFO_WE).

  Next, returning to FIG. 6, the horizontal direction start signal generation circuit 1332 will be described. FIG. 8 is a block diagram showing details of the horizontal start signal generation circuit. As shown in the figure, the STH generation circuit 1332 includes an STH edge extraction circuit 1332a, a state circuit 1332b, a counter 1332c, an STH generation circuit (decoder) 1332d, an OR gate 1332e, and AND gates 1332f to h. And an OR gate 1332i.

  The STH edge extraction circuit 1332a detects the rising edge of the odd-numbered horizontal start signal (STH) and generates and outputs a 1CLK width pulse. The counter 1332c is count-up controlled by a dot clock signal (CLKN) and is reset by an edge detection signal output from the STH edge detection circuit 1332a. The count value (PIX_COUNT) of the counter 1332c is supplied to the STH generation circuit (decoder) 1332d. The STH generation circuit (decoder) 1332d generates and outputs a horizontal start signal (STH_bit) that is a pulse of 1 CLK width every time the count value (PIX_COUNT) given from the counter 1332c reaches a specific value. Further, the horizontal start signal (STH_bit) is supplied to the reset terminal of the counter 1332c and the state circuit 1332b.

  Next, the state circuit 1332b will be described. The state circuit 1332b has three types of state signals S1, S2, and S3 based on the edge detection signal supplied from the STH edge detection circuit 1332a and the horizontal start signal (STH_bit) supplied from the STH generation circuit (decoder) 1332d. S0 and a blanking signal (BLANKING) are generated and output. These state state signals S1, S2, S0, and BLANKING are set to “H” when active. In this example, the status signal S1 corresponds to the first data output period, S2 corresponds to the second data output period, and S0 corresponds to the black data output period. Further, BLANKING represents a vertical blanking period.

  The state signals S1, S2, S0 and the blanking signal (BLANKING) are generated as follows. First, as a premise, the periods corresponding to the state signals S1, S2, and S0 do not overlap each other. These signals S1, S2, and S0 repeatedly appear in the order of S0, S1, and S2 every time a horizontal start signal (STH_bit) arrives from the STH generation circuit 1332d. When an edge detection signal arrives from the STH edge detection circuit 1332a, the S0 state is always set.

  The state signal S0 obtained in this way is gated by the horizontal direction start signal (STH_bit) in the AND gate 1332h and then output to the outside as the horizontal direction image start signal (STH_C1). The state signal S1 is gated by an AND gate 1332f with a horizontal direction start signal (STH_bit) and then output to the outside as a horizontal direction image start signal (STH_C2). Similarly, the state signal S2 is gated by the horizontal start signal (STH_bit) in the AND gate 1332g and then output to the outside as the horizontal black start signal (STH_BLACK). The state signal S0 is output to the outside as it is as a black state signal (STATE_BLACK). Further, the horizontal start signal (STH_bit) and the state signal S0 are logically ANDed with the AND gate 1332h, and further logically ORed with the horizontal direction start signal (STH_C2) with the OR gate 1332i. A direction image start signal (STH_COLOR) is output to the outside.

  Next, the blanking signal (BLANKING) will be described. As described above, the blanking period is a vertical blanking period, and when the blanking signal (BLANKING) is switched from the S2 state to the S0 state, the signal (STH) and the signal (STH_bit) have the same timing. If the signal does not arrive at “H”, “H” is output. On the other hand, when the signal (STH) arrives thereafter, “L” is output and the signal (COLOR_BLANK) is output as it is.

  Each signal output from the STH generation circuit in this way has the following meaning. First, the signal (STH_C1) corresponds to a start signal of image data to be written for the first time. The signal (STH_C2) corresponds to a start signal for image data to be written a second time. The signal (STH_BLANKING) corresponds to a black data start signal. The signal (STATE_BLACK) corresponds to a signal representing a black data output period. The signal (COLOR_BLANK) corresponds to a signal indicating a blanking period. The signal (STH_COLOR) corresponds to a start signal for image data. The signal (STH_bit) corresponds to a start signal for the source driver 8. A time chart showing the operation of each signal of these STH generation circuits is shown in FIG.

  Next, returning to FIG. 6, the FIFO read enable generation circuit 1333 will be described. This circuit 1333 has a circuit configuration similar to that of the FIFO write enable generation circuit 1331 described above, and only the input / output relationship is different. That is, in the FIFO write enable generation circuit 1331 shown in FIG. 7, the input of the enable generation circuit 1331a is replaced with a horizontal image start signal (STH_COLOR), the count clock of the counter 1331b is replaced with a dot clock signal (CLKN), If the reset input of the counter 1331b is replaced with a horizontal image start signal (STH_COLOR), the FIFO read enable generation circuit 1333 can be configured as it is.

  Next, returning to FIG. 6, the horizontal counter 1334 will be described. As shown in FIG. 9, the horizontal counter 1334 is a counter that counts the dot clock signal (CLKN) and is reset by the horizontal direction start signal (STH_bit). That is, this horizontal counter counts and outputs the number of dots in the horizontal direction and operates in a 2H / 3 cycle. Here, H is the original horizontal scanning period on the video source side.

  Next, returning to FIG. 6, the latch pulse generating circuit 1335 will be described. As shown in FIG. 10, the latch pulse generation circuit 1335 includes a first comparator 1335a, a second comparator 1335b, and an AND gate 1335c. When the value of the count data of the horizontal counter becomes larger than a predetermined LP rising value, the output of the first comparator 1335a changes from “L” to “H”. Similarly, the output of the second comparator 1335b changes from “H” to “L” when the value of the count data from the horizontal counter becomes larger than the predetermined LP falling value. As a result, a latch pulse (LP) having a specific width having a predetermined rising timing and falling timing is output and transmitted to the output side of the AND gate 1335c.

  Next, returning to FIG. 6, the polarity instruction signal generation circuit 1336 will be described. Details of the polarity instruction signal generation circuit 1336 are shown in FIG. As shown in the figure, this circuit includes a polarity initial state register 1336a, a polarity image register 1336b, a polarity black register 1336c, and a polarity selection circuit (selector) 1336d.

  The polarity initial state register 1336a generates an initial state signal (FIRST_STATE) based on the horizontal image start signal (STH_C1) and the image blanking signal (COLOR_BLANK) output from the horizontal direction start signal generation circuit 1332. That is, the polarity initial state register 1336a is an initial value setting register for the polarity instruction signal (POL), and its output signal (FIRST_STATE) is inverted at the head of each frame. That is, the polarity initial state register 1336a receives the first image start signal (STH_C1) after the image blanking signal (COLOR_BLANK) changes from “H” to “L” (or “L” to “H”). The output is inverted only at the rising edge. This is because the charge polarity of each pixel is alternately inverted every frame.

  The polarity designation image register 1336b includes an initial state signal (FIRST_STATE), a horizontal image start signal (STH_C1), a horizontal image start signal (STH_C2), and an image blanking signal (COLOR_BLANK) obtained from the polarity initial state register 1336a. Based on the above, an image polarity designation signal (POL_C) is generated. In other words, the polarity designation image register 1336b is initialized only at the rising edge of the first horizontal image start signal (STH_C1) after the image blanking signal (COLOR_BLANK) changes from “H” to “L”. A signal (FIRST_STATE) is read. Each time the horizontal image start signal (STH_C2) arrives, the contents of the image polarity designation signal (POL_C) are inverted.

  The polarity designation black register 1336c, based on the initial state signal (FIRST_STATE) output from the polarity initial state register 1336a, the horizontal direction black start signal (STH_BLACK), and the vertical direction black start signal (STV_BLACK) A signal (POL_B) is generated and output. That is, the polarity designation black register 1336c reads the state of the initial state signal (FIRST_STATE) at the rising edge of the horizontal black start signal (STH_BLACK). Each time the horizontal black start signal (STH_BLK) arrives, its output is inverted.

  The polarity designation select circuit (selector) 1336d selects one of the image polarity signal (POL_C) output from the polarity designation image register 1336b and the black polarity designation signal (POL_B) output from the polarity designation black register 1336c. Are selected and output to the outside as a polarity designation signal (POL_bit). This selection switching is controlled by a black state signal (STATE_BLACK) indicating black writing. That is, when the black state signal (STATE_BLACK) is “L”, the image polarity designation signal (POL_C) is selected, and when it is “H”, the black polarity designation signal (POL_B) is selected.

  Next, returning to FIG. 4, the vertical control circuit 134 will be described. The vertical direction control circuit 134 is based on a dot clock signal (CLKN) obtained from the PLL 131 and a horizontal direction start signal (STH_bit) obtained from the horizontal direction control circuit 133, and includes five signals (CPV_bit, STV_bit, OE1_bit, OE2_bit, OE3_bit) is generated and output.

  A block diagram showing details of the vertical control circuit is shown in FIG. As shown in the drawing, the vertical direction control circuit 134 includes an edge detection circuit 1341, a dot counter 1342, a vertical direction shift clock generation circuit 1343, a vertical direction start signal generation circuit 1344, and an output enable generation circuit. 1345.

  As shown in detail in FIG. 13, the edge detection circuit 1341 includes three systems of edge detection units. The first edge detection unit includes a first D-type flip-flop 1341a, a second D-type flip-flop 1341b, and an AND gate 1341c. The second edge detection unit includes a first D-type flip-flop 1341d, a second D-type flip-flop 1341e, and an AND gate 1341f. The third edge detection unit includes a first D-type flip-flop 1341g, a second D-type flip-flop 1341h, and two AND gates 1341i and 1341j.

  The first edge detection unit detects a rising edge of the horizontal start signal (STH_bit) and outputs a horizontal start signal rising edge detection signal (STH_H_DETECT) which is a pulse signal having a width of 1 CLK. The second edge detection unit detects the rising edge of the vertical shift clock signal (CPV_bit), and generates and outputs a vertical shift clock rising edge detection signal (CPV_H_DETECT) which is a 1 CLK width pulse signal. The third edge detector detects both the rising and falling edges of the vertical shift internal clock, and detects the vertical shift internal clock fall detection signal (INT_CPV_L_DETECT) and the vertical shift internal clock rise detection signal ( (INT_CPV_H_DETECT).

  Next, returning to FIG. 12, the dot counter 1342 will be described. As shown in FIG. 14, the dot counter 1342 counts the dot clock signal (CLKN) and is reset by the rising edge detection signal (STH_H_DETECT) of the horizontal start signal, and the count value is the horizontal period count signal (H_PERIOD_COUNT). Is output as That is, the dot counter 1342 is a counter that moves at a cycle of 2H / 3, and the counting operation is performed up to the number of dots in the horizontal direction (including the blanking period).

  Next, returning to FIG. 12, the vertical shift clock generation circuit 1343 will be described. Details of the vertical shift clock generation circuit 1343 are shown in FIG. As shown in the figure, this circuit 1343 includes a first comparator 1343a, a second comparator 1343b, an AND gate 1343c, a counter 1343d, a decoder 1343e, and an AND gate 1343f.

  When the value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined CPV rising value, the first comparator 1343a changes its output from “L” to “H”. When the value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined CPV falling value, the output of the second comparator 1343b changes from “H” to “L”. Therefore, on the output side of the AND gate 1343c, in response to the value of the horizontal period count signal reaching the CPV rising value, a pulse having a width corresponding to the difference between the CPV rising value and the CPV falling value is a vertical pulse. A direction shift internal clock signal (INT_CPV) is generated and output. In other words, in the internal clock signal for vertical shift, a clock pulse having a predetermined pulse width appears repeatedly with a period of 2H / 3.

  The counter 1343d is a so-called ternary counter, and repeatedly outputs count values “0”, “1”, and “2” sequentially. That is, the counter 1343d is count-controlled by the falling detection signal (INT_CPV_L_DETECT) of the internal clock for vertical shift, and counts up the dot clock signal (CLKN) only during the period of being enabled. As a result, “0”, “1”, and “2” are repeatedly output to the output side of the counter 1343d in a cycle of 2H / 3.

  The decoder 1343e decodes only one of the three values output from the counter 1343d, and outputs “H” to the output side. As a result, on the output side of the AND gate 1343f, a vertical shift clock signal (CPV_bit) that is a signal obtained by masking one of the three pulses generated in the internal clock signal for vertical shift is generated. Is output.

  Next, returning to FIG. 12, the vertical shift start signal generation circuit 1344 will be described. FIG. 16 is a block diagram showing details of the vertical shift start signal generating circuit. As shown in the figure, this circuit 1344 includes a first comparator 1344a, a second comparator 1344b, an AND gate 1344c, a line counter 1344d, an image decoder 1344e, a black decoder 1344f, Gate 1344g, AND gate 1344h, and OR gate 1344i are included.

  When the value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined vertical start signal falling value, the first comparator 1344a changes its output from “L” to “H”. When the value of the horizontal period count signal (H_PERIOD_COUNT) reaches a value corresponding to the falling value of the vertical start signal, the second comparator 1344b changes its output from “H” to “L”. Therefore, on the output side of the AND gate 1344c, a pulse signal having a predetermined pulse width determined by the value of the STV rising value and the STV falling value is generated and output in response to the rising of the horizontal period count signal (H_PERIOD_COUNT). .

  The line counter 1344d is a counter that counts the number of horizontal lines. The count enable control is performed by the vertical shift clock rising edge detection signal (CPV_H_DETECT), and the dot clock signal (CLKN) is output only when the count operation is enabled. Count. In other words, the line counter 1344d is counted up at the rising edge of the vertical shift clock rising detection signal (CPV_H_DETECT) and reset at the maximum number of horizontal lines. As a result, numerical data corresponding to the number of lines of the image being scanned is output to the output side of the line counter 1344d. This numerical data is supplied in parallel to the image decoder 1344e and the black decoder 1344f.

  The image decoder 1344e outputs “H” when the count value of the line counter 1344d is a count value corresponding to a specific line. Similarly, the black decoder 1344f outputs “H” when the count value of the line counter 1344d corresponds to a specific line. The decoded output of the picture decoder 1344e is supplied to an AND gate 1344g, and the decoded output of the black decoder 1344f is supplied to an AND gate 1344h. Therefore, the pulse signal output every horizontal period from the AND gate 1344c is gate-controlled by the AND gates 1344g and 1344h. As a result, a vertical start signal (STV_bit) to be supplied to the gate driver is output to the OR gate 1344i. At the same time, a vertical black start signal (STV_BLK) is generated and output on the output side of the AND gate 1344h.

  Next, returning to FIG. 12, the output enable generation circuit 1345 will be described. A block diagram showing details of the output enable generation circuit is shown in FIG. As shown in the figure, the circuit 1345 includes a first comparator 1345a, a second comparator 1345b, an AND gate 1345c, a counter 1345d, and a selector 1345e.

  The first comparator 1345a changes its output from “L” to “H” when the count value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined OE rising value. Similarly, when the count value of the horizontal period count signal (H_PERIOD_COUNT) reaches a predetermined OE falling value, the second comparator 1345b changes its output from “H” to “L”. As a result, on the output side of the AND gate 1345c, the value of the horizontal period count signal (H_PERIOD_COUNT) reaches the OE rising value and has a pulse signal having a pulse width defined by the difference between the OE rising value and the OE falling value. An internal output enable signal (INT_OE) is output. This internal output enable signal (INT_OE) is supplied to the selector 1345e.

  On the other hand, the counter 1345d is count-enable controlled by the vertical shift internal clock pulse rising detection signal (INT_CPV_H_DETECT), and counts the dot clock signal (CLKN) only when it is in the enabled state. More specifically, the counter 1345d is configured as a 9-value counter that repeatedly outputs “0” to “8” as count values.

  The selector 1345e has an internal output enable signal (INT_OE) as an input signal, and three output enable signals (OE1_bit, OE2_bit, OE3_bit) as output signals. The selector 1345e incorporates a selector function for allocating the internal output enable signal (INT_OE) to one of nine combinations of these three output lines. This selector function is a counter 1345d. Are controlled by nine types of count values “0” to “8” obtained from

For example, in the case of the first embodiment, the relationship between the count value of the counter 1345d and the output enable signals (OE1_bit, OE2_bit, OE3_bit) is as follows.
[1] When the count value is “0”, OE1_bit = “H”, OE2_bit = INT_OE, OE3_bit = INT_OE
[2] When the count value is “1” OE1_bit = INT_OE, OE2_bit = “H”, OE3_bit = “H”
[3] When the count value is “2”, OE1_bit = “H”, OE2_bit = INT_OE, OE3_bit = “H”
[4] When the count value is “3” OE1_bit = INT_OE, OE2_bit = INT_OE, OE3_bit = “H”
[5] When the count value is “4”, OE1_bit = “H”, OE2_bit = “H”, OE3_bit = INT_OE
[6] When the count value is “5” OE1_bit = INT_OE, OE2_bit = “H”, OE3_bit = “H”
[7] When the count value is “6” OE1_bit = INT_OE, OE2_bit = “H”, OE3_bit = INT_OE
[8] When the count value is “7”, OE1_bit = “H”, OE2_bit = INT_OE, OE3_bit = “H”
[9] When the count value is “8” OE1_bit = “H”, OE2_bit = “H”, OE3_bit = INT_OE

  Next, returning to FIG. 4, the timing adjustment circuit 135 will be described. The basic functions of the timing adjustment circuit 135 are black mixed data (DATA_bit) output from the data generation circuit 132, various signals (POL_bit, LP_bit, STH_bit) output from the horizontal direction control circuit 133, and vertical direction. By adjusting the phase of various signals (SPV_bit, STV_bit, OE1_bit, OE2_bit, OE3_bit) output from the control circuit 134 by clock synchronization using a D-type flip-flop group, a signal group (DATA_O, POL_O, LP_O, STH_O) and signal groups (CPV_O, STV_O, OE1_O, OE2_O, OE3_O) to the gate driver 9 are generated. The signal group obtained in this way is sent to the source driver 8 and the gate driver 9 and contributes to the black insertion operation for pseudo impulse generation according to the present invention.

  Next, the internal configuration of the gate driver 9, which is the main part of the present invention, will be described in detail with reference to FIGS.

  As shown in FIGS. 21 to 24, the gate driver 9 includes three semiconductor devices 91, 92, 93. Each of these semiconductor devices 91, 92, 93 incorporates shift register elements 911, 921, 931 having 256 stages in series. These shift register elements 911, 921, and 931 are connected in series with each other via a pattern on the substrate connecting the devices, thereby forming a shift register having serial 768 stages. Each of the shift register elements 911, 921, and 931 is provided with 256 parallel output lines. Output enable gates G1, G2 to G256 are provided for 256 parallel output lines of the shift register elements 911, 921, and 931, respectively.

  These gates G1, G2 to G256 are divided into three groups including a first group, a second group, and a third group. More specifically, when k is an integer of 0, 1, 2,..., The (3k + 1) th gates G1, G4, G7, G10... Belong to the first group. Similarly, the (3k + 2) th gates G2, G5, G8, G11... Belong to the second group. Furthermore, G3, G6, G9, G12... Which are the (3k + 3) th gate belong to the third group. The control inputs of a series of gates G1, G4, G7, G10... Belonging to the first group are connected in common within the device 91 and then led to the external terminal OE1. Similarly, the control input terminals of the gates G2, G5, G8, G11... Belonging to the second group are also connected in common within the device and then led to the external terminal OE2. Similarly, the control inputs of the gates G3, G6, G9, G12,... Belonging to the third group are also commonly connected in the device and then led to the external terminal OE3.

  On the other hand, each output line of the series of gates G1, G2 to G256 in each device 91, 92, 93 is led out from each of the devices 91, 92, 93, and the scanning lines 2-1, 2-2, ... connected to 2-768. Therefore, according to the gate driver 9 including the three devices 91, 92, 93, the first group common line, the second group common line, and the third group common line derived in the device are appropriately connected. Therefore, by making these common connection lines active at an appropriate timing, the black data or image data of each stage of the shift register elements 911, 921, 931 can be selectively led out to the outside in groups. It has become.

  Note that the shift register devices 91, 92, and 93 constituting the gate driver shown in FIGS. 21 to 24 have the same circuit configuration from the viewpoint of reducing the manufacturing cost. That is, the shift register elements 911, 921, and 931 all have 256 stages, and the output enable gates G1 to G256 included in each of them are divided into three groups. Furthermore, the (3k + 1) (where k is an integer of 0, 1, 2,...) Th output enable gate (G1, G4, G7...) Is in the first group, and the (3k + 2) th group is in the first group. The group order is determined so that the (3k + 3) -th group belongs to the third group in the two groups.

  In order to realize the operations necessary for the present invention, this group order needs to be continuous over the entire series of shift register elements 911, 921, 931. However, since the last gate G256 of the first-stage shift register element 911 belongs to the first group and the first gate G1 of the second-stage shift register element 921 belongs to the first group, each device 91, 92, When the common terminals derived from the first group are connected to each other in the first group, the repeated continuity of the group is lost at the connection portion between the first-stage shift register element 911 and the second-stage shift register element 921. . Therefore, in this example, the first group common line derived from the first-stage shift register device 91 corresponds to the second group common line derived from the second-stage shift register device 92 and the third group common line. It is connected to a third group common line derived from the shift register device 93 at the stage. The second group common line derived from the first-stage shift register device 91 includes the first group common line derived from the second-stage shift register device 92 and the third-stage shift register device 93. Is connected to the third group common line derived from. Further, the third group common line derived from the first-stage shift register device 91 includes the second group common line derived from the second-stage shift register device 92 and the third-stage shift register device. 93 is connected to the first group common line derived from 93. In this manner, the repetition of the group order of the output enable gates is maintained throughout the three shift register elements 911, 921, and 931.

  In the present invention, as will be described in detail later, the connection relationship between the first, second, and third group common lines derived from the devices 91, 92, 93 is included in the vertical start signal (STV_O). Black writing data, image writing data appearance timing, black data or image data appearance timing from the source driver 8, clock pulse appearance timing included in the vertical shift clock signal (CPV_O), By adjusting the enable timing of the output enable signals (OE1_O, OE2_O, OE3_O) to be given to the first, second, and third group common lines, it is possible to connect between the devices on the series of shift register elements 911, 921, 931. Data for black writing (scan line selection) separated by an arbitrary distance beyond the boundary of And image writing (scan line selection) data are simultaneously shifted and sent to the scan line without competing with each other, thereby suppressing the reduction in image writing time and writing black to each pixel row. This makes it possible to realize a pseudo impulse system that can be put to practical use.

  That is, as shown in FIG. 21, in the first state, there is data for image writing in the first stage of the shift register element 911 and data for black writing in the 251 and 252 stages. Assume that

  However, these image writing data and black writing data are distinguished for the sake of convenience, and both are actually input to the gate driver as a vertical direction start signal (STV_O). In the first state, it is assumed that black data is sent from the source driver 8 to the signal line 3. At this time, when the output enable signal OE1_O is non-active and OE2_O and OE3_O are activated as indicated by the bold lines in the figure, the gate G1 is closed and the gates G251 and G252 are opened, thereby causing two black signals. Only the write data is sent to the scanning lines 2-251, 2-252. As a result, as shown by the black circles in the figure, only the scanning lines 2-251, 2-252 are selected and two adjacent lines are selected. Black is simultaneously written in the horizontal pixel columns.

  As shown in FIG. 22, in the second state, image data is sent from the source driver to the signal line 3. At this time, OE1_O is active, and OE2_O and OE3_O are both inactive. Furthermore, no shift pulse appears in the vertical shift clock signal (CPV_O) during the transition from the first state to the second state. In this second state, the gate G1 is opened and the gates G251 and G252 are closed. Therefore, the image writing data stored in the first stage of the shift register element 911 is output to the scanning line 2-1 as a scanning signal, whereas it is stored in the 251 and 252 stages of the shift register element 911. The image writing data is not output to the scanning lines 2-251 and 2-252. Therefore, in this second state, as shown by the white circles in the figure, image data is written only to the horizontal pixel column corresponding to the scanning line 2-1.

  As shown in FIG. 23, image data is output to the signal line 3 in the third state. Further, the output enable signals OE1_O and OE3_O are inactive, and OE2_O is active. In addition, when shifting from the second state to the third state, one shift pulse appears in the vertical shift clock signal (CPV_O). Therefore, the image writing data existing in the first stage of the shift register element 911 is shifted to the second stage, and at the same time, the two black writing data existing in the 251st stage and the 252nd stage are respectively in the first stage. Shifted to the 252nd stage and the 253rd stage. At this time, the gate G2 is open, and the gates G252 and G253 are closed. Therefore, in this third state, the image writing data stored in the second stage is sent to the scanning line 2-2, whereas the black writing data stored in the 252nd stage and the 253rd stage is , Are not output to the scanning lines 2-252 and 2-253. As a result, in this third state, as shown by the white circles in the figure, image data is written only to the horizontal pixel column pixel row corresponding to the scanning line 2-2.

  As shown in FIG. 24, black data is sent to the signal line 3 in the fourth state. The output enable signals OE1_O and OE2_O are active, and OE3_O is inactive. At the time of transition from the third state to the fourth state, one shift clock appears in the vertical shift clock signal. Therefore, the image writing data that has existed in the second stage of the shift register element 911 until then is transferred to the third stage, and the two black writing data that have existed in the 252nd and 253th stages are the 253rd stage and the 2nd stage. Shifted to 254 stages. The gate G3 is closed and the gates G253 and G254 are open. Therefore, in this fourth state, the image writing data existing in the third stage is not output to the scanning line 2-3. The black writing data existing in the 253rd stage and the 254th stage is sent out to the scanning lines 2-253 and 2-254. Therefore, in this fourth state, as shown by black circles in the drawing, black data is written only to two horizontal pixel columns corresponding to the scanning lines 2-253 and 2-254.

  As described above with reference to FIGS. 21 to 24, in the present invention, the gate driver 9 having a specific circuit configuration is used, and this is used as a vertical start signal (STV_O) and three systems of output enable. By appropriately controlling with signals (OE1_O, OE2_O, OE3_O) and vertical shift clock signal (CPV_O), image writing data and black writing data are mixed in the shift register element 911 of the same device 91. However, it is possible to selectively output these to the corresponding scanning line, and by using this, the distance between the image writing data existence stage and the black writing data existence stage ( In other words, while setting the black insertion rate determinant) arbitrarily, image data writing for each line and multiple lines simultaneously It is carried out and writing alternately, it is possible to realize a pseudo-impulse-control by black writing for the purpose.

  That is, as previously described in the conventional example, if it is attempted to insert black on the screen while alternately repeating simultaneous writing of a plurality of lines and a plurality of times of image writing for each line, The distance from the black writing line must be at least 256 lines, which is the maximum number of lines in one device. This is accompanied by a very practical disadvantage in that the black insertion rate requirement can be dealt with only in the range of 33% to 66%. As is well known to those skilled in the art, the black insertion rate during black writing varies depending on the device characteristics of the display panel, and this is limited to the range of 33% to 66%. It becomes a big obstacle. On the other hand, according to the present invention, the black insertion rate can be arbitrarily changed in increments of 6 lines only by having the three output enable signals (OE1_O, OE2_O, OE3_O) shown in FIGS. Compared to the case of using a gate driver that cannot perform active / inactive control only in the unit of the previous device, the degree of freedom of the black insertion rate can be remarkably improved, and the reduction in luminance can be flexibly handled. I can do it.

  Next, a specific operation of the display panel driving apparatus described above will be described in detail with reference to FIGS. Note that the display panels shown in these drawings have a vertical scanning period of 24 lines for convenience of explanation, and 4 lines of 21 to 24 lines are used as a blanking period.

  Time charts (part 1 to part 3) showing operations of the source driver and the gate driver in the first embodiment are shown in FIGS. In the first embodiment, a liquid crystal display panel type is Cs on Common, three output enable signals (OE1_O, OE2_O, OE3_O), and a source clock frequency is 3/2 times. The thing is adopted.

  In FIGS. 25 to 27, the waveform (DATA) described at the top corresponds to 48-bit video data input to the black insertion circuit 13 shown in FIG. On the other hand, the waveform (DATA_O) described in the second row in these figures corresponds to the display data (DATA_O) with black insertion output from the black insertion circuit 13 shown in FIG. As can be seen by comparing these two waveforms, one black data and two image data are output in a 2H / 3 cycle in a period of 2H of data from the image source. The display data (DATA_O) with black insertion output from the black insertion circuit 13 is sent to the source driver 8 shown in FIG.

  In the source driver 8, display data is sequentially fetched into a first register group (not shown) by a horizontal start signal (STH_O) shifted by a dot clock, and data for one horizontal line is held. Based on the latch pulse (LP_O), data for one horizontal line is taken into a second register group (not shown). At the same time, the display data read into the second register group in this way is converted into a gradation voltage by a D / A converter (not shown) and then output from the source driver 8 to each signal line 3. The source driver output described in the fourth stage from the top in the figure indicates the output on the scanning line 3.

  On the other hand, on the gate driver 9 side, as described above, a predetermined control operation is performed based on the five systems of signals (CPV_O, STV_O, OE1_O, OE2_O, OE3_O). That is, in this example, a vertical shift pulse is output to the signal (CPV_O) in accordance with the data output timing from the source driver. However, of the timing when data is output from the source driver, a pulse is missing at the timing when image data is output after the timing when black data is output. As will be described in detail later, this is a device for writing the image data and the black data all over the continuous lines. Further, in this example, an image writing pulse and a black writing pulse appear in the signal (STV_O) at a predetermined time interval. In this example, the pulse width of the image writing pulse is about 2H / 3, and the pulse width of the black data writing pulse is set to about 4H / 3.

The operation shown in this time chart can be divided into nine states defined by three systems of output enable signals (OE1_O, OE2_O, OE3_O). The relationship between each state and the combination of signals OE1_O to OE3_O is as follows.
[First state]
OE1_O (non-active), OE2_O (active), OE3_O (active)
[Second state]
OE1_O (active), OE2_O (non-active), OE3_O (non-active [third state]
OE1_O (non-active), OE2_O (active), OE3_O (non-active)
[Fourth state]
OE1_O (active), OE2_O (active), OE3_O (non-active)
[Fifth state]
OE1_O (non-active), OE2_O (non-active), OE3_O (active)
[Sixth state]
OE1_O (active), OE2_O (non-active), OE3_O (non-active [seventh state]
OE1_O (active), OE2_O (non-active), OE3_O (active)
[Eighth state]
OE1_O (non-active), OE2_O (active), OE3_O (non-active [9th state]
OE1_O (non-active), OE2_O (non-active), OE3_O (active)

  Of the active states described above, the active color is black active, and the non-colored is active. When OE1_O is active, the (3k + 1) th line can be output. When OE2_O is active, the (3k + 2) th line can be output. When OE3_O is active, the (3k + 3) th line can be output. Also, the vertical start signal (STV_O) is appropriately input, and in the first state where black data is output from the source driver, the image writing data is in the stage corresponding to the first line, and the black writing data Are held on the stages corresponding to the 11th and 12th lines, respectively. Further, when shifting from the second state, the third state, the fifth state, the sixth state, the eighth state, and the ninth state to the next state, a vertical shift clock is input.

  In this manner, intermittently deleting the vertical shift clock pulse is a device for writing the image data and the black data to all the continuous lines as described above. If it is assumed that there is no missing pulse, an image is written on the second line, black is written on the 13th line and the 14th line, and then a pulse is input, so that the scanning line selection data becomes the first line. The stage is shifted to a stage corresponding to 4 lines, and writing of image data to the third line is lost. In order to prevent the omission of writing of image data as shown in this example, the pulse of the vertical shift clock is lost at the output timing of the image data next to the output timing of the black data.

  Assuming the above, in the first state in which black data is output from the source driver, only the eleventh line and the twelfth line are selected, and the black data for the horizontal pixel columns corresponding to these two lines is selected. Is written. In the second state in which the image data “1” is output from the source driver, only the first line is selected, and the image data is written to the horizontal pixel column corresponding to the first line. In the third state in which the second image data “2” is output from the source driver, only the second line is selected, and the image data “2” is written to the horizontal pixel row corresponding to the second line. Is done. In the fourth state in which black data is output from the source driver, only the thirteenth and fourteenth lines are selected, and black data is written into horizontal pixel columns corresponding to these two lines. In the fifth state in which the third image data “3” is output from the source driver, only the third line is selected, and the third image data “3” for the horizontal pixel column corresponding to the third line is selected. 3 ”is written. In the sixth state in which the fourth image data “4” is output from the source driver, only the fourth line is selected, and the fourth image data “4” for the horizontal pixel column corresponding to the fourth line is selected. 4 "is written. In the seventh state in which black data is output from the source driver, only the fifteenth line and the sixteenth line are selected, and black data is written into the horizontal pixel columns corresponding to these two lines. In the eighth state in which the fifth image data “5” is output from the source driver, only the fifth line is selected, and the fifth pixel data “5” for the horizontal pixel column corresponding to the fifth line is selected. Is written. In the ninth state in which the sixth image data “6” is output from the source driver, only the sixth line is selected, and the sixth image data “6” for the horizontal pixel column corresponding to the sixth line is selected. Is written.

  When a predetermined timing arrives while repeating the first state to the ninth state as described above, a start pulse for writing black data appears in the signal (STV_O). In this example, the pulse width of the start pulse for writing black data is set to about 4H / 3. This is to ensure that black write data is read into two successive stages of the shift register in response to two pulses appearing in the signal (CPV_O) (see FIG. 26).

  In this way, in order to continue the simultaneous writing of black data to two consecutive lines and the image data writing of one line at a time to two consecutive lines without conflict, display lines The sum (20 in this example) and the number of lines in the blanking period (4 in this example) (24 in this example) must be set to be a multiple of 6. This is because the first to ninth states described above are completed every 6H.

  Next, FIGS. 28 to 30 show time charts (part 1 to part 3) showing operations of the source driver and the gate driver in the second embodiment. The difference of the second embodiment from the first embodiment is that the insertion timing of the start pulse for black writing is different. That is, in the first embodiment shown in FIG. 26, the signal (CPV_O) continues in accordance with the timing when the 14th data is output from the source driver and the timing when the subsequent black data is output. Two pulses appear. Further, the black write start signal (STV_O) has a pulse width corresponding to the appearance period of the two clock pulses so that the black write data can be sent to the shift register at the rising edge of these two pulses. Appears on.

  On the other hand, in the case of the second embodiment, as shown particularly in FIG. 30, only the appearance timing of the start pulse for black writing is delayed by 6H. Specifically, in the case of the second embodiment, two pulses appear in the signal (CPV_O) in accordance with the output timing of the 20th image data and the subsequent black data from the source driver. To do. Further, a black data write start pulse having a width of approximately 4H / 3 appears in the signal (STV_O) so as to be read by these two consecutive pulses. As a result, compared with the first embodiment, the difference between the timing at which black is written on a certain line and the timing at which an image is written is reduced, thereby reducing the black insertion rate. In this way, the black insertion rate for the image can be freely changed by delaying the appearance timing of the black writing pulse every 6H.

  Next, time charts (part 1 to part 3) showing operations of the source driver and the gate driver in the third embodiment are shown in FIGS. The difference between the third embodiment and the first and second embodiments described above is that the output enable signal is increased from three lines to four lines. That is, in this third embodiment, four output enable signals comprising signals (OE1_O, OE2_O, OE3_O, OE4_O) are provided. Thereby, 16 states consisting of the first to sixteenth states are repeatedly set by the combination of the output enable signals. That is, when the signal OE1_O is active, the (4k + 1) th line can be output. When the signal OE2_O is active, the (4k + 2) th line can be output. When the signal OE3_O is active, the (4k + 3) th line can be output. When the signal OE4_O is active, the (4k + 4) th line is active.

  As for the relationship between the data (DATA) from the video source and the output data (DATA_O) from the black insertion circuit, one black data and three image data are input to the source driver within the period of 3H. The As a result, one black data and three image data are output from the source driver to each signal line within a period of 3H.

  Also, the vertical start signal (STV_O) is appropriately input, and in the first state where black data is output from the source driver, the image writing data is in the stage corresponding to the first line, and the black writing pulse Are held on stages corresponding to the 10th, 11th and 12th lines, respectively. Further, from the second state, the third state, the fourth state, the sixth state, the seventh state, the eighth state, the tenth state, the eleventh state, the twelfth state, the fourteenth state, the fifteenth state, and the sixteenth state. When shifting to the next state, it is assumed that a vertical shift clock is input.

  In the first state, only the tenth line, the eleventh line, and the twelfth line are selected, and black data is written to three horizontal pixel columns corresponding to these lines. In the subsequent second state, only the first line is selected, and the first image data “1” is written in the horizontal pixel column corresponding to the first line. In the subsequent third state, only the second line is selected, and image data is written to the horizontal pixel column corresponding to the same line. In the subsequent fourth state, only the third line is selected, and the third image data “3” is written only in the horizontal pixel row corresponding to the same line. In the subsequent fifth state, only the 13th line, the 14th line, and the 15th line are selected, and black data is written into the horizontal pixel columns corresponding to these lines. In the subsequent sixth state, only the fourth line is selected, and the fourth pixel data “4” is written to the horizontal pixel column corresponding to the same line. In the subsequent seventh state, only the fifth line is selected, and the fifth image data “5” is written to the horizontal pixel row corresponding to the same line. In the subsequent eighth state, only the sixth line is selected, and the sixth image data “6” is written in the horizontal pixel column corresponding to the line. In the subsequent ninth state, only the 16th line, the 17th line, and the 18th line are selected, and black data is written in the horizontal pixel columns corresponding to these lines. In the following tenth state, only the seventh line is selected, and the seventh image data “7” is written to the horizontal pixel column corresponding to the line. In the following eleventh state, only the eighth line is selected, and the eighth image data “8” is written to the horizontal pixel column corresponding to the line. In the twelfth state, only the ninth line is selected, and the ninth image data “9” is written to the horizontal pixel column corresponding to the line. In the following thirteenth state, only the 19th and 20th lines (the 21st line is not displayed because of the blanking period) are selected, and black data is written to the horizontal pixel column corresponding to the same line. . In the fourteenth state, only the tenth line is selected, and the tenth image data “10” is written in the horizontal pixel column corresponding to the same line. In the fifteenth state, only the eleventh line is selected, and the eleventh image data “11” is written in the horizontal pixel column corresponding to the line. In the sixteenth state, the twelfth line is selected, and the twelfth image data “12” is written in the horizontal pixel column corresponding to the line. Thereafter, similarly, the first to sixteenth states are repeatedly executed.

  According to the third embodiment, by increasing the output enable signal by one system, the writing time per line becomes 3H / 4. Compared with the first and second embodiments, image data and Black data writing time increases. By increasing the writing time, it is possible to suppress a decrease in the image data writing time due to the insertion of black data. In this example, since black is simultaneously written in three lines, the width of the pulse for black writing appearing in the signal (STV_O) is larger than that in the first and second embodiments. It is considered wide. In this example, the width of the black writing pulse is set to about 2H. This is because black write data is read into three consecutive stages of the shift register in response to three pulses appearing in the signal (CPV_O) (see FIG. 26).

  When the first and second embodiments are compared with the third embodiment, there is a difference in the number of output enable signals (OE) as described above. Here, when a general relational expression between the number of output enable signals and the black or image writing time is obtained, when the number of OE lines is M, the writing time is {(M−1) H} / M ( However, the image and black writing times are the same). A cycle of each state generated by the combination of OEs can be expressed as M (M−1) H. Therefore, the black insertion rate can be arbitrarily changed in increments of M (M-1) H, and the black insertion rate can be freely changed as compared with the conventional example using a gate driver that can be changed only in shift register device units. The degree can be increased.

  As described above, the number of display scanning lines and the blanking period are included in order to maintain a repetition cycle of simultaneous black writing of a plurality of lines and image writing of each line of a plurality of lines according to the present invention. Needless to say, it is preferable to set the sum total of the number of lines to be a multiple of M (M−1).

  Next, FIGS. 34 to 36 show time charts (No. 1 to No. 3) showing operations of the source driver and the gate driver in the fourth embodiment. The difference between the fourth embodiment and the first to third embodiments described above is that a Cs on Gate type TFT liquid crystal panel is used as the display panel.

  As described above with reference to FIG. 3, in the TFT-on-gate TFT liquid crystal panel, the other end of the storage capacitor 6 is connected to the gate of the previous scanning line. The inventors have found that if black data is simultaneously written to two pixel rows corresponding to adjacent scanning lines, writing of the black data is hindered. Therefore, in the fourth embodiment, by writing black data to be originally written to two consecutive pixel rows into two pixel rows separated by two lines controlled by the same OE, Even in the Cs on Gate type TFT liquid crystal panel, black can be simultaneously written to two adjacent lines.

  That is, in FIG. 34, in the first state, only the eleventh line and the fourteenth line are selected, and black data is written to the horizontal pixel columns corresponding to these two lines. In the second state, only the first line is selected, and the first image data “1” is written to the horizontal pixel column corresponding to the same line. In the third state, only the second line is selected, and the second image data “2” is written to the horizontal pixel column corresponding to the same line. In the fourth state, only the thirteenth and sixteenth lines are selected, and black data is written into two horizontal pixel columns corresponding to those lines. In the fifth state, only the third line is selected, and the third image data “3” is written to the horizontal pixel column corresponding to the same line. In the sixth state, only the fourth line is selected, and image data is written to the horizontal pixel column corresponding to the same line. In the seventh state, only the fifteenth line and the eighteenth line are selected, and black data is written into two horizontal pixel columns corresponding to these two lines. In the eighth state, only the fifth line is selected, and the fifth image data “5” is written to the horizontal pixel column corresponding to the same line. In the ninth state, only the sixth line is selected, and the sixth image data “6” is written to the horizontal pixel column corresponding to the line.

  In the fourth embodiment, the three output enable signals (OE1_O, OE2_O, OE3_O) are used, but the control is slightly different from the first embodiment. As is apparent from the first state to the ninth state, this difference is that only one OE is active in any state. Further, in the fourth embodiment, the method of inserting the write start pulse is also different from that in the first embodiment. That is, this difference is that, as shown in FIG. 35, when two lines are selected at the same time, a long and large pulse including the two lines in between is not caused to appear, but a pulse of approximately 2H / 3 width is intermittently generated. Thus, every other two lines are selected simultaneously. On the other hand, with respect to the black insertion rate, any black insertion rate can be realized in increments of 6 lines while simultaneously writing black in two lines separated by 2 lines in this way.

  Next, time charts (part 1 to part 3) showing operations of the source driver and the gate driver in the fifth embodiment are shown in FIGS. The feature of the fifth embodiment is that the speed of the source clock is increased compared with that of the fourth embodiment, thereby shortening the black writing time and increasing the image writing time accordingly. It is. That is, in the present invention, (M-1) image data and one black data are source driver for every period corresponding to (M-1) horizontal scanning periods (H) of the video signal. However, the image data output period and the black data output period do not have to be the same. It is also possible to shorten the black data writing period and extend the image writing period by using a clock having a frequency of M / (M-1) times or more. In this example, since the double source clock is used, the black writing time is H / 2 and the image writing time is 3H / 4.

  In the above embodiment, the output to the signal line is made constant (for example, black data) so that the shift register in the source driver is reset at once instead of sending black data to the source driver. Even if a function that enables the image signal is provided, (M-1) image data and one black data are obtained for each period corresponding to (M-1) horizontal scanning periods (H) of the video signal. The output of display data from the source driver to the vertical signal line can be controlled so that is output from the source driver to the vertical signal line.

  Next, time charts (No. 1 to No. 3) showing the output of the source driver and the operation of the gate driver in the sixth embodiment of the present invention are shown in FIGS. For the convenience of explanation, the display panels shown in these drawings use three signals (OE1_O, OE2_O, OE3_O) as output enable signals, and 3/2 times as the source clock frequency, and have a vertical scanning period. 18 lines, of which the 17th and 18th lines are the return period. The numbers in the source driver output column shown in the figure indicate the numbers of the scanning lines in which the image data is written.

  As is apparent from FIGS. 25 to 27 of the first embodiment described above, in the first embodiment, the black data is the first line and the second line, the third line and the fourth line,. While the scanning lines are simultaneously selected and written, the image data is written for each scanning line. Therefore, when attention is paid to two scanning lines (for example, the first line and the second line) in which black is simultaneously written, the display time of the image of one scanning line is 2H / 3 longer than the other. Also in the fourth embodiment, as is apparent from FIGS. 34 to 36, black data is simultaneously written in the first and fourth lines, the third and sixth lines, and two scanning lines. On the other hand, the image data is written for each scanning line. Therefore, when attention is paid to two scanning lines (for example, the first line and the fourth line) in which black is simultaneously written, the display time of the image of one scanning line is 8H / 3 longer than the other. The difference in display time may be recognized as a luminance difference by human eyes depending on the characteristics of the liquid crystal panel, the number of scanning lines simultaneously selected when writing black data, the number of vertical scanning lines, and the like. The present embodiment aims to eliminate these display time differences. In the sixth embodiment, the black writing method is the same as that of the fourth embodiment described above, but the image writing method is changed.

  Next, a method for writing these images will be described more specifically. 40 to 42, in the period A, the write data pulse input to the gate driver and shifted before the period A is held in the stage corresponding to the second line. During this period, since only the output enable signal OE2_O is enabled, an image is written to the second line.

  In the period B, the write data held in the stage corresponding to the second line in the period A is shifted by 1 CLK, and new write data is input to the stage corresponding to the first line and the third line. Retained respectively. During this period, since only the output enable signal OE1_O is enabled, an image is written only in the first line.

  In the period C, the write data is shifted by 1 CLK from the period B and is held in the stages corresponding to the second line and the fourth line, respectively. Since only the output enable signal OE1_O is enabled, an image is written only in the fourth line.

  In the period D, the write data is shifted by 1 CLK from the period C and is held in the stages corresponding to the third line and the fifth line, respectively. Since only the output enable signal OE3_O is enabled, an image is written only in the third line.

  In the period E, the write data is shifted by 1 CLK from the period D and held in the stages corresponding to the fourth line and the sixth line, respectively. Since only the output enable signal OE3_O is enabled, an image is written only in the sixth line.

  In the period F, the write data is shifted by 1 CLK from the period E and is held in the stages corresponding to the fifth line and the seventh line, respectively. Since only the output enable signal OE2_O is enabled, an image is written only in the fifth line.

  In the period G, the write data is shifted by 1 CLK from the period F and is held in the shift registers corresponding to the sixth line and the eighth line, respectively. Since only the output enable signal OE2_O is enabled, an image is written only in the eighth line.

  Thereafter, the same operation as in B to G is repeated and an image is written. Also, the image data is rearranged in the order of the numbers in the source driver output column so that the writing order is in accordance with these. In this case, a larger amount of data is required than in the fourth embodiment, so that the capacity of the image memory needs to be increased accordingly.

  On the other hand, as with the fourth embodiment, black data is written by selecting two scanning lines simultaneously such as the first line and the fourth line, the third line and the sixth line, the fifth line and the eighth line, etc. It is. If attention is paid to the first line and the fourth line, the image is written for each scanning line in such a manner that after the first line is selected and written, the fourth line is selected and written. On the other hand, in black, since two scanning lines are simultaneously written, the image display time T2 of the fourth line is 2H / 3 as compared with the image display time T1 of the first line as shown in FIGS. Only shortened. Similarly, other scanning lines have a time difference of 2H / 3 between two scanning lines selected at the same time. In order to eliminate these time differences, in the next frame, the order of images input to the source driver and the input timing of writing pulses are changed, and the writing order of these two scanning lines is changed.

  40 to 42, in the period I, the write data input and shifted to the gate driver before the period I is held in the stage corresponding to the second line. During this period, since only the output enable signal OE2_O is enabled, an image is written to the second line.

  In the period J, the write data held in the second line in the period I is shifted by 2 CLK and held in the shift registers corresponding to the fourth line. During this period, since only the output enable signal OE1_O is enabled, an image is written only in the fourth line.

  In the period K, the write data is shifted by 1 CLK from the period C, and a new start signal is input and held in the stages corresponding to the first line and the fifth line, respectively. Since only the output enable signal OE1_O is enabled, an image is written only in the first line.

  As described above, by changing the input timing of the write data, the fourth line is selected and written after the first line in the previous frame (period B to period C), but in this frame, the fourth line is selected. The first line is selected and written after the line (period J to period K). Since the writing order of the black data is not changed from the previous frame, as shown in FIGS. 40 to 42, the image display time T2 ′ of the fourth line is 2H / second compared to the image display time T1 ′ of the first line. It will be 3 longer. Similarly, the other scanning lines have a time difference of 2H / 3 which is opposite to the previous frame in the display period of the two simultaneously selected scanning lines.

  By this method, the image display time (T1 + T1 ') of the first line and the image display time (T2 + T2') of the fourth line are equalized between frames, and the respective display time differences are cancelled. In addition, the difference in display time is similarly canceled for the other scanning lines.

  As described above, the sixth embodiment requires more memory than the above-described embodiments, but it is possible to eliminate the luminance difference due to the difference in display time due to simultaneous writing of black data. The same effect can be obtained even on panels with different numbers of output enable signals by changing the phase of the output enable signal and the input timing of the write pulses and changing the image writing order every several frames. It becomes.

  Next, the polarity control of the present invention will be described. As is well known to those skilled in the art, when a DC voltage is continuously applied to the liquid crystal material, the liquid crystal material deteriorates. In order to prevent this deterioration, it is necessary to periodically invert the polarity of the signal voltage applied to the liquid crystal material with respect to the common electrode voltage.

  The inversion operation here is performed in adjacent frames, adjacent scanning lines, and adjacent pixels. However, since the polarity of the signal line is determined by the polarity instruction signal with respect to the scanning line, Depending on the application method, the opposite polarity is not necessarily applied to adjacent scanning lines. For example, as is well known, there is a method of applying a reverse polarity to every two scanning lines.

  In the present invention, the polarity of the black data output from the source driver is inverted every time black data is output. In black, since a plurality of scanning lines are simultaneously selected and writing is performed, the polarities of voltages applied to the pixels of the simultaneously selected scanning lines are the same in the signal line direction. As for the polarity of the image data, the polarity instruction signal (POL_O) is inputted so that the polarity of each scanning line becomes the same even when the image is written with respect to the scanning line having the same polarity when black is simultaneously selected. In other words, the number of scanning lines where the polarity inversion of black is performed is the same as the number of scanning lines where the polarity inversion of images is performed.

  A specific polarity control method according to the present invention will be described below with reference to FIGS. 25 to 27 of the first embodiment and FIGS. 34 to 36 of the fourth embodiment. The polarity of the voltage with respect to the common voltage output from each signal line is determined by the polarity instruction signal (POL_O) input to the source driver. For example, when the polarity instruction signal (POL_O) is “H”, the polarity of the voltage output from the signal line is positive, negative, positive, negative,... For each signal line. Are output as negative / positive / negative / positive ... for each signal line. “+” And “−” shown in FIGS. 25 to 27 and FIGS. 34 to 36 represent “H” and “L” of the polarity instruction signal (POL_O) given to these source drivers, respectively. Shall.

  In the first embodiment, as is clear from FIGS. 25 to 27, black is simultaneously written for every two scanning lines such as the first line and the second line, the third line and the fourth line, and so on. Therefore, the polarities of these simultaneously written scanning lines are the same. Accordingly, the polarity instruction signal (POL_O) is “+” when writing black to the first line and the second line, “−” when writing black to the third line and the fourth line, and the fifth line and the second line. When writing black to 6 lines, it is set to “+”, and the polarity is inverted every time black data is written. As a result, the polarity of black data writing is reversed every two scanning lines. In the next frame, the polarity instruction signal (POL_O) is “−” when writing black to the first line and the second line, “+” when writing black to the third line and the fourth line, When writing black on the fifth line and the sixth line, it is set to “−”, and the polarity is inverted in the adjacent frame.

  The polarity of the image is “+” for the first line and the second line so that the polarity of each scanning line is the same when writing the image to the scanning line having the same polarity when black is simultaneously selected. The polarity inversion is performed for every two scanning lines so that the third line and the fourth line are “−”, and the fifth line and the sixth line are “+”.

  In the fourth embodiment, unlike the first embodiment, after black is written in the second line as shown in FIGS. 34 to 36, the first line and the fourth line, the third line and the sixth line, Black is simultaneously written for every two scanning lines such as the fifth line, the eighth line,..., And the polarities of these simultaneously written scanning lines are the same. Accordingly, the polarity instruction signal (POL_O) is “+” when writing black to the second line, “−” when writing black to the first line and the fourth line, and to the third line and the sixth line. “+” Is written when black is written, and “−” is written when black is written on the fifth and eighth lines, and the polarity is inverted every time black data is written. As a result, the polarity of black data writing is reversed every two scanning lines. However, when black data is written to the second line, only one scanning line is inputted to the gate driver, so that the polarity is inverted after one scanning line.

  In the next frame, the polarity instruction signal (POL_O) is “−” when writing black on the second line, “+” when writing black on the first line and the fourth line, and the third line. When black is written in the sixth line, “−” is set, and when black is written in the fifth line and the eighth line, “+” is set, and the polarity is inverted in the adjacent frame.

  The polarity of the image is “+” for the second line so that the polarity of each scanning line is the same when writing the image with respect to the scanning line having the same polarity when black is simultaneously selected. The polarity instruction signal (POL_O) is input so that the line and the fourth line are “−”, the third line and the sixth line are “+”, and the fifth line and the eighth line are “−”. As described above, since the polarity of black is inverted every two scanning lines, the polarity of the image is also inverted every two lines (however, the second line is one), and the black polarity is adjacent as well. Polarity inversion is also performed in the frame.

  Further, in the case of four output enable signals increased from the fourth embodiment, after black is written in the second line, the first line, the third line, the fifth line, the fourth line, the sixth line, Black is simultaneously written for every three scanning lines, such as the eighth line, the seventh line, the ninth line, the eleventh line, etc., and the polarities of these simultaneously written scanning lines are the same. As a result, since the polarity of black data writing is inverted for each scanning line, the polarity of the image is also inverted for each scanning line.

  Also, in this example, when the polarity of black is “+”, the polarity of the image is also the same as that of “+” in the same frame, but when the polarity of black is “+” The polarity of black and image may be made different in the same frame so that the polarity is “−”.

  As is clear from the description of the above embodiments, according to the present invention, it is possible to achieve a pseudo impulse by applying a black insertion technique while minimizing a decrease in contrast and deterioration in image quality, and also achieving black insertion. It is possible to secure a wide degree of freedom in setting the rate and to easily apply it to hold-type display panels having various device structures. As a result of experiments by the present inventors, the blurring of moving images is remarkably generated in a 15-inch type XGA (1024 × 768) TN type liquid crystal module by introducing pseudo impulse generation by the black insertion technique using the group-by-group output enable of the present invention. It was confirmed that it was improved. Those skilled in the art will readily understand that similar effects can be obtained in other liquid crystal modes (IPS, MVA, OCB).

  In the video timing control unit 10 shown in FIG. 1, the scaler 11, the timing controller 12, and the black insertion circuit 13 are configured as separate semiconductor devices. This is an example of the device configuration. Not too much. Another example (part 1) of the video timing control unit 10 is shown in FIG. In this example, the scaler 11 is configured as an independent device, but the black insertion circuit 13 is built in a device constituting the timing controller 12. Another example (part 2) of the video timing control unit 10 is shown in FIG. In this example, the black insertion circuit 13 is configured as an independent device, but the timing controller 12 is built in a device constituting the scaler 11. Another example (part 3) of the video timing control unit 10 is shown in FIG. In this example, the black insertion circuit 13 is built in the device constituting the scaler together with the timing controller 12.

  Various forms of commercial use of the apparatus of the present invention can be employed. For example, if selling as a package IC, (1) when only the black insertion circuit 13 is made into one chip, (2) when making the black insertion circuit 13 and the timing controller 12 into one chip, (3) black insertion When the circuit 13, the timing controller 12, and the scaler 11 are made into one chip, various product forms such as the above can be considered.

  Further, if a package IC is manufactured on the customer side, an IP core (for example, a black insertion circuit, a timing controller, a scaler, etc.) that is a main part of the present invention is provided to the customer as source code. Here, the source code is a description of these circuits in a hardware description language (VHDL, Verilog, C, etc.). For example, a black insertion circuit and timing controller may be provided to the customer as source code, and the customer may use a method of developing the scaler unit independently and converting it into a single chip, and putting both into a single chip. it can. In this case, on the customer side, “logic synthesis” processing is performed by a computer having a compiler function based on the source code of the black insertion circuit and timing controller and the source code of the scaler unit designed by the customer. Based on the information (generally referred to as “net list”), a “place and route” process is performed to produce a target chip. Here, “logic synthesis” means that source code described in a hardware description language is converted into a logical expression and logically compressed, and expanded into a group of circuit elements such as AND, OR, and latch. Specifically, it means compiling those source codes using a library specific to a semiconductor manufacturer. Further, “placement and wiring” means that where circuit element information obtained by logic synthesis is arranged on an actual chip and how a wiring path is to be determined.

  According to the present invention, every time (M-1) pieces of image data are written into (M-1) horizontal pixel columns, black data is simultaneously applied to (M-1) horizontal pixel columns different from them. Is written, the hold type display panel can be pseudo-impulsed and the black insertion rate can be changed in units of M (M-1) H. While achieving this, it is possible to avoid a decrease in contrast and image quality as much as possible, and to secure a wide degree of freedom in setting the black insertion rate, facilitating application to display panels having various device structures. be able to.

It is a block diagram which shows the whole structure of this invention apparatus. It is an equivalent circuit diagram of a Cs on Common type liquid crystal display panel. It is an equivalent circuit diagram of a Cs on Gate type liquid crystal display panel. It is a block diagram which shows the detail of a black insertion circuit. It is a block diagram which shows the detail of a data generation circuit. It is a block diagram which shows the detail of a horizontal direction control circuit. It is a block diagram which shows the detail of a FIFO_WE production | generation circuit. It is a block diagram which shows the detail of a STH generation circuit. It is a block diagram which shows the detail of a horizontal counter. It is a block diagram which shows the detail of a LP_bit generation circuit. It is a block diagram which shows the detail of a POL_bit production | generation circuit. It is a block diagram which shows the detail of a vertical direction control circuit. It is a block diagram which shows the detail of an edge detection circuit. It is a block diagram which shows the detail of a dot counter. It is a block diagram which shows the detail of a CPV_bit production | generation circuit. It is a block diagram which shows the detail of a STV_bit production | generation circuit. It is a block diagram which shows the detail of an OE production | generation circuit. It is a block diagram (the 1) which shows another example of a video | video timing processing block. It is a block diagram (the 2) which shows another example of a video | video timing processing block. FIG. 12 is a block diagram (part 3) illustrating another example of the video / timing processing block. It is a state transition diagram (1st state) which shows operation | movement of the gate driver of this invention. It is a state transition diagram (2nd state) which shows operation | movement of the gate driver of this invention. It is a state transition diagram (3rd state) which shows operation | movement of the gate driver of this invention. It is a state transition diagram (4th state) which shows operation | movement of the gate driver of this invention. It is a time chart (the 1) which shows operation | movement of the source driver and gate driver in 1st Example. It is a time chart (the 2) which shows operation | movement of the source driver and gate driver in 1st Example. It is a time chart (the 3) which shows operation | movement of the source driver and gate driver in 1st Example. It is a time chart (the 1) which shows operation | movement of the source driver and gate driver in 2nd Example. It is a time chart (the 2) which shows operation | movement of the source driver and gate driver in 2nd Example. It is a time chart (the 3) which shows operation | movement of the source driver and gate driver in 2nd Example. It is a time chart (the 1) which shows operation | movement of the source driver and gate driver in 3rd Example. It is a time chart (the 2) which shows operation | movement of the source driver and gate driver in 3rd Example. It is a time chart (the 3) which shows operation | movement of the source driver and gate driver in 3rd Example. It is a time chart (the 1) which shows operation | movement of the source driver in 4th Example, and a gate driver. It is a time chart (the 2) which shows operation | movement of the source driver and gate driver in 4th Example. It is a time chart (the 3) which shows operation | movement of the source driver and gate driver in 4th Example. It is a time chart (the 1) which shows operation | movement of the source driver and gate driver in 5th Example. It is a time chart (the 2) which shows operation | movement of the source driver and gate driver in 5th Example. It is a time chart (the 3) which shows operation | movement of the source driver and gate driver in 5th Example. It is a chart (the 1) which shows operation | movement of the source driver and gate driver in 6th Example. It is a chart (the 2) which shows operation | movement of the source driver and gate driver in 6th Example. It is a chart (the 3) which shows the operation | movement of the source driver and gate driver in 6th Example. It is a time chart which shows operation | movement of each signal of an STH generation circuit. It is a state transition diagram (1st state) which shows operation | movement of the conventional gate driver. It is a state transition diagram (2nd state) which shows operation | movement of the conventional gate driver. It is a state transition diagram (3rd state) which shows operation | movement of the conventional gate driver. It is a state transition diagram (4th state) which shows operation | movement of the conventional gate driver.

Explanation of symbols

1 Liquid crystal panel 2 Scan line 3 Signal line 4 TFT
5 Liquid Crystal Capacitance 6 Storage Capacitance 7 Common Electrode 8 Source Driver 9 Gate Driver 10 Video / Timing Controller 11 Scaler 12 Timing Controller 13 Black Insertion Circuit 131 PLL
132 Data Generation Circuit 133 Horizontal Control Circuit 134 Vertical Control Circuit 135 Timing Adjustment Circuit 91 Shift Register Device 92 Shift Register Device 93 Shift Register Device 911 Shift Register Element 921 Shift Register Element 931 Shift Register Element

Claims (8)

A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines;
A source driver that outputs display data to each vertical signal line of the hold-type display panel;
A gate driver that outputs a scanning signal to a horizontal scanning line selected from the horizontal scanning lines of the hold-type display panel;
And a video / timing control unit,
The gate driver
A scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages;
An output enable gate provided on each of the parallel output lines of the scanning shift register and opening / closing a scanning signal to each horizontal scanning line of the display panel, and the output enable gates are {kM + 1} -th, {KM + 2} -th,... {KM + M} -th (where k is an integer of 0, 1, 2,..., M is an integer of 3 or more) each of M groups These output enable gates can be collectively opened and closed in units of groups in response to control signals given to each group from the outside.
The video / timing control unit
For every period corresponding to (M−1) horizontal scanning periods (H) of the video signal, (M−1) image data and one black data are output from the source driver to the vertical signal line. Vertical direction control means for controlling the output of the display data from the source driver to the vertical signal line,
The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively fetched into the first stage of the shift register at a predetermined timing, and are perpendicular to the source driver. The shift register is controlled so that it is shifted in accordance with the output of display data to the signal line, and when image data is output from the source driver to the vertical signal line, scanning for writing image data is performed. When the black data is output from the source driver to the vertical signal line so that only the scanning signal generated by the line selection data is output to the corresponding horizontal scanning line, black for (M-1) lines. The output enable signal is output for each group so that only the scanning signal generated by the scanning line selection data for data writing is simultaneously output to the corresponding horizontal scanning line. Horizontal direction control means for controlling the opening and closing of the gate,
Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. Thus, the hold type display panel is realized by realizing pseudo impulse of the hold type display panel and changing the black insertion rate in M (M-1) H units.   The scanning shift register is formed by connecting a plurality of shift register devices having the same configuration in series, and the output enable control terminal for each group derived from each shift register device is output enabled at the serial connection position of the shift register devices. 2. The hold-type display device according to claim 1, wherein the hold-type display devices are interconnected so that continuity of the group order of the gates is maintained. The hold type display panel is a TFT- on-gate type TFT liquid crystal display panel, and (M-1) horizontal pixel columns to which black data is simultaneously written are separated from each other by one or more horizontal pixel columns. The hold-type display device according to claim 1, wherein the hold-type display device is in a relation.   (M-1) The hold type display device according to any one of claims 1 to 3, wherein the writing order of image data for each of the horizontal pixel columns is changed for each frame. Drive control adapted to a hold type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines A device,
A source driver that outputs display data to each vertical signal line of the hold-type display panel;
A gate driver that outputs a scanning signal to a horizontal scanning line selected from the horizontal scanning lines of the hold-type display panel;
And a video / timing control unit,
The gate driver
A scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages;
An output enable gate provided on each of the parallel output lines of the scanning shift register and opening / closing a scanning signal to each horizontal scanning line of the display panel, and the output enable gates are {kM + 1} -th, {KM + 2} -th,... {KM + M} -th (where k is an integer of 0, 1, 2,..., M is an integer of 3 or more) each of M groups These output enable gates can be collectively opened and closed in units of groups in response to control signals given to each group from the outside.
The video / timing control unit
For every period corresponding to (M−1) horizontal scanning periods (H) of the video signal, (M−1) image data and one black data are output from the source driver to the vertical signal line. Vertical direction control means for controlling the output of the display data from the source driver to the vertical signal line,
The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively fetched into the first stage of the shift register at a predetermined timing, and are perpendicular to the source driver. The shift register is controlled so that it is shifted in accordance with the output of display data to the signal line, and when image data is output from the source driver to the vertical signal line, scanning for writing image data is performed. When the black data is output from the source driver to the vertical signal line so that only the scanning signal generated by the line selection data is output to the corresponding horizontal scanning line, black for (M-1) lines. The output enable signal is output for each group so that only the scanning signal generated by the scanning line selection data for data writing is output simultaneously to the corresponding horizontal scanning line. Horizontal direction control means for controlling the opening and closing of the gate,
Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. Thus, the hold-type display panel drive control apparatus is characterized in that the pseudo-impulse of the hold-type display panel is realized and the black insertion rate can be changed in units of M (M−1) H. A hold-type display panel having a plurality of vertical signal lines, a plurality of horizontal scanning lines, and a pixel with a switch arranged corresponding to each intersection of the vertical signal lines and the horizontal scanning lines;
A source driver that outputs display data to each vertical signal line of the hold-type display panel;
A gate driver that outputs a scanning signal to a horizontal scanning line selected from the horizontal scanning lines of the hold-type display panel is integrated,
The gate driver
A scanning shift register in which scanning line selection data for generating scanning signals is sequentially shifted in a serial direction on a series of stages;
An output enable gate provided on each of the parallel output lines of the scanning shift register and opening / closing a scanning signal to each horizontal scanning line of the display panel, and the output enable gates are {kM + 1} -th, {KM + 2} -th,... {KM + M} -th (where k is an integer of 0, 1, 2,..., M is an integer of 3 or more) each of M groups These output enable gates are video / timing control devices suitable for a display panel with a driver that can be opened / closed in groups in response to control signals given to each group from the outside. ,
For each period corresponding to (M-1) horizontal scanning periods (H) of the video signal, (M-1) image data and one black data are output from the source driver to the vertical signal line. Vertical direction control means for controlling the output of the display data from the source driver to the vertical signal line,
The scanning line selection data for writing image data and the scanning line selection data for (M-1) lines for writing black data are respectively fetched into the first stage of the shift register at a predetermined timing, and are perpendicular to the source driver. The shift register is controlled so that it is shifted in accordance with the output of display data to the signal line, and when image data is output from the source driver to the vertical signal line, scanning for writing image data is performed. When the black data is output from the source driver to the vertical signal line so that only the scanning signal generated by the line selection data is output to the corresponding horizontal scanning line, black for (M-1) lines. The output enable signal is output for each group so that only the scanning signal generated by the scanning line selection data for data writing is simultaneously output to the corresponding horizontal scanning line. Horizontal direction control means for controlling the opening and closing of the gate,
Thus, every time (M-1) image data is written to (M-1) horizontal pixel columns, black data is simultaneously written to (M-1) horizontal pixel columns different from them. Thus, the video / timing control device for a display panel with a driver, which realizes pseudo impulse of the hold type display panel and allows the black insertion rate to be changed in units of M (M-1) H. 7. An FPGA, ASIC, or ASSP functioning as a vertical direction control means and a horizontal direction control means constituting the video / timing control device for a display panel with a driver according to claim 6 .   8. A record in which source code to be read by a computer having a compiler function for generating and outputting a netlist essential for producing the FPGA, ASIC, or ASSP according to claim 7 is recorded in a format readable by the computer. Medium.

Images