JP3488107B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix array in which a switching element is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, and the signal lines. The present invention relates to an active matrix type liquid crystal display device including a horizontal drive circuit for driving the liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a liquid crystal display device which can be applied to personal computers, workstations, televisions, etc. having different image frequencies, numbers of pixels and scanning methods.

In order to support the above-mentioned personal computer or work station, it is necessary to perform a sequential scanning method in which scanning is performed in order regardless of whether odd lines or even lines.

On the other hand, in order to support current television and high-definition television, it is necessary to perform interlaced driving in which odd-numbered line pixels are sequentially scanned in an odd-numbered field while even-numbered line pixels are sequentially scanned in an even-numbered field. .

Further, in the odd field, the next even line is scanned at the same time as the scanning of the odd line to write the same signal, while in the even field, the next odd line is simultaneously scanned at the same time as the scanning of the even line. Since two lines are simultaneously scanned by writing the same signal, a liquid crystal display device capable of coping with this is required.

Further, there is a demand for a liquid crystal display device capable of performing not only the scanning method but also enlarged display, black display writing and bidirectional scanning.

As such a liquid crystal display device, for example,
A liquid crystal display device disclosed in JP-A-8-122747 is disclosed. The conventional liquid crystal display device will be described below.

As shown in FIG. 20, the above liquid crystal display device includes an active matrix array 101 having thin film transistors arranged at intersections of scanning lines and signal lines,
It is composed of a vertical drive circuit 102 which drives the scanning lines and a horizontal drive circuit 103 which drives the signal lines. In the above liquid crystal display device, the number of scanning lines is 1024.

A vertical drive circuit 102 for the above liquid crystal display device.
Is a scanning circuit having a half-bit configuration of 256 stages (hereinafter, referred to as “half-bit configuration”, which sequentially shifts a pulse signal input from the input terminal a or the input terminal b in synchronization with a clock signal, as shown in FIG. "Scanning circuit") 10
4-1 to 104-257 and the output signals P1 ... of the half-bit configuration scanning circuits 104-1 to 104-257.
P2 ... P256 and control signals G1 G2 ... G8
NAND gate circuits 105-1 to 10 whose input signals are
5-1024 and those NAND gate circuits 105-1
The output buffer circuits 106 ... Each of which uses the respective output signals of 105 to 1024 as input signals.

In the above liquid crystal display device, four NAND gate circuits 105 ... Are connected to each output of the half bit configuration scanning circuits 104-1 to 104-257, and eight adjacent NAND gate circuits are provided. The control signals 105 ... Are all different.

Further, the half-bit configuration scanning circuit 1 described above is used.
Each of 04-1 to 104-257 has a configuration capable of bidirectional scanning. Therefore, the pulse signal is input from the input terminal a when scanning in one direction, while the pulse signal is input from the input terminal b when scanning in the opposite direction.

The above half-bit configuration scanning circuit 104-
1 to 104-257 use circuits driven by two-phase clock signals. Therefore, the number of drive signals required to drive the half-bit configuration scanning circuits 104-1 to 104-257 includes two clock signals and two input signals, including a pulse signal input when scanning in the reverse direction. Will be 4 in total. In addition, NAND gate circuits 105-1 to 105-1
The total number of drive signals input to the vertical drive circuit 102 is twelve, in addition to the respective control signals G1 to G8 of 05-1024. The number of these drive signals is equal to the number of signal lines.
Even if the number exceeds 024, it does not change.

A driving method in the above liquid crystal display device will be described.

As shown in FIG. 21, first, in the half-bit configuration scanning circuits 104-1 to 104-257, a clock signal CLK having a clock cycle of (8T) (T is a scanning line selection period) and the input terminal. The pulse width from a is (8
The input pulse signal VSTa of T) is input at the timing shown in the figure, and the input pulse signal VSTa is sequentially shifted in synchronization with the clock signal CLK.

As a result, the half-bit configuration scanning circuit 1
04-1 to 104-257 output signals P1 to P256
As shown in the figure, a pulse signal whose pulse width is (8T) and whose phase is sequentially shifted by (4T) is output.

On the other hand, the NAND gate circuit 105-1
To 105 to 1024, as control signals G1 to G8,
A pulse signal in which the pulse width is (T), the pulse period is (8T), and the phase is sequentially shifted by (T) is input at the timing shown in FIG. As a result, as the output signals GP1 to GP1024 of the output buffer circuit 106, pulse signals sequentially obtained by shifting the pulse width by (T) and the phase by (T) are obtained.

As described above, the signals for sequential scanning are extracted by the above driving method.

[0018]

However, in the above-described conventional liquid crystal display device and its driving method, the number of drive signals input to the vertical drive circuit 102 is only eight control signals. Need to create. Further, since eight wirings for routing these control signals from the input pad to the inside of the vertical drive circuit 102 are required,
The area required by these wirings becomes large, and the area required by the pads becomes large because input pads for inputting these control signals are formed on the substrate. Therefore, there is a problem that the glass substrate required for one liquid crystal display device becomes large and the number of the glass substrates becomes small when a plurality of liquid crystal panels are taken out from one substrate.

Further, there is a problem that an increase in the number of input pads also causes a decrease in yield when the pads are connected to an external flexible substrate.

The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a liquid crystal display device which has a small number of driving signals for operating the liquid crystal display device and which can improve yield. It is to provide the driving method.

[0021]

In order to solve the above-mentioned problems, a liquid crystal display device according to a first aspect of the present invention is an active device in which a switching element is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines. In a liquid crystal display device including a matrix array, a vertical drive circuit that drives the scanning lines, and a horizontal drive circuit that drives the signal lines, the vertical drive circuit clocks a pulse signal by inputting a start pulse. An N-stage (N is a positive integer) scanning circuit that sequentially shifts and outputs each half cycle of a signal, and each first control terminal is commonly connected for every M (M is an integer of 2 or more), An output signal from the N-stage scanning circuit is input to each of the commonly connected first control terminals, and (M
-1) (N * M) first first terminals to which second control terminals for inputting M second control signals are connected in common.
And a second logic gate circuit to which the output of the first logical gate circuit and one of the two types of third control signals are input from the third control terminal. It is characterized by

According to the above invention, the control signal inputted to the vertical drive circuit is the start pulse and the clock signal inputted to the first scanning circuit in the scanning circuit of N stages (N is a positive integer), and ( There are M kinds of second control signals input to the (N × M) first logic gate circuits and two kinds of third control signals input to the second logic gate circuits.

That is, in the prior art, since signals of different types were input to the first logic gate circuit at intervals of (2 × M−1), they are input to the first logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, each second control terminal in the first logic gate circuit is commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, since the wiring is distributed between the first logic gate circuit and the second logic gate circuit, it is possible to prevent the control lines from being concentrated.

That is, since the area of the drive circuit and the input pad can be reduced by reducing the number of control terminals, when a plurality of liquid crystal display devices are taken out from one glass substrate, the substrates are taken out. It is possible to increase the number of passengers for, and increase the number of non-defective panels.

Further, since the area of the drive circuit and the input pad is reduced, the frame area around the display portion of the liquid crystal display device is reduced, which facilitates incorporation into a personal computer or the like.

Further, by increasing the number of inputs from one stage in the scanning circuit to the logic gate circuit such that the output for one stage in the scanning circuit is input to a plurality of logic gate circuits, the number of stages in the scanning circuit is increased. Therefore, it is difficult to lay out one scanning circuit at the small pixel pitch, especially in a high-definition liquid crystal display device, but in the present invention, the layout becomes easy.

As a result, it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In order to solve the above-mentioned problems, the liquid crystal display device according to a second aspect of the present invention includes an active matrix array in which switching elements are arranged at respective intersections of a plurality of scanning lines and a plurality of signal lines, and the above scanning. In a liquid crystal display device including a vertical drive circuit that drives a line and a horizontal drive circuit that drives the signal line, the vertical drive circuit inputs a start pulse to generate a pulse signal for each half cycle of a clock signal. Scanning circuits of N stages (N is a positive integer) for sequentially shifting and outputting, pulse width shortening means for reducing the pulse width of the output pulse of each scanning circuit and outputting the M pulses (M is 2 or more). Each of the first control terminals is commonly connected for each (integer), and the output signal from each of the pulse width shortening means is input to each of the commonly connected first control terminals, and (M− ) Each of the second control terminal for inputting M types of signals to individual intervals is characterized by comprising a logic gate circuit of the common-connected (N × M) pieces of third.

According to the above invention, the control signal input to the vertical drive circuit is the start pulse and the clock signal input to the first scanning circuit in the scanning circuit of N stages (N is a positive integer), and It becomes M kinds of second control signals input to the (N × M) third logic gate circuits.

That is, in the prior art, since the signals of different types are input to the third logic gate circuit every (2 × M−1), the signals are input to the third logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, each second control terminal in the third logic gate circuit is commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, the wiring is provided with each pulse width shortening means and the third wiring.
The control lines can be prevented from being concentrated because they are distributed to the logic gate circuits.

As a result, it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In order to solve the above-mentioned problems, the liquid crystal display device according to a third aspect of the present invention is the liquid crystal display device according to the second aspect, wherein the pulse width shortening means has adjacent outputs in the scanning circuits of N stages. It is characterized by comprising a fourth logic gate circuit to which a pulse is inputted.

According to the above-mentioned invention, as the concrete pulse width shortening means, the wiring is constituted by the fourth logic gate circuit to which the adjacent output pulses in the N-stage scanning circuits are inputted. 4 logic gate circuits and a third logic gate circuit.

As a result, it is possible to provide a liquid crystal display device in which the control lines are prevented from concentrating and the number of drive signals for operating the liquid crystal display device is surely reduced and the yield can be improved. .

In order to solve the above-mentioned problems, the liquid crystal display device according to a fourth aspect of the present invention is the liquid crystal display device according to the third aspect, wherein the pulse width shortening means includes a front stage or a front stage in the N-stage scanning circuit. It is characterized in that a spare scanning circuit is provided in the subsequent stage.

According to the above invention, since the pulse width shortening means is provided with the spare scanning circuit at the front stage or the rear stage of the N-stage scanning circuit, the adjacent output pulses in the N-stage scanning circuit are supplied. It can be taken out reliably.

In order to solve the above problems, a liquid crystal display device according to a fifth aspect of the present invention is the liquid crystal display device according to the second aspect, wherein the pulse width shortening means is an output pulse in the scanning circuit of N stages. , A fifth logic gate circuit to which any one of the two types of fourth control signals consisting of the forward and reverse pulses is input.

According to the above invention, as a concrete pulse width shortening means, an output pulse in an N-stage scanning circuit,
7. A clock signal and an inverted clock signal as set forth in claim 6, comprising a fifth logic gate circuit to which any one of two types of fourth control signals consisting of forward and reverse pulses is inputted. Since the signal can be used as two kinds of fourth control signals consisting of forward and reverse pulses, surely
It is possible to provide a liquid crystal display device that has a small number of drive signals for operating the liquid crystal display device and can improve yield.

In order to solve the above problems, the liquid crystal display device according to a sixth aspect of the present invention is the liquid crystal display device according to the first or fifth aspect, wherein the third control signal or the fourth control signal is a clock. It is characterized by comprising a signal and an inverted clock signal.

That is, the third control signal or the fourth control signal is a positive / periodic (2 × M × T) and pulse width (M × T) signal.
Two types of signals composed of reverse pulses are required.

Here, these two types of signals are the same as the existing clock signal and inverted clock signal.

Therefore, in the present invention, the third control signal or the fourth control signal is composed of the clock signal and the inverted clock signal, whereby the third control signal and the fourth control signal are obtained.
It is not necessary to input a new control line to the vertical drive circuit as the control signal.

As a result, in the conventional case, the number of control lines input to the vertical drive circuit is increased, the area of the input pad is increased, and furthermore, it is necessary to lay out the wires for the number of control lines. Although there is a problem that the area required for the circuit layout becomes large, this can be prevented by using the existing control line.

Therefore, it is possible to provide a liquid crystal display device which has a small number of drive signals for operating the liquid crystal display device and which can improve the yield.

In order to solve the above problems, a liquid crystal display device according to a seventh aspect of the present invention is the liquid crystal display device according to any one of the first to sixth aspects, wherein M = 4. I am trying.

That is, in a high-definition liquid crystal display device,
It is difficult to lay out one scanning circuit with the small pixel pitch.

Therefore, the number of stages of the scanning circuit is increased by increasing the number of inputs to the logic gate circuit from one stage in the scanning circuit such that the output of one stage in the scanning circuit is input to a plurality of logic gate circuits. Can be reduced.

In the present invention, particularly when M = 4,
Since the number of inputs to the logic gate circuit is 4, the layout for one stage of the scanning circuit can be performed at a pitch of 4 pixels, and the layout can be easily performed.

As a result, it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In order to solve the above-mentioned problems, a liquid crystal display device according to an eighth aspect of the present invention includes an active matrix array in which switching elements are arranged at respective intersections of a plurality of scanning lines and a plurality of signal lines, and the above scanning. In a liquid crystal display device including a vertical drive circuit that drives a line and a horizontal drive circuit that drives the signal line, the vertical drive circuit inputs a start pulse to generate a pulse signal for each half cycle of a clock signal. The scanning circuits of 2 × N stages (N is a positive integer) for sequentially shifting and outputting, and the first control terminals for each M (M is an integer of 2 or more) are commonly connected, and these are commonly connected. Further, the output signals of every other stage from the scanning circuit of 2 × N stages are input to each of the first control terminals, and
(N × M) sixth logic gate circuits to which second control terminals for inputting M types of second control signals every (M−1) are commonly connected. It is characterized by that.

According to the above invention, the control signal inputted to the vertical drive circuit is the start pulse and the clock signal inputted to the first scanning circuit in the scanning circuit of 2 × N stages (N is a positive integer). , (N × M) sixth logic gate circuits, which are M kinds of second control signals.

That is, in the conventional case, since every 6th logic gate circuit receives different (2 × M-1) different kinds of signals, it is inputted to the 6th logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, each second control terminal in the sixth logic gate circuit is commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

As a result, it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In order to solve the above problems, a liquid crystal display device driving method according to a ninth aspect of the present invention is the liquid crystal display device driving method according to the first aspect, in which the scanning circuit in the vertical driving circuit comprises: By inputting a start pulse having a pulse width of (2 × M × T) with the scanning line selection period being T, a half cycle is sequentially shifted using a clock signal having a period of (2 × M × T). Generated signals and then sequentially shifted by the above half cycle, and M kinds of second control signals which output pulses having a pulse width (T) and a period of (M × T). Is input to the first control terminal and the second control terminal of each first logic gate circuit, and from each of these first logic gate circuits, each pulse width is (T) and the phase is ( (M-1) x T)
Two pulses separated from each other are generated, and next, the above-mentioned two pulses and two kinds of third pulses each consisting of a forward / reverse pulse having a period (2 × M × T) and a pulse width (M × T). Any one of the control signals is input to the second logic gate circuit to output a pulse width (T) signal from each of the second logic gate circuits, and the pulse width (T) signal is sequentially scanned. Characterized by entering in a line.

According to the above invention, when the start pulse is input to the scanning circuit of N stages in the vertical drive circuit,
Each scanning circuit outputs a pulse signal sequentially shifted by a half cycle of a clock signal having a cycle of (2 × M × T).

These pulse signals are (N × M) first
Is input to each first control terminal of the logic gate circuit.

In the (N.times.M) first logic gate circuits, the first control terminals are commonly connected every M, so that the pulse signals from the respective scanning circuits are M respectively.
Are input to the first logic gate circuits.

Further, to each of the first logic gate circuits, M types of second control signals are input from the second control terminal at intervals of (M-1) as other inputs. Each second
The control signal of 1 is composed of pulses having a pulse width (T) with a period of (M × T).

As a result, in each of the first logic gate circuits, the pulse width is (T) and the phases are ((M-
1) × T) Generate two pulses separated.

Next, the two pulses and the period (2 × M ×
T) and consists of forward and reverse pulses of pulse width (M × T) 2
When any one of the third control signals of the type is input to the second logic gate circuit, a signal having a pulse width (T) is output from each second logic gate circuit.

Therefore, by sequentially inputting signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit are combined to turn ON / OFF the switching elements of the active matrix array. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, since signals of different types are input to the first logic gate circuit every (2 × M−1), the signals are input to the first logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, each second control terminal in the first logic gate circuit is commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, since the wiring is distributed in the first logic gate circuit and the second logic gate circuit, it is possible to prevent the control lines from being concentrated.

As a result, it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can realize an improvement in yield.

In order to solve the above-mentioned problems, a liquid crystal display device driving method according to a tenth aspect of the present invention is the liquid crystal display device driving method according to the second aspect, wherein the scanning circuit in the vertical driving circuit comprises: By inputting a start pulse having a pulse width of (2 × M × T) with the scanning line selection period being T, a half cycle is sequentially shifted using a clock signal having a period of (2 × M × T). Generated signals, and then the signals sequentially shifted by the half cycle are input to the pulse width shortening means to generate pulses of pulse width (M × T) respectively, and the output from the pulse width shortening means is generated. , A second control signal of M kinds which outputs a pulse having a pulse width (T) and a period of (M × T), and a first control terminal and a second control terminal in each sixth logic gate circuit. Type in each of these Of each pulse width from the logic gate circuit generates the signals (T), is characterized in that input to the sequential scanning line signals of the pulse width (T).

According to the above invention, when the start pulse is input to the scanning circuit of N stages in the vertical drive circuit,
Each scanning circuit outputs a pulse signal sequentially shifted by a half cycle of a clock signal having a cycle of (2 × M × T).

These pulse signals are input to the pulse width shortening means, and the pulse width shortening means reduces the pulse width of the output pulse to generate pulses of pulse width (M × T).

The output of these pulse width shortening means is (N ×
It is input to each of the first control terminals of the M) third logic gate circuits.

Here, in the (N × M) third logic gate circuit, since the first control terminals are commonly connected for every M, the pulse signals from the pulse width shortening means are: It is input to M third logic gate circuits.

Further, to the respective third logic gate circuits, M types of second control signals are input from the second control terminal every (M-1) pieces as other inputs. Each second
The control signal of 1 is composed of pulses having a pulse width (T) with a period of (M × T).

As a result, a pulse width (T) signal is output from each of the third logic gate circuits.

Therefore, by sequentially inputting signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit are combined to turn ON / OFF the switching elements of the active matrix array. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, since signals of different types are input to the third logic gate circuit at intervals of (2 × M−1), they are input to the third logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, by providing the pulse width shortening means for reducing the pulse width of the output pulse of each scanning circuit and outputting it, each second control terminal in the third logic gate circuit is connected to (M -1) It becomes possible to make common connection for every two pieces. Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, the wiring is composed of the pulse width shortening means and the third wiring.
The control lines can be prevented from being concentrated because they are distributed to the logic gate circuits.

As a result, it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can realize an improvement in yield.

In order to solve the above-mentioned problems, a liquid crystal display device driving method according to an eleventh aspect of the present invention is the liquid crystal display device driving method according to the eighth aspect, wherein the scanning circuit in the vertical driving circuit comprises: By inputting a start pulse having a pulse width of (M × T) with the scanning line selection period being T, signals sequentially shifted by a half period using a clock signal having a period of (M × T), respectively. Then, each output signal sequentially generated for every one cycle extracted every other stage from the scanning circuit of the above 2 × N stages and the cycle is (M ×
T) and M types of second control signals for outputting pulses having a pulse width (T) are input to the first control terminal and the second control terminal of each sixth logic gate circuit,
Each pulse width is (T) from each of these sixth logic gate circuits.
Is generated and the signals having the pulse width (T) are sequentially input to the scanning lines.

According to the above invention, when a start pulse having a pulse width of (M × T) is input to the scanning circuit of 2 × N stages in the vertical driving circuit, the period from each scanning circuit is (M
The pulse signals sequentially shifted by half a cycle of the clock signal (XT) are output. Therefore, the above 2
The output signals extracted from every other stage from the scanning circuit of × N stages are sequentially shifted by one cycle.

These pulse signals are (N × M) sixth signals.
Is input to each first control terminal of the logic gate circuit.

Here, in the (N × M) sixth logic gate circuit, since the first control terminals are commonly connected for every M pieces, the pulse signals from the scanning circuits at every other stage are transmitted. , Each of which is input to the M sixth logic gate circuits.

Further, to each of the sixth logic gate circuits, M types of second control signals are input from the second control terminal at intervals of (M-1) as other inputs. Each second
The control signal of 1 is composed of pulses having a pulse width (T) with a period of (M × T).

As a result, a pulse width (T) signal is output from each of the sixth logic gate circuits.

Therefore, by sequentially inputting signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit are combined to turn ON / OFF the switching elements of the active matrix array. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, since every 6th logic gate circuit receives different (2 × M-1) signals of different types, it is inputted to the 6th logic gate circuit. At least (2 × M) control lines were required. For this reason, the number of control lines input to the vertical drive circuit increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout is reduced. There was a problem that it would grow.

However, in the present invention, the scanning circuit for sequentially shifting and outputting the pulse signal by the half cycle of the clock signal by inputting the start pulse is provided in 2 × N stages (N is a positive integer), and , Take out the output signal 2
The output signals are sequentially shifted by one cycle by carrying out every other stage in the scanning circuit of × N stages. As a result, it becomes possible to commonly connect every second control terminal in the sixth logic gate circuit every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Therefore, it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve the yield.

In order to solve the above problems, a liquid crystal display device driving method according to a twelfth aspect of the present invention is the liquid crystal display device driving method according to the first aspect, wherein the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. Then, the signal sequentially shifted by the above half cycle and (M
/ 2) control signals having a period of ((M / 2) × T) are input to the first logic gate circuit and the pulse width is (T) (((M / 2) -1 ) × T) two pulses apart from each other are generated from the first logic gate circuit, and the two pulses and a third control signal having a period of (M × T)
Of the pulse width (T), the signal having the pulse width (T) is output from the second logic gate circuit, and the signal having the pulse width (T) is sequentially input every other scanning line. .

According to the above invention, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

A pulse width (T) signal is sequentially input every other scanning line. Therefore, by using the liquid crystal display device according to the first aspect, it is possible to perform interlaced scanning in which every other scanning line is sequentially input.

In order to solve the above problems, a liquid crystal display device driving method according to a thirteenth aspect of the present invention is the liquid crystal display device driving method according to the first aspect, in which the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. Then, the signals sequentially shifted by the above half cycle and the M / 2 type control signals having a period of ((M / 2) × T) to the M type control terminals are input to the first logic gate circuit. Then, two pulses having a pulse width of (T) and separated by (((M / 2) -1) × T) are first
Of the two pulses and a third control signal having a period (M × T) are input to a second logic gate circuit, and a signal having a pulse width (T) is generated from the second logic gate circuit. The logic gate circuit outputs the signal of the pulse width (T) sequentially for every two scanning lines.

According to the above invention, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

Further, a signal having a pulse width (T) is sequentially input every two scanning lines. Therefore, by using the liquid crystal display device according to the first aspect, it is possible to perform two simultaneous scanning in which two scanning lines are sequentially input.

In order to solve the above-mentioned problems, a liquid crystal display device driving method according to a fourteenth aspect of the present invention is the liquid crystal display device driving method according to the second aspect, wherein the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. Then, the signals sequentially shifted by the half cycle are input to the pulse width shortening means to generate pulses of pulse width (M × T / 2) respectively, and the output from the pulse width shortening means and M A control signal having a period of (M × T / 2) is supplied to (M / 2) control terminals of the control terminals and the first control signal in each third logic gate circuit.
To the control terminal and the second control terminal of the pulse width (T), the pulse width (T) signal is output from the third logic gate circuit, and the pulse width (T) signal is sequentially input to every other scanning line. It is characterized by doing.

According to the above invention, the number of types of the second control terminals is M, which is half that of the conventional one. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

A pulse width (T) signal is sequentially input every other scanning line. Therefore, by using the liquid crystal display device according to the second aspect, it is possible to perform interlaced scanning in which every other scanning line is sequentially input.

In order to solve the above-mentioned problems, a liquid crystal display device driving method according to a fifteenth aspect of the present invention is the liquid crystal display device driving method according to the second aspect, wherein the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. Then, the signals sequentially shifted by the half cycle are input to the pulse width shortening means to generate pulses of pulse width (M × T / 2) respectively, and the output from the pulse width shortening means and M The control terminal inputs M / 2 types of control signals having a cycle of (M × T / 2) to the first control terminal and the second control terminal of each third logic gate circuit, and outputs the pulse width. The signal of (T) is applied to the third logic gate. Is output from the circuit, is characterized in that sequentially inputs a signal of the pulse width (T) two by two scan lines.

According to the above invention, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

Further, a signal having a pulse width (T) is sequentially input every two scanning lines. Therefore, by using the liquid crystal display device according to the second aspect, it is possible to perform two simultaneous scanning in which two scanning lines are sequentially input.

In order to solve the above problems, a liquid crystal display device driving method according to a sixteenth aspect of the present invention is the liquid crystal display device driving method according to the eighth aspect, in which the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. , Then the above 2 × N
Each output signal sequentially shifted by one cycle extracted from every other stage from the scanning circuit of the stage and (M /
2) A control signal having a cycle of (M × T / 2) is input to the first control terminal and the second control terminal of each sixth logic gate circuit, and the pulse width ( The signal of T) is output from the sixth logic gate circuit,
It is characterized in that the signals of the pulse width (T) are sequentially input every other scanning line.

According to the above invention, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

A pulse width (T) signal is sequentially input every other scanning line. Therefore, by using the liquid crystal display device according to the eighth aspect, it is possible to perform interlaced scanning in which every other scanning line is sequentially input.

In order to solve the above-mentioned problems, a liquid crystal display device driving method according to a seventeenth aspect of the present invention is the liquid crystal display device driving method according to the eighth aspect, wherein the scanning circuit in the vertical driving circuit comprises: With the scanning line selection period as T, a start pulse with a pulse width of (M × T) is input, and a clock signal with a period of (M × T) is used to generate signals sequentially shifted by a half period. , Then the above 2 × N
Each output signal sequentially shifted by one cycle extracted from every other stage from the scanning circuit of stages and M / 2 types of control signals having a period of (M × T / 2) are provided to M control terminals. Each 6th
Input to the first control terminal and the second control terminal of the logic gate circuit, and the pulse width (T) signal is output from the sixth logic gate circuit.
It is characterized in that the signal of 2 is sequentially input every two scanning lines.

According to the above invention, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

Further, a signal having a pulse width (T) is sequentially input every two scanning lines. Therefore, by using the liquid crystal display device according to the eighth aspect, it is possible to perform two-line simultaneous scanning in which two scanning lines are sequentially input.

[0111]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. 1 to 3.
It is as follows.

The liquid crystal display device of this embodiment is an active matrix type liquid crystal display device, and as shown in FIG. 3, a thin film transistor as a switching element is arranged at the intersection of a scanning line and a signal line. Active matrix array 1 and horizontal drive circuit 2 for driving signal lines
And a vertical drive circuit 10 for driving the scanning lines. In this liquid crystal display device, the number of scanning lines is 1024, for example. However, the number is not necessarily limited to this.

Vertical drive circuit 10 of the above liquid crystal display device
As shown in FIG. 1, a scanning circuit having a half-bit configuration (hereinafter, referred to as a “half-bit configuration scanning circuit”) 11-1 that sequentially shifts a start pulse STa by half a pulse per stage in synchronization with a clock signal CLK. ~ 11-257
And these half bit configuration scanning circuits 11-1 to 11-
AND gate circuits 12-1 to 12-1024 as first logic gate circuits to which the output signals P1, P2, P3, ... P256 of 257 are output, and the outputs of these AND gate circuits 12-1 to 12-1024 GPP1 ・ GPP2
... NAND gate circuits 13-1 to 13-1024 forming a second logic gate circuit to which GPP1024 is input
And the NAND gate circuits 13-1 to 13-1024
Output signal GP1 · GP2 ... GP1
It is comprised from each output buffer circuit 14 which outputs 024. In this embodiment, each second logic gate circuit is configured by a combination of each of the NAND gate circuits 13-1 to 13-1024 and each of the output buffer circuits 14 ...

The half bit configuration scanning circuits 11-1 to 11-1
11-257 is 256 as N stages (N is a positive integer)
It consists of one step added to the step. The last one-stage half-bit configuration scanning circuit 11-257 has a function as a terminating device, and the output is not taken out.

Half-bit configuration scanning circuit 11-1 described above
A start pulse STa, a clock signal CLK, and its inverted clock signal / CLK are input to.

On the other hand, the AND gate circuits 12-1 to 12-1
Each of 2-1024 has a first terminal as an input terminal.
Control terminals and second control terminals are provided.

Each of the first control terminals is commonly connected, for example, every four pieces as M pieces (M is an integer of 2 or more), and each of the four pieces is commonly connected to the half bit. It is connected to each output terminal of the configuration scanning circuits 11-1 to 11-256. As a result, the AND gate circuit 12
−1 to 12-1024 include the output signals P1 and P2 ...
P256 is input to the first control terminal.

Also, AND gate circuits 12-1 to 12-
1024 is 256 × 4 = 102 as (N × M).
There are four. This allows the number of scan lines above 1
It corresponds to 024 lines.

Further, the AND gate circuit 12-1 described above.
Second control signals G1, G2, G3, and G4 input from the outside are input to the respective second control terminals 12 to 1024.
Are sequentially input.

That is, each AND gate circuit 12-1 to 12-12
In general, M-type signals are input to each second control terminal at −1024 at intervals of (M−1), and in the present embodiment, as M, for example, 4 signals are input.
The second control signals G1, G2, G3, and G4 are input every three (M-1). The second control signals G1, the second control signals G2, the second control signals G3, and the second control signals G4 are commonly connected to each other.

On the other hand, each of the above NAND gate circuits 13-1
13 to 1024 are connected to the AND gate circuit 12-1.
Output signals GPP1, GPP2 ... GP of 12-1024
P1024 is input and the third control signal PP1 is input.
-Any one of PP2 is input.

In the present embodiment, the third control signal P
P1 and PP2 are NAND gate circuits 13-1 to 13-
For 1024, every four data are input alternately. That is, the first four NAND gate circuits 13
The third control signal PP1 is input to −1 to 13-4, and the next four NAND gate circuits 13-5 to 13-8 are input.
A third control signal PP2 is input to. Further, the next four NAND gate circuits 13-9 to 13-12 are
The third control signal PP1 is input, and the next four N
The third control signal PP2 is input to the AND gate circuits 13-13 to 13-16. Similarly, the third control signals PP1 and PP2 are alternately input every four signals.

The above NAND gate circuits 13-1 to 13-13
Each output signal of −1024 is inverted by the output buffer circuit 14 and input to each scanning line as an output signal GP1 · GP2 ... GP1024.

That is, the feature of the vertical drive circuit 10 is that the NAND gate circuit 1 shown in FIG.
05-1 to 105-1024 are connected to the AND gate circuit 12
-1 to 12-1024 and NAND gate circuit 13-1 to
13-1024, the number of control signals to the AND gate circuits 12-1 to 12-1024 is halved. In the present embodiment, AND gate circuits 12-1 to 12-1024 and N
Although the AND gate circuits 13-1 to 13-1024 are used in combination, the present invention is not limited to this, and it is also possible to use circuits having the same functions as these circuits in combination. For example, the inverted pulse output from the half-bit configuration scanning circuits 11-1 to 11-256 and the inverted control signal may be input to the NOR gate circuit. Such a method is the same in other embodiments described later.

A driving method in the liquid crystal display device having the above structure will be described with reference to a timing chart in the case of sequential scanning shown in FIG. Incidentally, the above-mentioned sequential scanning means a method of sequentially scanning regardless of an odd line or an even line.

First, the half bit configuration scanning circuit 11
A start pulse STa having a pulse width (8T), a clock signal CLK having a period (8T), and its inverted clock signal / CLK are input to -1 to 11-257 with T being a scanning line selection period. As a result, the outputs P1 to P from the half bit configuration scanning circuits 11-1 to 11-257 are output.
256 occurs.

At this time, in the present embodiment, as the control signals input to the AND gate circuits 12-1 to 12-1024, as shown in the figure, the second control signals G1 to G4 are used.
4 signals are used. Therefore, the number of control signals is 1/2 that of the conventional one.

In the present embodiment, as shown in the figure, the pulses of the second control signals G1 to G4 are generated even in the blanking period immediately after the video signal writing period, but this is not always the case. However, the pulse need not be generated during the blanking period.

Thereafter, these AND gate circuits 12-1
The output GPP1 to GPP1024 of 12 to 1024 have two output pulses shown in FIG. These two output pulses are NAND gate circuits 13-1 to 13-13.
-Enter in 1024. At that time, the outputs of the odd-numbered half-bit configuration scanning circuits 11-1, 11-3, 11-5, ... Are connected to the NAND gate circuits 13-1 to 13-4.
While the third control signal PP1 is input to 13-9 to 13-12 ..., the outputs of the half-bit configuration scanning circuits 11-2, 11-4, 11-6, ... NAND gate circuits 13-5 to 13-8 and 13-13 to
The third control signal PP2 is input to 13-16 ...

The clock signal CLK input to the half-bit configuration scanning circuits 11-1 to 11-257 may be used as the third control signal PP1.
The inverted clock signal / CLK may be used as the control signal PP2. Therefore, it is not necessary to create a new control signal, and it is not necessary to newly create a signal input terminal from the outside.

In this way, the NAND gate circuits 13-1 to 13-1
The pulse widths of GP1 to GP1024 are (T) and the phases are sequentially shifted by (T) as an output signal from 13-1024 and an output signal from the output buffer circuit 14, thereby sequentially scanning the scanning lines. can do.

Output signals GP1, GP2 ... GP1024 from the vertical drive circuit 10 and the horizontal drive circuit 2
An ON / OFF signal is supplied to each thin film transistor provided at the intersection of the scanning line and the signal line in the active matrix array 1 by the signal of each signal line from the pixel array, and the screen of the liquid crystal display device displays each pixel. To be done.

As a result, since the number of control signals can be reduced, the liquid crystal display device can be downsized and the cost can be reduced.

As described above, in the liquid crystal display device and the driving method thereof according to the present embodiment, 25 in the vertical driving circuit 10 are provided.
6-stage half-bit configuration scanning circuits 11-1 to 11-25
When the start pulse STa is input to 7, the half-bit configuration scanning circuits 11-1 to 11-257 sequentially shift by half a cycle of the clock signal CLK having a cycle of (2 × 4 × T). Output signal P1, which is a pulse signal
P2, P3 ... P256 are output respectively.

These pulse signals are input to the respective first control terminals of the (256 × 4) AND gate circuits 12-1 to 12-1024.

In the (256.times.4) AND gate circuits 12-1 to 12-1024, the first control terminals are commonly connected to every four AND gate circuits, so that the half bit configuration scanning circuit 11 is used. The pulse signals from -1 to 11-257 are four AND gate circuits 12-1 to 12-, respectively.
4-12-5-12-8 ... 12-1021-12-10
24 is input.

Further, each AND gate circuit 12-1 to 12-12
As other inputs, four types of second control signals G1 to G4 are input to the −1024 from the second control terminal at intervals of three. Each of the second control signals G1 to G4 is a pulse having a period (4 × T) and a pulse width (T).

As a result, each AND gate circuit 1 described above is
2-1 to 12-1024 generate two pulses having a pulse width (T) and phases separated from each other by ((4-1) × T).

Next, the above two pulses and the period (2 × 4 ×
T) and consists of forward and reverse pulses of pulse width (4 × T) 2
When any one of the third type control signals PP1 and PP2 is input to the NAND gate circuits 13-1 to 13-1024, respectively.
A pulse width (T) signal is output from 13-1024 and the output buffer circuit 14.

Therefore, by sequentially inputting signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit 2 are combined to turn on / off the thin film transistors of the active matrix array 1. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, the NAND gate circuits 105-1 to 105-1024 (see FIG. 20) are
Since different types of signals are input every (2 × 4-1 = 7), NAND gate circuits 105-1 to 105
The control line input to −1024 is at least (2 × 4)
I needed one. For this reason, the number of control lines input to the vertical drive circuit 10 increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, and the area required for the circuit layout. However, there was a problem that

However, in this embodiment, the control signal input to the vertical drive circuit 10 is the start pulse STa, the clock signal CLK, and the inverted clock signal input to the first scan circuit half-bit configuration scan circuit 11-1. / C
LK and 256 × 4 = 1024 AND gate circuits 1
2-1 to 12-1024 four kinds of second control signals G1 to G4 and NAND gate circuits 13-1 to 13-1
2-type third control signal PP input to 3-1024
It becomes 1 · PP2. That is, the AND gate circuits 12-1 to 12-1
Each second control terminal in 12-1024 is (4-1
= 3) Every 3 pieces are commonly connected.

Therefore, the number of types of the second control terminals is four, which is half the conventional type.

The wiring is the AND gate circuit 12-1.
To 12-1024 and NAND gate circuits 13-1 to 13-13
-1024 so that the control lines can be prevented from being concentrated.

That is, the area of the vertical drive circuit 10 and the input pad can be reduced by reducing the number of control terminals. Therefore, in the case of so-called multi-cavity taking out a plurality of liquid crystal display devices from one glass substrate. In addition, the number of boards to be mounted on the board is increased, and the number of non-defective panels can be increased.

Further, since the area of the vertical drive circuit 10 and the input pad is reduced, the frame area around the display portion of the liquid crystal display device is reduced, and it is easy to incorporate into a personal computer or the like.

Further, the half bit configuration scanning circuit 11-
The output of one stage in each of 1 to 11-256 is provided with four AND gate circuits 12-1 to 12-4 and 12-5 to 1 respectively.
2-8 ... 12-1021 to 12-1024, so that the half-bit configuration scanning circuits 11-1 to 11-11
-256 AND gate circuit 12 from one stage
1 to 12-1024 by increasing the number of inputs to half-bit configuration scanning circuits 11-1 to 11-256.
Since it is possible to reduce the number of stages of the scanning lines from the required number of scanning lines of 1024, it is difficult to lay out the scanning circuits of 1024 stages with the small pixel pitch, especially in a high-definition liquid crystal display device. In the embodiment, the layout becomes easy.

In particular, in this embodiment, M = 4, and
Since the number of inputs to the AND gate circuits 12-1 to 12-1024 is set to 4, the layout of the half bit configuration scanning circuits 11-1 to 11-256 can be performed at a pitch of 4 pixels, Layout can be done easily.

As a result, it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In this embodiment, the clock signal CLK and the inverted clock signal / CLK are used as the third control signals PP1 and PP2. Therefore, it is not necessary to input a new control line to the vertical drive circuit 10 as the third control signals PP1 and PP2.

As a result, in the conventional case, the vertical drive circuit 1
The number of control lines input to 0 increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, which increases the area required for circuit layout. However, this can be prevented by using the existing control line.

Therefore, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

[Second Embodiment] The following will describe another embodiment of the present invention in reference to FIG. 4 and FIG. Incidentally, for convenience of explanation, regarding members having the same functions as the members shown in the drawings of the first embodiment,
The same reference numerals are given and the description thereof is omitted.

As shown in FIG. 4, the vertical drive circuit 20 of the liquid crystal display device of the present embodiment is a half-bit structure scanning circuit which sequentially shifts the start pulse STa by half a pulse per stage in synchronization with the clock signal CLK. 11-P.1
1-1 to 11-257 and respective output signals Q1 of the half-bit configuration scanning circuits 11-P and 11-1 to 11-256.
P1, P2, P3 ... P256 and their adjacent output signals Q1 and P1, P1 and P2, ..., P255 and P25
AN as fourth logic gate circuit with 6 as input signal
D gate circuits 21-1, 21-2 to 21-256 and these AND gate circuits 21-1, 21-2 to 21-25
NAND gate circuits 15-1 to 15-1024, which form a third logic gate circuit using the output signals GPP1, GPP2, ... GPP256 from 6 and the second control signals G1, G2, G3, G4 as input signals, The NAND gate circuits 15-1 to 15-1024 are composed of an output buffer circuit 14 which receives the output signals as input signals.

In this embodiment, the NAND gate circuits 15-1 to 15-1024 and the output buffer circuit 14 ...
A third logic gate circuit is configured by the combination with.

Further, each half-bit configuration scanning circuit 11-
1 to 11-257 have a function as a pulse width shortening means for reducing the pulse widths of the output pulses and outputting the adjacent output pulses in the 256-stage half-bit configuration scanning circuits 11-1 to 11-257. This is achieved by configuring the AND gate circuits 21-1, 21-2 to 21-256.

The feature of this circuit is that the half-bit configuration scanning circuits 11-P. 11-1 to 11-25 are different from the conventional example.
7 and the NAND gate circuits 15-1 to 15-1024, AND gate circuits 21-1, 21-2 to 21-2.
By providing 56, the NAND gate circuit 15-1
The number of the second control signals G1 to G4 to 15 to 1024 is halved.

Further, the output signals from the adjacent half-bit configuration scanning circuits 11-P.11-1 to 11-257 are set to A.
It is input to the ND gate circuits 21-1, 21-2 to 21-256. These AND gate circuits 21-1, 21-
Since 256 output signals from 2 to 21-256 are required, another stage of spare scanning circuit 11-P is provided in front of the half-bit configuration scanning circuit 11-1. The spare scanning circuit 11-P may be provided in the subsequent stage of 11-257.

A driving method in the liquid crystal display device having the above structure will be described with reference to a timing chart in the case of sequential scanning shown in FIG.

First, the half bit configuration scanning circuit 11
-P. Start pulse STa having a pulse width of (8T) with T being a scanning line selection period in P-11-1 to 11-257,
A clock signal CLK having a cycle of (8T) and an inverted clock signal / CLK which is its inverted signal are input.

As a result, the half-bit configuration scanning circuit 1
Outputs from 1-P.11-1 to 11-257 Q1.P1
~ P256 occurs. Thereafter, outputs Q1 and P1, P1 and P2, ..., P255 and P256 from the adjacent half-bit configuration scanning circuits 11-P.
And AND gate circuits 21-1, 21-2 to 21-25
6 and inputs these AND gate circuits 21-1 and 21-
2 to 21-256, the half-bit configuration scanning circuit 11
-GPP1, GPP2 to G, which are half of the output pulse width (4T) of the output pulses from P.11-1 to 11-257
PP256 is output.

Next, these outputs GPP1 to GPP256
Is input to the NAND gate circuits 15-1 to 15-1024, but these NAND gate circuits 15-1 to 15-1
The second control signal G shown in FIG.
Four signals 1 to G4 are used, and the number of control signals is ½ of the conventional number.

In this way, the NAND gate circuits 15-1 to 15-1
The pulse widths of GP1 to GP1024 are (T) and the phases are sequentially shifted by (T) as an output signal from the output terminal 15-1024 and an output signal from the output buffer circuit 14, thereby sequentially scanning the scanning lines. To do.

As a result, since the number of control signals can be reduced, the liquid crystal display device can be downsized and the cost can be reduced.

As described above, in the liquid crystal display device and the driving method thereof according to the present embodiment, 25 in the vertical drive circuit 20.
6-stage half-bit configuration scanning circuits 11-1 to 11-25
When the start pulse STa is input to 7, the half-bit configuration scanning circuits 11-1 to 11-257 sequentially shift by half a cycle of the clock signal CLK having a cycle of (2 × 4 × T). Output signal Q1, which is a pulse signal
P1, P2, P3 ... P256 are output respectively.

These pulse signals are AND gate circuits 21-1, 21-2 to 21-2 as a means for shortening the pulse width.
The AND gate circuits 21-1 and 21
At -2 to 21-256, the pulse width of the output pulse is reduced to generate the pulse having the pulse width (4 * T).

These AND gate circuits 21-1, 21-
The output of 2-21-256 is (256 × 4 = 1024)
It is input to each first control terminal of the NAND gate circuits 15-1 to 15-1024.

Here, the NA of (256 × 4 = 1024)
In the ND gate circuits 15-1 to 15-1024, each of the four first control terminals is commonly connected, and thus each of the A
Each of the pulse signals from the ND gate circuits 21-1, 21-2 to 21-256 has four NAND gate circuits 1
5-1 to 15-4, 15-5 to 15-8 ... 15-102
1 to 15-1024.

Further, each NAND gate circuit 15-1 to 15-1
5-1024 has four other types of second control signals G every (4-1 = 3) from the second control terminal as another input.
1 to G4 are input respectively. Each second control signal G1
G4 is composed of pulses having a pulse width (T) and a period of (4 × T).

As a result, the NAND gate circuits 15-1 to 15-1024 and the output buffer circuit 14 ...
Outputs a pulse width (T) signal.

Therefore, by sequentially inputting the signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit 2 are combined to turn on / off the thin film transistors of the active matrix array 1. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, the NAND gate circuits 105-1 to 105-1024 (see FIG. 20) are
Since different types of signals are input every (2 × 4-1 = 7), NAND gate circuits 105-1 to 105
The control line input to −1024 is at least (2 × 4 =
8) I needed one. Therefore, the vertical drive circuit 20
There is a problem in that the number of control lines input to the circuit increases and the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, which increases the area required for the circuit layout. there were.

However, in the present embodiment, AND gate circuits 21-1, 21 as pulse width shortening means for reducing the pulse width of the output pulse of each half bit configuration scanning circuit 11-1 to 11-257 and outputting it. -2-21-256
Since the NAND gate circuits 15-1 to 15-1 are provided
Each second control terminal in 5-1024 (4-1 =
3) It becomes possible to make common connection every other number. Therefore,
The number of types of second control terminals is four, which is half the conventional type.

Further, the wiring is connected to each AND gate circuit 21-
1.21-2-2 to 21-256 and NAND gate circuit 15
It is possible to prevent the control lines from being concentrated, because the control lines are distributed in the range from -1 to 15-1024.

As a result, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device, in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

Further, in the liquid crystal display device according to the present embodiment, in particular, the half bit configuration scanning circuits 11-1 to 11-1.
As a pulse width shortening means for reducing the pulse width of the output pulse of 1-257 and outputting it, the AND gate circuit 21- to which the adjacent output pulses in the 256-stage half-bit configuration scanning circuits 11-1 to 11-257 are input. 1.21
It is composed of −2 to 21-256.

As a result, it is possible to provide a liquid crystal display device and a method of driving the liquid crystal display device, which can surely reduce the number of drive signals for operating the liquid crystal display device and improve the yield.

[Embodiment 3] The following will describe another embodiment of the present invention in reference to FIGS. 6 and 7. For convenience of explanation, members having the same functions as the members shown in the drawings of the first and second embodiments will be designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 6, the vertical drive circuit 30 of the liquid crystal display device of the present embodiment is a half-bit configuration scanning circuit which sequentially shifts the start pulse STa by half a pulse per stage in synchronization with the clock signal CLK. 11-1 to 1
1-257 and its half-bit configuration scanning circuit 11-1
11-257 output signals P1, P2, P3 ... P25
AND gate circuits 31-1, 31-2 to 31-256 as pulse width shortening means and fifth logic gate circuits, which have 6 and the fourth control signals H1 and H2 as input signals, and these AND gate circuits 31- NAN having output signals PP1, PP2, ... PP256 from 1 / 31-2 to 31-256 and second control signals G1, G2, G3, G4 as input signals
D gate circuits 15-1 to 15-1024 and their NAs
The output buffer circuit 14 receives the output signals of the ND gate circuits 15-1 to 15-1024 as an input signal.

The feature of this circuit is that the AND circuit is compared with the conventional example.
By providing the gate circuits 31-1, 31-2 to 31-256, the NAND gate circuits 15-1 to 15-10 are provided.
The reason is that the number of control signals to 24 is halved.

A driving method in the liquid crystal display device having the above structure will be described with reference to a timing chart in the case of sequential scanning shown in FIG.

First, the half bit configuration scanning circuit 11
In -1 to 11-257, a start pulse STa having a pulse width of (8T) and a period of (8
The clock signal CLK which is T) and the inverted clock signal / CLK which is its inverted signal are input.

As a result, the half-bit configuration scanning circuit 1
Outputs P1 to P256 from 1-1 to 11-257 are generated. After that, the half bit configuration scanning circuits 11-1 to 11-1
The outputs P1 to P256 from 1-257 and the fourth control signals H1 and H2 are AND gate circuits 31-1 and 31-2 to 3-2.
1-256 and these AND gate circuits 31-
From 1 · 31-2 to 31−256, PP1 · PP2 ... PP256 having an output pulse width that is half of the output pulse from the half-bit configuration scanning circuits 11-1 to 11-257 is output.

Next, these PP1 ... PP256 are NAN
The NAND gate circuits 15-1 to 15-102 are input to the D gate circuits 15-1 to 15-1024.
The second control signals G1 to G1 shown in FIG.
Uses four G4 signals and sets the number of control signals to 1
The number is / 2.

In this way, the NAND gate circuits 15-1 to 15-1
The pulse widths of GP1 to GP1024 are (T) and the phases are sequentially shifted by (T) as an output signal from the output terminal 15-1024 and an output signal from the output buffer circuit 14, thereby sequentially scanning the scanning lines. To do.

As a result, since the number of control signals can be reduced, the liquid crystal display device can be downsized and the cost can be reduced.

As described above, in the liquid crystal display device and the driving method thereof according to the present embodiment, 25 in the vertical drive circuit 30.
6-stage half-bit configuration scanning circuits 11-1 to 11-25
When the start pulse STa is input to 7, the half-bit configuration scanning circuits 11-1 to 11-257 sequentially shift by half a cycle of the clock signal CLK having a cycle of (2 × 4 × T). Output signal P1, which is a pulse signal
P2, P3 ... P256 are output respectively.

These pulse signals are AND gate circuits 31-1, 31-2 to 31-2 as a pulse width shortening means.
56, and the pulse width shortening means reduces the pulse width of the output pulse to generate a pulse having a pulse width (M × T). These AND gate circuits 31-
The outputs of 1.31-2 to 31-256 are (256 × 4 =
1024) NAND gate circuits 15-1 to 15-1
024 is input to each first control terminal.

Here, the NA of (256 × 4 = 1024)
In the ND gate circuits 15-1 to 15-1024, each of the four first control terminals is commonly connected, and thus each of the A
The pulse signals from the ND gate circuits 31-1, 31-2 to 31-256 are respectively provided by four NAND gate circuits 1.
5-1 to 15-4, 15-5 to 15-8 ... 15-102
1 to 15-1024.

Further, each NAND gate circuit 15-1 to 15-1
5-1024 has four other types of second control signals G every (4-1 = 3) from the second control terminal as another input.
1 to G4 are input respectively. Each second control signal G1
G4 is composed of pulses having a pulse width (T) and a period of (4 × T).

As a result, the NAND gate circuits 15-1 to 15-1024 and the output buffer circuit 14 ...
Outputs a pulse width (T) signal.

Therefore, by sequentially inputting signals of these pulse widths (T) to the scanning lines, the signals from the signal lines of the horizontal drive circuit 2 are combined to turn on / off the thin film transistors of the active matrix array 1. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, the NAND gate circuits 105-1 to 105-1024 (see FIG. 20) are
Since different types of signals are input every (2 × 4-1 = 7), NAND gate circuits 105-1 to 105
The control line input to −1024 is at least (2 × 4 =
8) I needed one. Therefore, the vertical drive circuit 30
There is a problem in that the number of control lines input to the circuit increases and the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, which increases the area required for the circuit layout. there were.

However, in the present embodiment, AND gate circuits 31-1 and 31 as pulse width shortening means for reducing the pulse width of the output pulse of each half bit configuration scanning circuit 11-1 to 11-257 and outputting it. -2-31-256
Since the NAND gate circuits 15-1 to 15-1 are provided
Each second control terminal in 5-1024 (4-1 =
3) It becomes possible to make common connection every other number. Therefore,
The number of types of second control terminals is four, which is half the conventional type.

Further, the wiring is connected to each AND gate circuit 31-
1.31-2-31-256 and NAND gate circuit 15
It is possible to prevent the control lines from being concentrated, because the control lines are distributed in the range from -1 to 15-1024.

As a result, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device, in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

Further, in the liquid crystal display device and the driving method thereof according to the present embodiment, in particular, the pulse width shortening means includes the output pulse from the 256-stage half-bit configuration scanning circuits 11-1 to 11-257 and the period (2 AN input with either one of two types of fourth control signals H1 and H2 consisting of forward and reverse pulses having a pulse width of (4 × T) and a pulse width (4 × T).
It is composed of D gate circuits 31-1, 31-2 to 31-256.

Therefore, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device, which can surely reduce the number of drive signals for operating the liquid crystal display device and improve the yield.

Further, in the liquid crystal display device and the driving method thereof according to the present embodiment, the clock signal CLK and the inverted clock signal / CLK are used as the fourth control signals H1 and H2. Therefore, it is not necessary to input a new control line to the vertical drive circuit 30 as the fourth control signals H1 and H2. Further, it is not necessary to create a new signal in the external circuit.

As a result, in the conventional case, the vertical drive circuit 3
The number of control lines input to 0 increases, the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, which increases the area required for circuit layout. However, this can be prevented by using the existing control line.

Therefore, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

[Fourth Embodiment] The following will describe another embodiment of the present invention in reference to FIGS. 8 and 9. For convenience of explanation, members having the same functions as those shown in the drawings of the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 8, the vertical drive circuit 40 of the liquid crystal display device of the present embodiment is a half-bit configuration scanning circuit which sequentially shifts the start pulse STa by half a pulse for each stage in synchronization with the clock signal CLK. 11-1 to 1
1-512 and their half-bit configuration scanning circuits 11-
Each output signal PP that outputs 1 to 11-512 every other stage
1, PP2, PP3 ... PP256 and these output signals PP
1 · PP2 ... PP256 and second control signals G1 · G2 ·
NAND gate circuits 15-1 to 15-1024 forming a sixth logic gate circuit having G3 and G4 as input signals
And these NAND gate circuits 15-1 to 15-102
4 and the output buffer circuit 14 which uses the output signal of 4 as an input signal.

The feature of this circuit is that half-bit configuration scanning circuits 11-1 to 11-512 having twice as many stages as those in the first to third embodiments are provided, and the output is provided every other stage. By taking out, the overlap between adjacent output pulses is eliminated, and NAND gate circuits 15-1 to 15-
This is to halve the number of control signals to 1024.

A driving method in the liquid crystal display device having the above structure will be described with reference to a timing chart in the case of sequential scanning shown in FIG.

First, the half bit configuration scanning circuit 11
-1 to 11-512, with T as a scanning line selection period, a start pulse STa having a pulse width of (4T), a clock signal CLK having a period of (4T), and an inverted clock signal / CLK which is an inverted signal thereof. Enter. Then
These half bit configuration scanning circuits 11-1 to 11-51
By taking out the outputs from the second stage every other stage, outputs PP1 ... PP2 that do not overlap in the adjacent output pulses.
56 occurs.

Next, these PP1 ... PP256 are NAN
It is input to the D gate circuits 15-1 to 15-1024.
As control signals to these NAND gate circuits 15-1 to 15-1024, the second control signals G1 to G shown in FIG.
It is assumed that four signals are used and the number of control signals is 1/2 that of the conventional one.

Thus, the NAND gate circuits 15-1 to 15-1
As the output from 15-1024 and the output signal from the output buffer circuit 14, a pulse having a pulse width of GP1 to GP1024 of (T) and a phase sequentially shifted by (T) is generated, thereby sequentially scanning the scanning lines. To scan.

As a result, the number of control signals can be reduced, so that the liquid crystal display device can be downsized and the cost can be reduced.

As described above, in the liquid crystal display device and the driving method thereof according to the present embodiment, 2 × in the vertical drive circuit 40 is used.
Start pulse S with a pulse width of (4 × T) in 256 steps
When Ta is input, each half bit configuration scanning circuit 11
From -1 to 11-511, pulse signals sequentially shifted by half a cycle of the clock signal CLK having a cycle of (4 * T) are output. Therefore, the output signals extracted from the 2 × 256 stages of half-bit configuration scanning circuits 11-1 to 11-512 every other stage are sequentially shifted by one cycle.

These pulse signals are (256 × 4 = 10
24) NAND gate circuits 15-1 to 15-102
4 to each first control terminal.

Here, the NA of (256 × 4 = 1024)
In the ND gate circuits 15-1 to 15-1024, the first control terminals are commonly connected every four, so that the half-bit configuration scanning circuits 11-1 to 11-51 in every other stage are connected.
The pulse signals from 1 are four NAND gate circuits 15-1 to 15-4, 15-5 to 15-8, ... 15-, respectively.
1021 to 15-1024.

Further, each NAND gate circuit 15-1 to 15-1
5-1024 has four other types of second control signals G every (4-1 = 3) from the second control terminal as another input.
1 to G4 are input respectively. Each second control signal G1
G4 is composed of pulses having a pulse width (T) and a period of (4 × T).

As a result, the NAND gate circuits 15-1 to 15-1024 and the output output buffer circuit 1 described above are provided.
4 outputs a pulse width (T) signal.

Therefore, by sequentially inputting the signals of these pulse widths (T) to the scanning lines, the thin film transistors of the active matrix array 1 are turned on / off in combination with the signals from the signal lines of the horizontal drive circuit 2. The screen of the liquid crystal display device can be displayed.

That is, in the conventional case, the NAND gate circuits 105-1 to 105-1024 (see FIG. 20) are
Since different types of signals are input every (2 × 4-1 = 7), NAND gate circuits 105-1 to 105
The control line input to −1024 is at least (2 × 4 =
8) I needed one. Therefore, the vertical drive circuit 40
There is a problem in that the number of control lines input to the circuit increases and the area of the input pad increases, and moreover, it is necessary to lay out the wires for the number of control lines, which increases the area required for the circuit layout. there were.

However, in the present embodiment, two half-bit configuration scanning circuits 11-1 to 11-512 which sequentially shift and output the pulse signal by a half cycle of the clock signal CLK by inputting the start pulse STa are output. × 25
The scanning circuit 11 is provided in 6 stages (N is a positive integer), and the output signal thereof is extracted in 2 × 256 stages of the half-bit configuration scanning circuit 11.
By performing every other stage from -1 to 11-512, each output signal is sequentially shifted by one cycle.

As a result, the NAND gate circuits 15-1 to 15-1
Each second control terminal in 15-1024 (4-1 =
3) It becomes possible to make common connection every other number. Therefore,
The number of types of second control terminals is four, which is half the conventional type.

Therefore, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

[Embodiment 5] The following will describe another embodiment of the present invention in reference to FIGS. 10 and 11. For convenience of explanation, the first embodiment described above is used.
The members having the same functions as the members shown in the drawings of the fourth embodiment are designated by the same reference numerals and the description thereof will be omitted.

Further, in the first to fourth embodiments, the example in which four scanning lines are driven by the output signal of one stage has been shown, but in the present embodiment, the output of one stage is output. An example in which two scanning lines are driven by a signal will be described.

As shown in FIG. 10, the vertical drive circuit 50 of the liquid crystal display device of the present embodiment has a start pulse STa.
Scan circuit 11-P., Which sequentially shifts each half pulse by one pulse in synchronization with the clock signal CLK.
11-1 to 11-513 and these output signals Q1 and P1 adjacent to the output signals Q1, P1, P2, P3, ... P256 of the half-bit configuration scanning circuits 11-P, 11-1 to 11-512, respectively. P1 and P2, ..., P511 and P5
AND gate circuits 51-1, 51-2 to 51-512 as a seventh logic gate circuit having 12 and 12 as input signals
And these AND gate circuits 51-1 and 51-2 to 51
-512 Output signal GPP1, GPP2 ... GPP5
NAND having 12 and control signals G1 and G2 as input signals
Gate circuits 15-1 to 15-1024 and these NANs
The output buffer circuit 14 receives the output signals of the D gate circuits 15-1 to 15-1024 as input signals.

That is, the vertical drive circuit 50 of the present embodiment.
Is similar to the vertical drive circuit 20 shown in the second embodiment, and compared with the vertical drive circuit 20 shown in FIG. 4, one AND gate circuit 21-1, 21-2 to 2 is provided.
The number of outputs from 1-256 is two.

The feature of this circuit is that the AN
The NAND gate circuits 15-1 to 15-1 are provided by providing the D gate circuits 51-1 and 51-2 to 51-512.
The number of control signals to 024 is halved. In addition, adjacent half-bit configuration scanning circuits 11-P
While the output signals from 11-1 to 11-513 are input to the AND gate circuits 51-1 and 51-2 to 51-512, these AND gate circuits 51-1 and 51-2 to 51-51
Since 256 output signals from -512 are required, another half-stage spare half-bit scan circuit 11-P is provided in front of the half-bit scan circuit 11-1. Incidentally, this spare half-bit configuration scanning circuit 1
1-P may be provided in the subsequent stage of the half bit configuration scanning circuit 11-513. A driving method in the liquid crystal display device having the above configuration will be described with reference to a timing chart when sequential scanning is performed as shown in FIG.

First, the half bit configuration scanning circuit 11
-P. 11-1 to 11-513, in which T is a scanning line selection period, a start pulse STa having a pulse width of (4T),
A clock signal CLK having a cycle of (4T) and an inverted clock signal / CLK which is its inverted signal are input.

As a result, the half-bit configuration scanning circuit 1
1-P. 11-1 to 11-512 output Q1. P1
... P512 occurs. Thereafter, outputs Q1 and P1, P1 and P2, ..., P511 and P512 from the adjacent half-bit configuration scanning circuits 11-P.
Are AND gate circuits 51-1 and 51-2 to 51-512
Are input to the AND gate circuits 51-1 and 51-
2 to 51-512, half-bit configuration scanning circuit 11
GPP1, GPP2 ... GPP51, which has an output pulse width that is half that of the output pulses from P. 11-1 to 11-513
2 is output.

Next, these GPP1 to GPP512 are N
Input to the AND gate circuits 15-1 to 15-1024, these NAND gate circuits 15-1 to 15-10
As the control signal of 24, two signals of G1 and G2 shown in the figure are used.

These control signals G1 and G2 have a cycle (2
The control signal G2 can be an inverted signal of the control signal G1. Therefore, the number of signal input terminals can be reduced by inputting the signal of the control signal G1 to the control signal G2 with one signal input terminal through the inverter formed on the substrate.

In this way, the NAND gate circuits 15-1 to 15-1
15-1024 and an output signal from the output buffer circuit 14, the pulse width of GP1 ... GP1024 is (T), and the pulse whose phase is sequentially shifted by (T) is generated, thereby sequentially scanning lines. To scan.

As a result, since the number of control signals can be reduced, the liquid crystal display device can be downsized and the cost can be reduced.

As described above, in the liquid crystal display device and the driving method thereof according to the present embodiment, the half bit configuration scanning circuits 11-1 to 11-257 in the vertical drive circuit 20 (see FIG. 4) shown in the second embodiment are provided. Adjacent output pulses in the AND gate circuits 21-1, 21-2 to 21-25
6 and the half-bit configuration scanning circuit 11
-1 to 11-257 is doubled.

As a result, even with such a combination, it is possible to provide a liquid crystal display device and a method for driving the liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In the above first to fifth embodiments,
Although only the progressive scanning method has been described, the liquid crystal display device shown in the first to fourth embodiments can be applied to the interlaced scanning method and the two-line simultaneous scanning method. However, in the fifth embodiment, the sequential scanning can be performed with a small number of control signals, but the interlace scanning method or the two-line simultaneous scanning method cannot be applied.
That is, these scans can be performed when the number of control signals is four or more.

[Sixth Embodiment] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to fifth embodiments are designated by the same reference numerals and the description thereof will be omitted.

While the sequential scanning has been described in the first to fifth embodiments, the case where interlaced scanning or two simultaneous scanning is performed will be described from the present embodiment onward.

First, interlaced scanning using the vertical drive circuit 10 shown in FIG. 1 in the first embodiment will be described.

In the interlaced scanning in the vertical drive circuit 10, as shown in FIG. 12, the half-bit configuration scanning circuits 11-1 to 11-257 are provided with a start pulse having a pulse width of (4T) with T being a scanning line selection period. STa, a clock signal CLK having a pulse period of (4T), and an inverted clock signal / CLK which is an inversion signal thereof are input.

As a result, the half-bit configuration scanning circuit 1
Output signals P1 and P2 ... P25 from 1-1 to 11-257
6 occurs. The second is used as a control signal for the AND gate circuits 12-1 to 12-1024, which are the first logic gate circuits.
The control signals G1, G2, G3, and G4 are used to reduce the control signal to 1/2 of the conventional one.

In the present embodiment, in the odd field, the control signal of the pulse period (2T) is input to the second control signal G1, and the second control signal G3 has the same phase as the second control signal G1. A control signal deviated by (T) is input. Further, regarding the second control signals G2 and G4, no control signal is input.

In the present embodiment, the pulses of the second control signals G1 and G3 are generated even in the blanking period immediately after the video signal writing period. However, the present invention is not limited to this. Second control signal G
The 1 · G3 pulse may not be generated.

After that, the first logic gate circuit AN
Output GPP1 of the D gate circuits 12-1 to 12-1024
Two output pulses appear in GPP2 ... GPP1024. These output pulses are input to the NAND gate circuits 13-1 to 13-1024 which form the second logic gate circuit.

At this time, the NAND gate circuits 13-1 to 13-4.13 to which the outputs of the odd-numbered half-bit configuration scanning circuits 11-1, 11-3 ... 11-257 are connected.
While the third control signal PP1 is input to -9 to 13-12, the half-bit configuration scanning circuit 11-2 of the even-numbered stage is input.
・ 11-4 ... NAN to which output of 11-256 is connected
D gate circuits 13-5 to 13-8 and 13-13 to 13-
The third control signal PP2 is input to 16 ...

The clock signal CLK input to the half-bit configuration scanning circuits 11-1 to 11-257 may be used as the third control signal PP1, while the half-bit configuration may be used as the third control signal PP2. Configuration scanning circuit 1
Inverted clock signal input to 1-1 to 11-257 /
CLK should be used. Therefore, it is not necessary to create a new control signal. Further, it is not necessary to newly create a signal input terminal from the outside.

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Thus, a pulse whose phase is sequentially shifted by (T) is generated, whereby the scanning lines are interlaced.

Although not shown in the figure, in the even-numbered fields, the signals indicated by the second control signals G1 and G3 are input to the second control signals G2 and G4, respectively, and the output buffer circuits 14 ... Output signal GP2 as the output signal of
A pulse having a pulse width (T) and a phase sequentially shifted by (T) is generated in the even-numbered scanning lines of GP4, GP6, ... GP1024.

As described above, in the present embodiment, the vertical drive circuit 10 of the liquid crystal display device can be used to perform interlaced scanning.

[Seventh Embodiment] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to sixth embodiments are designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, description will be given of two-line simultaneous scanning using the vertical drive circuit 10 shown in the first embodiment.

In the two-line simultaneous scanning in the vertical drive circuit 10 of the present embodiment, as shown in FIG. 13, the half-bit configuration scanning circuits 11-1 to 11-257 have a pulse width of T as a scanning line selection period. A start pulse STa of (4T), a clock signal CLK having a pulse period of (4T), and an inverted clock signal / CL which is an inverted signal thereof.
You typed K.

As a result, the half-bit configuration scanning circuit 1
Output signals P1 and P2 ... P25 from 1-1 to 11-257
6 occurs. The second is used as a control signal for the AND gate circuits 12-1 to 12-1024, which are the first logic gate circuits.
The control signals G1, G2, G3, and G4 are used to reduce the control signal to 1/2 of the conventional one.

In the present embodiment, in the odd field, the second control signals G1 and G2 have a pulse period (2T).
Control signal is input, and the second control signals G3 and G4 are input with control signals that are out of phase with the second control signals G1 and G2 by (T).

In the present embodiment, the pulses of the second control signals G1, G2, G3, and G4 are generated even in the blanking period immediately after the video signal writing period.
It is not always limited to this, and these second
It is not necessary to generate the pulses of the control signals G1, G2, G3, and G4.

After that, the first logic gate circuit AN
Output GPP1 of the D gate circuits 12-1 to 12-1024
Two output pulses appear in GPP2 ... GPP1024. These output pulses are input to the NAND gate circuits 13-1 to 13-1024 which form the second logic gate circuit.

At this time, the NAND gate circuits 13-1 to 13-4.13 to which the outputs of the odd-numbered half-bit configuration scanning circuits 11-1, 11-3 ... 11-257 are connected.
While the third control signal PP1 is input to -9 to 13-12, the half-bit configuration scanning circuit 11-2 of the even-numbered stage is input.
・ 11-4 ... NAN to which output of 11-256 is connected
D gate circuits 13-5 to 13-8 and 13-13 to 13-
The third control signal PP2 is input to 16 ...

The clock signal CLK input to the half-bit configuration scanning circuits 11-1 to 11-257 may be used as the third control signal PP1, while the third control signal PP2 may be half-bit. Configuration scanning circuit 1
Inverted clock signal input to 1-1 to 11-257 /
CLK should be used. Therefore, it is not necessary to create a new control signal. Further, it is not necessary to newly create a signal input terminal from the outside.

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Therefore, a pulse whose phase is sequentially shifted by (T) is generated, and thereby two scanning lines are simultaneously scanned.

Although not shown in the figure, in the even field, the signals shown in the second control signals G1 and G3 are input to the second control signals G2 and G4, respectively, and the output buffer circuits 14 ... Output signal GP2 as the output signal of
A pulse having a pulse width (T) and a phase sequentially shifted by (T) is generated in the even-numbered scanning lines of GP4, GP6, ... GP1024.

As described above, in the present embodiment, the vertical drive circuit 10 of the liquid crystal display device can be used to perform simultaneous scanning of two lines.

[Embodiment 8] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to seventh embodiments will be designated by the same reference numerals, and the description thereof will be omitted.

In this embodiment, interlaced scanning using the vertical drive circuit 20 shown in FIG. 4 in the second embodiment will be described.

In the interlaced scanning in the vertical drive circuit 20 of the present embodiment, as shown in FIG. 14, half-bit configuration scanning circuits 11-P.11-1 to 11-257.
Further, a start pulse STa having a pulse width of (4T), a clock signal CLK having a pulse period of (4T), and an inverted clock signal / CLK which is an inverted signal of the start pulse STa are input with T being a scanning line selection period.

As a result, the half-bit configuration scanning circuit 1
Output signal Q1 · P from 1-P · 11-1 to 11-257
1 / P2 / P3 ... P256 occurs. After that, adjacent half-bit configuration scanning circuits 11-P. 11-1 to 11-
257 output signals Q1 and P1, P1 and P2, ..., P
255 and P256 are ANs as a fourth logic gate circuit.
The output signal GPP1 having a half output pulse width of each output signal Q1, P1, P2, P3, ... P256 is input from the AND gate circuits 12-1 to 12-1024 to the D gate circuits 21-1 to 21-256.・ GPP2 ... GPP
256 is output.

Next, these output signals GPP1 and GPP2
... NA which GPP256 comprises a 3rd logic gate circuit
These NAND gate circuits 15-1 to 15-102 are input to the ND gate circuits 15-1 to 15-1024.
The second control signal G1, G2, G3.
Four signals of G4 are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the control signal of the pulse period (2T) is input to the second control signal G1, and the second control signal G3 has a phase different from that of the second control signal G1. A control signal deviated by (T) is input. Note that no control signal is input for the second control signals G2 and G4.

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Thus, a pulse whose phase is sequentially shifted by (T) is generated, whereby the scanning lines are interlaced.

Although not shown, in the even field, the signals shown in the second control signals G1 and G3 are input to the second control signals G2 and G4, and the output buffer circuits 14 ... Output signal GP2 as the output signal of
A pulse having a pulse width (T) and a phase sequentially shifted by (T) is generated in the even-numbered scanning lines of GP4, GP6, ... GP1024.

As described above, in the present embodiment, the vertical drive circuit 20 of the liquid crystal display device can be used to perform interlaced scanning.

[Ninth Embodiment] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to eighth embodiments will be designated by the same reference numerals, and the description thereof will be omitted.

In the present embodiment, two-line simultaneous scanning using the vertical drive circuit 20 shown in FIG. 4 in the second embodiment will be described.

In the two-line simultaneous scanning in the vertical drive circuit 20 of the present embodiment, as shown in FIG. 15, the half bit configuration scanning circuits 11-P.
In the scanning line selection period, a start pulse STa having a pulse width of (4T), a clock signal CLK having a pulse period of (4T), and an inverted clock signal / CLK which is an inverted signal thereof are input.

As a result, the half-bit configuration scanning circuit 1
Output signal Q1 · P from 1-P · 11-1 to 11-257
1 / P2 / P3 ... P256 occurs. After that, adjacent half-bit configuration scanning circuits 11-P. 11-1 to 11-
257 output signals Q1 and P1, P1 and P2, ..., P
255 and P256 are ANs as a fourth logic gate circuit.
The output signal GPP1 having a half output pulse width of each output signal Q1, P1, P2, P3, ... P256 is input from the AND gate circuits 12-1 to 12-1024 to the D gate circuits 21-1 to 21-256.・ GPP2 ... GPP
256 is output.

Next, these output signals GPP1 and GPP2
... NA which GPP256 comprises a 3rd logic gate circuit
These NAND gate circuits 15-1 to 15-102 are input to the ND gate circuits 15-1 to 15-1024.
The second control signal G1, G2, G3.
Four signals of G4 are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the pulse period (2T) is added to the second control signals G1 and G2.
Control signal is input, and the second control signals G3 and G4 are input with control signals that are out of phase with the second control signals G1 and G2 by (T).

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 and GP2, GP3 and GP4 ... GP1023 and GP10
The pulse width is (T) for each of the 24 scanning lines, and pulses whose phases are sequentially shifted by (T) are generated, whereby two scanning lines are simultaneously scanned.

Although not shown in the figure, in the even-numbered field, the signals indicated by the second control signals G1 and G3 are input to the second control signals G2 and G4, respectively, and the second control signals G1 and G3 are input. The signals indicated by the second control signals G3 and G4 are input to G4, and the pairs of output signals GP1 and GP2 and GP3 and GP4 and GP are recombined with the odd field.
The pulse width is (T) for each of the two scanning lines 5 ..., and pulses whose phases are sequentially shifted by (T) are generated, whereby two scanning lines are simultaneously scanned.

As described above, in the present embodiment, the vertical drive circuit 20 of the liquid crystal display device can be used to perform simultaneous scanning of two lines.

[Embodiment 10] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to ninth embodiments will be designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, interlaced scanning using the vertical drive circuit 30 shown in FIG. 6 in the third embodiment will be described.

In the interlaced scanning in the vertical drive circuit 30, as shown in FIG. 16, the half-bit configuration scanning circuits 11-1 to 11-257 are provided with a start pulse having a pulse width (4T) with T as a scanning line selection period. STa, a clock signal CLK having a pulse period of (4T), and an inverted clock signal / CLK which is an inversion signal thereof are input.

Thus, the half-bit configuration scanning circuit 1
Output signals P1 and P2 ... P25 from 1-1 to 11-257
6 occurs. After that, output signals P1, P2, ... P256
Is an AND gate circuit 3 forming a fifth logic gate circuit
1-1, 31-2 to 31-256, and AN
The D-gate circuits 31-1, 31-2 to 31-256 have a fourth
Of the AND gate circuits 31-1 and 31- by inputting the control signal H1 or the fourth control signal H2 of
2 to 31-256 to output signals P1 · P2 ... P256 whose output pulse width is half that of output signals P1 · P2 ... P256
P256 is output.

Next, these output signals PP1, PP2 ... P
P256 is the NAND gate circuits 15-1 to 15-102.
The second control signal G1, G2, G3.
Four signals of G4 are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the control signal of the pulse period (2T) is input to the second control signal G1 and the second control signal G3 has the same phase as the second control signal G1. A control signal deviated by (T) is input. Further, regarding the second control signals G2 and G4, no control signal is input.

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Thus, a pulse whose phase is sequentially shifted by (T) is generated, whereby the scanning lines are interlaced.

Although not shown, in the even field, the signals indicated by the second control signals G1 and G3 are input to the second control signals G2 and G4, respectively, and the output buffer circuits 14 ... Output signal GP2 as the output signal of
A pulse having a pulse width (T) and a phase sequentially shifted by (T) is generated in the even-numbered scanning lines of GP4, GP6, ... GP1024.

As described above, in this embodiment, the vertical drive circuit 30 of the liquid crystal display device can be used to perform interlaced scanning.

[Eleventh Embodiment] The following will describe another embodiment of the present invention in reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to tenth embodiments will be designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, two-line simultaneous scanning using the vertical drive circuit 30 shown in FIG. 6 in the third embodiment will be described.

In the two-line simultaneous scanning in the vertical drive circuit 30, as shown in FIG.
1-1 to 11-257, a start pulse STa having a pulse width (4T) with T being a scanning line selection period, a clock signal CLK having a pulse period (4T), and an inverted clock signal / CLK which is an inverted signal thereof. I entered.

Thus, the half-bit configuration scanning circuit 1
Output signals P1 and P2 ... P25 from 1-1 to 11-257
6 occurs. After that, output signals P1, P2, ... P256
Is an AND gate circuit 3 forming a fifth logic gate circuit
1-1, 31-2 to 31-256, and AN
The D-gate circuits 31-1, 31-2 to 31-256 have a fourth
Of the AND gate circuits 31-1 and 31- by inputting the control signal H1 or the fourth control signal H2 of
2 to 31-256 to output signals P1 · P2 ... P256 whose output pulse width is half that of output signals P1 · P2 ... P256
P256 is output.

Next, these output signals PP1, PP2 ... P
P256 is the NAND gate circuits 15-1 to 15-102.
The second control signal G1, G2, G3.
Four signals of G4 are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the pulse period (2T) is applied to the second control signals G1 and G2.
Control signal is input, and the second control signals G3 and G4 are input with control signals that are out of phase with the second control signals G1 and G2 by (T).

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Thus, a pulse whose phase is sequentially shifted by (T) is generated, whereby two lines are simultaneously scanned.

Although not shown in the figure, in the even-numbered field, the signals indicated by the second control signals G1 and G2 are input to the second control signals G2 and G3, respectively, and the second control signals G1 and G1 are input. The signals indicated by the second control signals G3 and G4 are input to G4, and the pairs of output signals GP1 and GP2 and GP3 and GP4 and GP are recombined with the odd field.
The pulse width is (T) for each of the two scanning lines 5 ..., and pulses whose phases are sequentially shifted by (T) are generated, whereby two scanning lines are simultaneously scanned.

As described above, in the present embodiment, the vertical drive circuit 30 of the liquid crystal display device can be used to perform two-line simultaneous scanning.

[Embodiment 12] Another embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to eleventh embodiments will be designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, interlaced scanning using the vertical drive circuit 40 shown in FIG. 8 in the fourth embodiment will be described.

In the interlaced scanning in the vertical drive circuit 40, as shown in FIG. 18, the half-bit configuration scanning circuits 11-1 to 11-512 are provided with a start pulse having a pulse width (2T) with T as a scanning line selection period. STa, a clock signal CLK having a pulse period of (2T), and an inverted clock signal / CLK which is an inverted signal thereof are input.

Here, the half-bit configuration scanning circuit 11-
By taking out the outputs from 1 to 11-512 every other stage, the output signals PP1 and PP2 ...
PP256 occurs. After that, output signals PP1 and PP
2 ... PP256 is an NA forming a sixth logic gate circuit
Input to the ND gate circuits 15-1 to 15-1024,
The second control signals G1, G2, G3, G4 are used as control signals for these NAND gate circuits 15-1 to 15-1024.
4 signals are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the control signal of the pulse period (2T) is input to the second control signal G1, and the second control signal G3 has the same phase as the second control signal G1. A control signal deviated by (T) is input. Further, regarding the second control signals G2 and G4, no control signal is input.

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 ・ GP3 ・ GP5 ... The pulse width of GP1023 is (T)
Thus, a pulse whose phase is sequentially shifted by (T) is generated, whereby the scanning lines are interlaced.

Although not shown in the figure, in the even field, the signals indicated by the second control signals G1 and G3 are input to the second control signals G2 and G4, respectively, and the output buffer circuits 14 ... Output signal GP2 ・ G
Pulses having a pulse width (T) and a phase sequentially shifted by (T) are generated in the even-numbered scanning lines of P4, GP6, ..., GP1024.

As described above, in this embodiment, the vertical drive circuit 40 of the liquid crystal display device can be used to perform interlaced scanning.

[Embodiment 13] Another embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to eleventh embodiments will be designated by the same reference numerals and the description thereof will be omitted.

In the present embodiment, two-line simultaneous scanning using the vertical drive circuit 40 shown in FIG. 8 in the fourth embodiment will be described.

In the two-line simultaneous scanning in the vertical drive circuit 40, as shown in FIG.
1-1 to 11-512, a start pulse STa having a pulse width (2T) with T being a scanning line selection period, a clock signal CLK having a pulse period (2T), and an inverted clock signal / CLK which is an inverted signal thereof. I entered.

Here, the half-bit configuration scanning circuit 11-
By taking out the outputs from 1 to 11-512 every other stage, the output signals PP1 and PP2 ...
PP256 occurs. After that, output signals PP1 and PP
2 ... PP256 is an NA forming a sixth logic gate circuit
Input to the ND gate circuits 15-1 to 15-1024,
The second control signals G1, G2, G3, G4 are used as control signals for these NAND gate circuits 15-1 to 15-1024.
4 signals are used, and the control signal is halved as compared with the conventional one.

In the present embodiment, in the odd field, the pulse period (2T) is applied to the second control signals G1 and G2.
Control signal is input, and the second control signals G3 and G4 are input with control signals that are out of phase with the second control signals G1 and G2 by (T).

Thus, in the odd field, the output signal GP is output from each output buffer circuit 14 ...
1 and GP2, GP3 and GP4 ... GP1023 and GP10
The pulse width is (T) for each of the 24 scanning lines, and pulses whose phases are sequentially shifted by (T) are generated, whereby two scanning lines are simultaneously scanned.

Although not shown in the figure, in the even-numbered field, the signals indicated by the second control signals G1 and G2 are input to the second control signals G2 and G3, respectively. The signals indicated by the second control signals G3 and G4 are input to G4, and the pairs of output signals GP1 and GP2 and GP3 and GP4 and GP are recombined with the odd field.
A pulse width is (T) for every two scanning lines 5 ..., and pulses whose phases are sequentially shifted by (T) are generated.

As described above, in the present embodiment, the vertical drive circuit 40 of the liquid crystal display device can be used to perform simultaneous scanning of two lines.

In the first to thirteenth embodiments described so far, all the scanning line selection periods are indicated by T, but this T is different depending on the number of scanning lines and the scanning method. There is no end.

Further, the first to thirteenth embodiments.
, AND gate circuit 1 is used as a logic gate circuit.
Although 2.21, 31 and the NAND gate circuit 15 are used, the present invention is not limited to this, and another logic gate circuit can be used. For example, AND gate circuit 12
A NOR gate circuit may be used instead of 21, 31. In this case, the signal input to the NOR gate circuit is a signal obtained by inverting the signal input to the AND gate circuits 12, 21, 31. Just enter it. Furthermore, the use of other logic gate circuits is also within the scope of the present invention.

[0313]

The liquid crystal display device of the invention according to claim 1 is
As described above, the vertical drive circuit has N stages (N is a positive integer) of the scan circuits that sequentially shift and output the pulse signals by a half cycle of the clock signal by inputting the start pulse, and M vertical scanning circuits. Each of the first control terminals is commonly connected for each (M is an integer of 2 or more), and an output signal from the N-stage scanning circuit is input to each of the commonly connected first control terminals. , (M-1) every M kinds of second
(N × M) first logic gate circuits to which respective second control terminals for inputting a control signal are commonly connected, an output of the first logical gate circuit, and a third control terminal To a second logic gate circuit to which any one of the two types of the third control signals is input.

Therefore, the second control terminals in the first logic gate circuit are commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, since the wiring is distributed between the first logic gate circuit and the second logic gate circuit, it is possible to prevent the control lines from being concentrated.

That is, the area of the drive circuit and the input pad can be reduced by reducing the number of control terminals. Therefore, when a plurality of liquid crystal display devices are taken out from one glass substrate, the substrates are taken out. It is possible to increase the number of passengers for, and increase the number of non-defective panels.

Further, since the area of the drive circuit and the input pad is reduced, the frame area around the display portion of the liquid crystal display device is reduced, and it is easy to incorporate into a personal computer or the like.

Furthermore, by increasing the number of inputs to the logic gate circuit from one stage in the scanning circuit such that the output for one stage in the scanning circuit is input to a plurality of logic gate circuits, the number of stages in the scanning circuit is increased. Therefore, it is difficult to lay out one scanning circuit at the small pixel pitch, especially in a high-definition liquid crystal display device, but in the present invention, the layout becomes easy.

As a result, there is an effect that it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

As described above, in the liquid crystal display device according to the second aspect of the present invention, the vertical drive circuit inputs the start pulse to sequentially shift the pulse signal by half a cycle of the clock signal and output the pulse signal. A scanning circuit of stages (N is a positive integer), a pulse width shortening means for reducing the pulse width of the output pulse of each scanning circuit and outputting the pulse, and a first for each M (M is an integer of 2 or more) Control terminals are commonly connected, and the output signals from the pulse width shortening means are input to each of the commonly connected first control terminals.
It is provided with (N × M) third logic gate circuits to which the respective second control terminals for inputting M kinds of signals every (M−1) are commonly connected.

Therefore, the second control terminals in the third logic gate circuit are commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, the wiring is provided with each pulse width shortening means and the third wiring.
The control lines can be prevented from being concentrated because they are distributed to the logic gate circuits.

As a result, there is an effect that it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

As described above, the liquid crystal display device according to a third aspect of the present invention is the liquid crystal display device according to the second aspect, wherein the pulse width shortening means inputs the adjacent output pulses in the scanning circuits of N stages. And a fourth logic gate circuit.

Therefore, as a concrete pulse width shortening means, by configuring the fourth logic gate circuit to which the adjacent output pulses in the N-stage scanning circuit are inputted, the wiring is arranged to the fourth logic gate. Circuit and a third logic gate circuit.

As a result, it is possible to provide a liquid crystal display device in which the control lines are prevented from concentrating, the number of drive signals for operating the liquid crystal display device is small, and the yield can be improved without fail. Has the effect.

As described above, in the liquid crystal display device according to the fourth aspect of the present invention, in the liquid crystal display device according to the third aspect, the pulse width shortening means has a spare in the preceding stage or the latter stage of the scanning circuit of the N stages. Scanning circuit is provided.

Therefore, there is an effect that the adjacent output pulses in the scanning circuits of N stages can be reliably taken out.

As described above, in the liquid crystal display device according to the fifth aspect of the present invention, in the liquid crystal display device according to the second aspect, the pulse width shortening means includes an output pulse in the N-stage scanning circuit and a positive / negative pulse. It is composed of a fifth logic gate circuit to which any one of two kinds of fourth control signals composed of reverse pulses is inputted.

Therefore, as a concrete pulse width shortening means, the output pulse in the N-stage scanning circuit and any one of the two kinds of the fourth control signals consisting of the forward and reverse pulses are inputted. According to the sixth aspect of the present invention, the clock signal and the inverted clock signal are composed of two kinds of fourth pulses each consisting of forward and reverse pulses.
Since it can be used as a control signal for the liquid crystal display device, it is possible to reliably provide a liquid crystal display device which has a small number of drive signals for operating the liquid crystal display device and can improve the yield.

As described above, the liquid crystal display device according to a sixth aspect of the present invention is the liquid crystal display device according to the first or fifth aspect, wherein the third control signal or the fourth control signal is a clock signal or an inversion signal. It consists of a clock signal.

Therefore, it is not necessary to input a new control line to the vertical drive circuit as the third control signal and the fourth control signal.

As a result, in the conventional case, the number of control lines input to the vertical drive circuit is increased, the area of the input pad is increased, and further, it is necessary to lay out the wires for the number of control lines. Although there is a problem that the area required for the circuit layout becomes large, this can be prevented by using the existing control line.

Therefore, there is an effect that it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

As described above, the liquid crystal display device according to the invention of claim 7 is the liquid crystal display device according to any one of claims 1 to 6, wherein M = 4.

That is, in a high-definition liquid crystal display device,
It is difficult to lay out one scanning circuit with the small pixel pitch.

Therefore, the number of stages of the scanning circuit is increased by increasing the number of inputs to the logic gate circuit from one stage in the scanning circuit such that the output of one stage in the scanning circuit is input to a plurality of logic gate circuits. Can be reduced.

In the present invention, particularly when M = 4,
Since the number of inputs to the logic gate circuit is 4, the layout for one stage of the scanning circuit can be performed at a pitch of 4 pixels, and the layout can be easily performed.

As a result, there is an effect that it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

In the liquid crystal display device according to the eighth aspect of the present invention, as described above, the vertical drive circuit sequentially shifts the pulse signal by half a cycle of the clock signal and outputs it by inputting the start pulse. × N stages (N is a positive integer) of scanning circuits and M first units (M is an integer of 2 or more) are commonly connected to each of the first control terminals. To the output signals of every other stage from the scanning circuit of 2 × N stages, and each second control for inputting M kinds of second control signals every (M-1). And (N × M) sixth logic gate circuits whose terminals are commonly connected.

Therefore, the second control terminals in the sixth logic gate circuit are commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

As a result, there is an effect that it is possible to provide a liquid crystal display device in which the number of drive signals for operating the liquid crystal display device is small and the yield can be improved.

As described above, the driving method of the liquid crystal display device according to the ninth aspect of the present invention is the driving method of the liquid crystal display device according to the first aspect, in which the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (2 × M ×
By inputting a start pulse that is T), signals that are sequentially shifted by a half period using a clock signal having a period of (2 × M × T) are generated, and then sequentially shifted by the above half period. And each of the M types of second signals that output a pulse having a pulse width (T) and a period of (M × T).
And a control signal of the pulse width (T) from each of the first logic gate circuits to the first control terminal and the second control terminal of each first logic gate circuit. Two pulses whose phases are ((M−1) × T) apart from each other are generated, and then the two pulses and the period (2
× M × T) and one of the two types of third control signals consisting of forward / reverse pulses having a pulse width (M × T) is input to the second logic gate circuit, and these second control signals are input. Output a pulse width (T) signal from the logic gate circuit of
This is a method of sequentially inputting signals of the pulse width (T) to the scanning lines.

Therefore, the second control terminals in the first logic gate circuit are commonly connected every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, since the wiring is distributed between the first logic gate circuit and the second logic gate circuit, it is possible to prevent the control lines from being concentrated.

As a result, there is an effect that it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

As described above, the driving method of the liquid crystal display device according to the tenth aspect of the present invention is the driving method of the liquid crystal display device according to the second aspect, wherein the scanning line in the scanning circuit in the vertical driving circuit is selected. The pulse width is (2 × M
By inputting a start pulse of (XT), signals that are sequentially shifted by a half cycle are generated using the clock signal having a cycle of (2 × M × T), and then the above-described half cycle is sequentially generated. The shifted signal is input to the pulse width shortening means to generate pulses each having a pulse width (M × T), and the output from the pulse width shortening means and the cycle are (M × T).
T) and M types of second control signals for outputting pulses having a pulse width (T) are input to the first control terminal and the second control terminal of each sixth logic gate circuit,
Each pulse width is (T) from each of these third logic gate circuits.
Is generated and the signals having the pulse width (T) are sequentially input to the scanning lines.

Therefore, by providing the pulse width shortening means for reducing the pulse width of the output pulse of each scanning circuit and outputting it, each second control terminal in the third logic gate circuit is connected to (M-1). It becomes possible to make common connection every other piece. Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Further, the wiring is provided with each pulse width shortening means and the third wiring.
The control lines can be prevented from being concentrated because they are distributed to the logic gate circuits.

As a result, there is an effect that it is possible to provide a method of driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can realize an improvement in yield.

As described above, the driving method of the liquid crystal display device according to the eleventh aspect of the present invention is the driving method of the liquid crystal display device according to the eighth aspect, wherein the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
By inputting a start pulse of (T), the clock signal having a period of (M × T) is used to generate signals sequentially shifted by a half period, and then the above 2 ×
Each output signal that is sequentially shifted by one cycle extracted from every other stage from the N-stage scanning circuit and the M kinds of second signals that output a pulse having a pulse width (T) and a period of (M × T). A control signal and a sixth control signal are input to the first control terminal and the second control terminal of each sixth logic gate circuit, respectively.
In this method, a signal having a pulse width (T) is generated from the logic gate circuit and the signals having the pulse width (T) are sequentially input to the scanning lines.

Therefore, 2 × N stages (N is a positive integer) of the scanning circuit which sequentially shifts the pulse signal by half cycle of the clock signal and outputs the pulse signal by inputting the start pulse.
, And the output signal is taken out every other stage in the scanning circuit of 2 × N stages, so that each output signal is sequentially shifted by one cycle. As a result, it becomes possible to commonly connect every second control terminal in the sixth logic gate circuit every (M-1). Therefore, the number of types of the second control terminals is M, which is half of the conventional type.

Therefore, there is an effect that it is possible to provide a driving method of a liquid crystal display device, which has a small number of driving signals for operating the liquid crystal display device and can realize an improvement in yield.

As described above, the driving method of the liquid crystal display device according to the twelfth aspect of the present invention is the driving method of the liquid crystal display device according to the first aspect, wherein the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
, Respectively, to generate signals that are sequentially shifted by a half cycle, and then generate signals that are sequentially shifted by the half cycle and (M / 2) control terminals of the M types of control terminals. Two control signals having a cycle of ((M / 2) × T) are input to the first logic gate circuit, and the pulse width is (T) and (((M / 2) −1) × T) apart. The first pulse
Of the two pulses and a third control signal having a period of (M × T) are input to the second logic gate circuit, and a signal having a pulse width (T) is generated. In this method, the signal having the pulse width (T) is output from the second logic gate circuit and is input sequentially to every other scanning line.

Therefore, the number of types of the second control terminals is M, which is half the conventional type. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

In addition, a pulse width (T) signal is sequentially input every other scanning line. Therefore, the liquid crystal display device according to the first aspect can be used to perform the interlaced scanning in which every other scanning line is sequentially input.

As described above, the driving method of the liquid crystal display device according to the thirteenth aspect of the present invention is the driving method of the liquid crystal display device according to the first aspect, in which the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
The signals sequentially shifted by a half cycle are generated using the clock signal which is, and then the signals sequentially shifted by the half cycle and the cycle at the M kinds of control terminals are ((M / 2)).
XT) M / 2 types of control signals are input to the first logic gate circuit, and the pulse width is (T) (((M / 2)-
1) × T) Two pulses apart from each other are generated from the first logic gate circuit, and the two pulses and a third control signal having a period (M × T) are supplied to the second logic gate circuit. Input,
In this method, a signal having a pulse width (T) is output from the second logic gate circuit, and the signal having the pulse width (T) is sequentially input every two scanning lines.

Therefore, the number of types of second control terminals is M, which is half that of the conventional one. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

Further, a signal having a pulse width (T) is sequentially input every two scanning lines. Therefore, the liquid crystal display device according to the first aspect has an effect that two scanning lines can be simultaneously input by sequentially inputting two scanning lines.

As described above, the driving method of the liquid crystal display device according to the fourteenth aspect of the present invention is the driving method of the liquid crystal display device according to the second aspect, in which the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
Using the clock signal, the signals sequentially shifted by the half cycle are generated respectively, and then the signals sequentially shifted by the half cycle are input to the pulse width shortening means, and the pulse width (M
XT / 2) pulses are generated respectively, and the output from the pulse width shortening means and (M /
2) A control signal having a cycle of (M × T / 2) is input to the first control terminal and the second control terminal of each third logic gate circuit, and the pulse width ( The signal of T) is output from the third logic gate circuit,
This is a method of sequentially inputting signals of the pulse width (T) every other scanning line.

Therefore, the number of types of the second control terminals is M, which is half that of the conventional type. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

A signal having a pulse width (T) is sequentially input every other scanning line. Therefore, the liquid crystal display device according to the second aspect can be used to perform an interlaced scan in which every other scan line is sequentially input.

As described above, the driving method of the liquid crystal display device according to the fifteenth aspect of the present invention is the driving method of the liquid crystal display device according to the second aspect, in which the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
Using the clock signal, the signals sequentially shifted by the half cycle are generated respectively, and then the signals sequentially shifted by the half cycle are input to the pulse width shortening means, and the pulse width (M
XT / 2) pulses are generated respectively, and the period from the output from the pulse width shortening means and the M control terminals is (M
XT / 2) M / 2 types of control signals are input to the first control terminal and the second control terminal of each third logic gate circuit, and the pulse width (T) signal is input to the first control terminal and the second control terminal. In this method, the signal having the above pulse width (T) is sequentially input every two scanning lines.

Therefore, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

In addition, a pulse width (T) signal is sequentially input for every two scanning lines. For this reason, the liquid crystal display device according to the second aspect can be used to perform the simultaneous scanning of two scanning lines by sequentially inputting two scanning lines.

As described above, the driving method of the liquid crystal display device according to the sixteenth aspect of the present invention is the driving method of the liquid crystal display device according to the eighth aspect, in which the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
Generating a signal sequentially shifted by a half cycle using the clock signal, and then outputting each output signal sequentially shifted by one cycle taken from every other stage from the scanning circuit of 2 × N stages, A control signal having a cycle of (M × T / 2) is supplied to the (M / 2) control terminals of the M control terminals and the first control terminal and the second control terminal in each sixth logic gate circuit.
Of the pulse width (T), the signal of the pulse width (T) is output from the sixth logic gate circuit, and the signal of the pulse width (T) is sequentially input every other scanning line.

Therefore, the number of types of the second control terminals is M, which is half of the conventional type. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

In addition, a pulse width (T) signal is sequentially input every other scanning line. Therefore, it is possible to perform interlaced scanning in which every other scanning line is sequentially input by using the liquid crystal display device according to the eighth aspect.

As described above, the driving method of the liquid crystal display device according to the seventeenth aspect of the present invention is the driving method of the liquid crystal display device according to the eighth aspect, wherein the scanning line in the scanning circuit in the vertical drive circuit is selected. The pulse width is (M ×
Input the start pulse that is T), and the cycle is (M × T)
Generating a signal sequentially shifted by a half cycle using the clock signal, and then sequentially shifting the output signal by one cycle taken from every other stage from the scanning circuit of 2 × N stages, The M control terminals have a cycle (M × T /
2) M / 2 types of control signals are input to the first control terminal and the second control terminal of each sixth logic gate circuit, and a signal having a pulse width (T) is applied to the sixth logic gate circuit. In this method, the signal having the pulse width (T) is output from the gate circuit and two scanning lines are sequentially input.

Therefore, the number of types of the second control terminals is M, which is half the conventional type. Therefore, there is an effect that it is possible to provide a method for driving a liquid crystal display device, which has a small number of drive signals for operating the liquid crystal display device and can improve yield.

Further, a signal having a pulse width (T) is sequentially input every two scanning lines. Therefore, the liquid crystal display device according to the eighth aspect has an effect that it is possible to perform two simultaneous scanning by sequentially inputting two scanning lines.

[Brief description of drawings]

FIG. 1 shows an embodiment of a liquid crystal display device according to the present invention and is a block diagram showing a configuration of a vertical drive circuit.

FIG. 2 is a timing chart showing a driving method in the vertical driving circuit.

FIG. 3 is an overall configuration diagram of the liquid crystal display device.

FIG. 4 shows another embodiment of the liquid crystal display device according to the present invention and is a block diagram showing a configuration of a vertical drive circuit.

FIG. 5 is a timing chart showing a driving method in the vertical driving circuit.

FIG. 6 shows still another embodiment of the liquid crystal display device according to the present invention, and is a block diagram showing a configuration of a vertical drive circuit.

FIG. 7 is a timing chart showing a driving method in the vertical driving circuit.

FIG. 8 shows still another embodiment of the liquid crystal display device according to the present invention, and is a block diagram showing a configuration of a vertical drive circuit.

FIG. 9 is a timing chart showing a driving method in the vertical driving circuit.

FIG. 10 shows still another embodiment of the liquid crystal display device according to the present invention, and is a block diagram showing a configuration of a vertical drive circuit.

FIG. 11 is a timing chart showing a driving method in the vertical driving circuit.

FIG. 12 is a view showing still another embodiment of the driving method of the liquid crystal display device according to the present invention, the timing showing interlaced scanning in which every other scanning line is sequentially input using the vertical driving circuit shown in FIG. 1. It is a chart.

13 is a timing chart showing two-line simultaneous scanning in which two scanning lines are sequentially input using the vertical drive circuit shown in FIG.

FIG. 14 is a view showing still another embodiment of the driving method of the liquid crystal display device according to the present invention, the timing showing interlaced scanning in which every other scanning line is sequentially input using the vertical driving circuit shown in FIG. It is a chart.

15 is a timing chart showing two-line simultaneous scanning in which two scanning lines are sequentially input using the vertical drive circuit shown in FIG.

16 is a view showing still another embodiment of the driving method of the liquid crystal display device according to the present invention, the timing showing interlaced scanning in which every other scanning line is sequentially input using the vertical driving circuit shown in FIG. It is a chart.

17 is a timing chart showing two-line simultaneous scanning in which two scanning lines are sequentially input using the vertical drive circuit shown in FIG.

FIG. 18 is a diagram showing still another embodiment of the driving method of the liquid crystal display device according to the present invention, the timing showing interlaced scanning in which every other scanning line is sequentially input using the vertical driving circuit shown in FIG. It is a chart.

19 is a timing chart showing two-line simultaneous scanning in which two scanning lines are sequentially input using the vertical drive circuit shown in FIG.

FIG. 20 is an overall configuration diagram showing a conventional liquid crystal display device.

FIG. 21 is a timing chart showing a driving method in the vertical driving circuit of the liquid crystal display device.

[Explanation of symbols]

1 Active Matrix Array 2 Horizontal Driving Circuit 10 Vertical Driving Circuit 11 Half Bit Configuration Scanning Circuit (Scanning Circuit) 12 AND Gate Circuit (First Logical Gate Circuit) 13 NAND Gate Circuit (Second Logical Gate Circuit) 14 Output Buffer Circuit (Second logic gate circuit, third logic gate circuit) 15 NAND gate circuit (third logic gate circuit, sixth logic gate circuit) 20 Vertical drive circuit 21 AND gate circuit (fourth logic gate circuit, Pulse width shortening means) 30 vertical drive circuit 31 AND gate circuit (fifth logic gate circuit) 40 vertical drive circuit 50 vertical drive circuit CLK clock signal (positive pulse) / CLK inverted clock signal (reverse pulse) G1 to G4 second Control signal PP1 · PP2 Third control signal STa Start pulse

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-122747 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/133 550 G09G 3/36

Claims (17)

(57) [Claims] 1. An active matrix array in which a switching element is arranged at each intersection of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit for driving the scanning lines, and a horizontal driving circuit for driving the signal lines. In the liquid crystal display device including the above, the vertical drive circuit is an N-stage (N is a positive integer) scanning circuit that sequentially shifts and outputs a pulse signal by a half cycle of a clock signal by inputting a start pulse. And the first control terminals are commonly connected for every M (M is an integer of 2 or more), and the output signals from the scanning circuits of the N stages are respectively connected to the commonly connected first control terminals. (N × M) first logic gate circuits to which M second second control signals for inputting every M (M-1) second control signals are commonly connected. And the above first logical gate The output of the road, a liquid crystal display device and either of the third two from the control terminal of the third control signal is characterized in that it comprises a second logic gate circuit to be inputted. 2. An active matrix array in which switching elements are arranged at respective intersections of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit for driving the scanning lines, and a horizontal driving circuit for driving the signal lines. In the liquid crystal display device including the above, the vertical drive circuit is an N-stage (N is a positive integer) scanning circuit that sequentially shifts and outputs a pulse signal by a half cycle of a clock signal by inputting a start pulse. And pulse width shortening means for reducing the pulse width of the output pulse of each scanning circuit and outputting the same, and each of the M first control terminals (M is an integer of 2 or more) are commonly connected and The output signal from each of the pulse width shortening means is input to each of the connected first control terminals, and each of the (M-1) second M-type second control signals is input. 2 control A liquid crystal display device, comprising: (N × M) third logic gate circuits whose control terminals are commonly connected. 3. The liquid crystal display device according to claim 2, wherein said pulse width shortening means comprises a fourth logic gate circuit to which adjacent output pulses in said N stages of scanning circuits are inputted. 4. The liquid crystal display device according to claim 3, wherein the pulse width shortening means is provided with a spare scanning circuit at a front stage or a rear stage of the N stages of scanning circuits. 5. A fifth pulse width shortening means to which an output pulse from the N-stage scanning circuit and any one of two types of fourth control signals consisting of forward and reverse pulses are inputted. The liquid crystal display device according to claim 2, wherein the liquid crystal display device comprises a logic gate circuit. 6. The liquid crystal display device according to claim 1, wherein the third control signal or the fourth control signal comprises a clock signal and an inverted clock signal. 7. A method according to claim 1, wherein M = 4.
6. The liquid crystal display device according to any one of 6 above. 8. An active matrix array in which switching elements are arranged at respective intersections of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit for driving the scanning lines, and a horizontal driving circuit for driving the signal lines. In the liquid crystal display device including the above, the vertical drive circuit outputs a pulse signal sequentially shifted by half a cycle of the clock signal by inputting a start pulse.
An N-stage (N is a positive integer) scanning circuit and the first control terminals are commonly connected for every M (M is an integer of 2 or more), and for each of these commonly connected first control terminals. Output signals from every other stage from the scanning circuit of 2 × N stages are input respectively, and each second control terminal for inputting M kinds of second control signals every (M-1). And (N × M) sixth logic gate circuits commonly connected to each other. 9. The method of driving a liquid crystal display device according to claim 1, wherein the scanning circuit in the vertical driving circuit has a pulse width of (2 × M × T), where T is a scanning line selection period. By inputting a pulse, a clock signal having a cycle of (2 × M × T) is used to generate signals that are sequentially shifted by a half cycle, and then, the signals that are sequentially shifted by the half cycle are generated. A second control signal of M types that outputs a pulse having a pulse width (T) and a period of (M × T) is supplied to the first control terminal and the second control terminal of each first logic gate circuit. Each of them is input to generate two pulses having a pulse width of (T) and phases of ((M−1) × T) apart from each other, and The above two pulses, the period (2 × M × T) and the pulse width (M × T) One of the two types of third control signals consisting of the positive and reverse pulses of is input to the second logic gate circuit, and a signal of pulse width (T) is output from each of the second logic gate circuits. A method of driving a liquid crystal display device, which comprises outputting the signals and sequentially inputting the signals having the pulse width (T) to the scanning lines. 10. The method of driving a liquid crystal display device according to claim 2, wherein the scanning circuit in the vertical driving circuit has a pulse width of (2 × M × T) with a scanning line selection period of T. By inputting a pulse, a clock signal having a period of (2 × M × T) is used to generate signals that are sequentially shifted by a half period, and then the signals that are sequentially shifted by the half period are pulse width The pulse having the pulse width (M × T) is generated by inputting to the shortening means, and the output from the pulse width shortening means and the period are (M × T)
And a second control signal of M types for outputting a pulse having a pulse width (T) and the first control signal in each third logic gate circuit.
Input to the control terminal and the second control terminal of the pulse generator, the signals having the pulse widths (T) are generated from the respective third logic gate circuits, and the signals having the pulse width (T) are sequentially input to the scanning lines. A method for driving a liquid crystal display device, comprising: 11. A method of driving a liquid crystal display device according to claim 8, wherein a start pulse having a pulse width of (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. By inputting, clock signals having a cycle of (M × T) are used to generate signals that are sequentially shifted by a half cycle, and then taken out every other stage from the scanning circuit of 2 × N stages. And each output signal sequentially shifted by one cycle and the cycle is (M
XT) and M types of second control signals for outputting a pulse having a pulse width (T) are input to the first control terminal and the second control terminal of each sixth logic gate circuit, A method for driving a liquid crystal display device, wherein a signal having a pulse width (T) is generated from each of the sixth logic gate circuits, and the signal having the pulse width (T) is sequentially input to a scanning line. 12. The method of driving a liquid crystal display device according to claim 1, wherein a start pulse having a pulse width of (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. A clock signal having a cycle of (M × T) is input to generate signals that are sequentially shifted by a half cycle. Next, signals that are sequentially shifted by the half cycle and M types of control terminals are generated. The period of (M / 2) control terminals is ((M /
2) × T) control signal is input to the first logic gate circuit, and two pulses having a pulse width of (T) and separated by (((M / 2) −1) × T) are supplied to the first logic gate circuit. The two pulses and a third control signal having a period of (M × T) are input to a second logic gate circuit, and a pulse width (T) signal is generated from the logic gate circuit. Output from the logic gate circuit of
A method of driving a liquid crystal display device, wherein the pulse width (T) signal is sequentially input every other scanning line. 13. A method of driving a liquid crystal display device according to claim 1, wherein a start pulse having a pulse width (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. A clock signal having a cycle of (M × T) is input to generate signals that are sequentially shifted by a half cycle. Next, the signals that are sequentially shifted by the half cycle and a cycle to M types of control terminals are generated. Is input to the first logic gate circuit, and the pulse width is (T), and (((M / 2) -1) * T). ) Two pulses separated from each other are generated from the first logic gate circuit, and the two pulses and the third control signal having the period (M × T) are input to the second logic gate circuit, and the pulse is input. Width (T)
And a signal of the above pulse width (T) is sequentially input for every two scanning lines. 14. A method of driving a liquid crystal display device according to claim 2, wherein a start pulse having a pulse width of (M × T) is provided to the scanning circuit in the vertical driving circuit, with the scanning line selection period being T. The clock signals having the cycle of (M × T) are input to generate the signals sequentially shifted by the half cycle, and the signals sequentially shifted by the half cycle are input to the pulse width shortening means, A pulse having a pulse width of (M × T / 2) is generated, and the output from the pulse width shortening means and (M / 2) control terminals of the M control terminals have a cycle of (M × T / 2). / 2)
And a control signal that is respectively input to the first control terminal and the second control terminal of each third logic gate circuit, and outputs a signal of pulse width (T) from the third logic gate circuit, A method of driving a liquid crystal display device, wherein a signal having a pulse width (T) is sequentially input every other scanning line. 15. The method of driving a liquid crystal display device according to claim 2, wherein a start pulse having a pulse width of (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. The clock signals having a cycle of (M × T) are input to generate signals that are sequentially shifted by a half cycle, and then the signals that are sequentially shifted by the half cycle are input to the pulse width shortening means, A pulse having a pulse width (M × T / 2) is generated respectively, and the output from the pulse width shortening means and M / 2 types of control with a cycle of (M × T / 2) at M control terminals. A signal and a second control terminal in each of the third logic gate circuits, and outputs a pulse width (T) signal from the third logic gate circuit. The signal of (T) is sequentially input every two scanning lines. Method of driving a liquid crystal display device, characterized in that. 16. A method of driving a liquid crystal display device according to claim 8, wherein a start pulse having a pulse width of (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. A clock signal having a period of (M × T) is input to generate signals sequentially shifted by a half period, and then, every other stage from the 2 × N stage scanning circuit is extracted. Each output signal sequentially shifted by a cycle has a cycle of (M × T) among (M / 2) control terminals of the M control terminals.
/ 2) is input to the first control terminal and the second control terminal of each sixth logic gate circuit, and a pulse width (T) signal is output from the sixth logic gate circuit. And a signal of the above pulse width (T) is sequentially input for every other scanning line. 17. A method of driving a liquid crystal display device according to claim 8, wherein a start pulse having a pulse width (M × T) is set to a scanning circuit in the vertical driving circuit, with a scanning line selection period being T. A clock signal having a period of (M × T) is input to generate signals sequentially shifted by a half period, and then, every other stage from the 2 × N stage scanning circuit is extracted. The first control terminal in each sixth logic gate circuit is provided with each output signal sequentially shifted by a period and M / 2 types of control signals whose period is (M × T / 2) for M control terminals. And a second control terminal respectively to output a pulse width (T) signal from the sixth logic gate circuit, and the pulse width (T) signal is sequentially input to every two scanning lines. And a method for driving a liquid crystal display device.