CN102253909A - PCI (Peripheral Component Interconnect) interface and data transmission method thereof under FPGA (Filed-Programmable Gate Array) environment - Google Patents
PCI (Peripheral Component Interconnect) interface and data transmission method thereof under FPGA (Filed-Programmable Gate Array) environment Download PDFInfo
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Abstract
The invention discloses a multipurpose PCI interface and the data transmission method thereof under an FPGA environment. A method for implementing the PCI interface with the DMA (Direct Memory Access) function is adopted, and the interface is independently implemented through a PCI master device module, a PCI slave device module and a PCI register module. A simple FIFO (First Input First Output) interface easy to implement is adopted and used for a PCI user-side interface, DMA control details are concealed from a user, and the design complexity of the user interface is reduced. In high-capacity data transmission, data are encapsulated according to a data format required by the interface and can be realized in a DMA way by being simply written into FIFO, the control logic complexity is simplified, and the efficiency of development of the user interface is improved.
Description
Technical field
The present invention relates to multi-usage pci interface under a kind of FPGA environment and according to the data transmission method of this interface, FPGA is the abbreviation of Field-Programmable Gate Array, i.e. field programmable gate array.
Background technology
PCI (Peripheral Component Interconnect) is the bus structure that SIG (Special Interest Group) releases.Rose in 1992, and successively had famous manufacturers such as Intel, HP, IBM, Apple, DEC, Compaq, NEC to join again and set up.32 pci buss are to occur with the replacer's of low speed bus identity with PC such as ISA/EISA, and why it becomes the main flow of local bus, are that some outstanding features that had by it determine.Specific as follows:
(1) transfer efficiency height, favorable expandability
The typical frequency of operation of pci bus is 33MHz, supports the 66MHz expansion.Its highway width is 32, and can expand to 64.When more peripheral hardware is received on the cpu bus and is made the bus driver scarce capacity, can adopt many pci buss, these buses can concurrent work, and maximum can connect 4 PCI equipment on every bus.
(2) multibus coexistence, reliable and stable
Pci bus can with bus compatibles such as ISA, EISA, VESA because PCI standard and CPU and clock are irrelevant, that is to say that the plug-in card of PCI is general, can be inserted into any one system that pci bus is arranged get on (general system) to same Type C PU.Pci card is common to the microcomputer of all x86 architectures, no matter be 486 or Pentium CPU, also no matter what hertz are dominant frequency be, has all simplified system design greatly, has guaranteed duty stable of PCI equipment simultaneously.
(3) be independent of processor
PCI can support plug and play, and so-called " plug and play " requires various plug-in card insertion systems just can work exactly, and switch or wire jumper needn't manually be set, and automatic configuration feature is promptly arranged.Pci bus has been each PCI slot definition corresponding configuration space, in case pci card insertion system, system bios can be according to the information of reading from configuration space about this expansion card, the coupling system actual conditions are plug-in card storage allocation or I/O address, interruption and some timing information, realize automatic configuration feature, fundamentally exempted human configuration.
(5) pci bus is widely used
The application of pci bus is very extensive.Almost every PC and industrial computer all have pci bus, and all based on pci bus, other buses are auxilliary; The pci interface bus that all is based on present most video acquisition system, data acquisition system (DAS), network interface unit realizes.
Pci bus is fast owing to its speed, and favorable expandability is compatible strong, the characteristics that stability is high, and the system applies of underway high speed such as video acquisition, data acquisition when PCI-Express is realized, is very desirable selection.But when developing when as above using, two kinds of methods are arranged, a kind of is to design pci interface voluntarily according to self needs, and another kind of method is to utilize 90 Series PC I chips of present existing pci interface chip such as PLX company to develop for the basis.Preceding a kind of method need redesign whole pci interface, need deep understanding and grasping be arranged to the pci interface agreement, and cycle development time is long, and difficulty is big; Though back a kind of method construction cycle and difficulty have all been improved, the expense of buying chip still can make cost of development rise, and its user interface that provides still can have a few complexity, and this is a cost to obtain relative higher flexibility certainly.Therefore,, reduce the angle that user interface uses difficulty, design one and be easy to user's use, be applicable to vedio data from alleviating the pci interface cost of development, data acquisition, the pci interface that the PCI gigabit networking is used is significant.
Summary of the invention
Therefore, the object of the present invention is to provide multi-usage pci interface under the FPGA environment that a kind of user of being easy to uses, a kind of data transmission method according to this multi-usage pci interface also is provided simultaneously.
According to the present invention, adopt the implementation method of the pci interface of band DMA function, interface is realized being divided into PCI main equipment module, PCI slave unit module, and the PCI register module is realized separately.PCI user side interface is adopted the fifo interface that is simple and easy to realize, the user is hidden DMA control details, reduce the user interface design complexity.In the Large Volume Data transmission, according to the data layout encapsulation of data of interface requirement, simple data are write among the FIFO just can be realized the mode of data with DMA, simplifies the steering logic complexity, improves the efficient of user interface exploitation.Therefore:
According to multi-usage pci interface under the FPGA environment of one aspect of the invention, it comprises:
Register is used for interruption status, address, order and the data of the equipment of temporary described pci interface;
The slave unit module connects described register, and the instruction of acceptance and parse upper layers main frame or DMA, to read and write the information that described register is deposited; And
The main equipment module, connect described register, and be connected to the FIFO read-write interface that is used to connect user side, be used for finishing the DMA interrupt request and data transmit, and echo-plex size and address are in described register according to the interruption status that information comprised, address and the order of the read-write of described slave unit module.
Main equipment module and slave unit module are shared out the work and helped one another, and reduce the burden and the design logic difficulty of single control module.By revising the setting of register, realizes that different numbers will establish transmission, as image data transmission, data acquisition, the application of PCI PCI-Express.The PCI user side adopts the fifo interface of standard, and the user is hidden DMA control details, reduces the user interface design complexity.Adopt the temporary DMA channel number of register, transmission size of data, the data of revising the register correspondence get final product, and do not need the complicated hardware logical design.
Multi-usage pci interface under the above-mentioned FPGA environment, also comprise connect described main equipment module and slave unit module and with pci bus interconnected moderator, with the Access status of the equipment of controlling described pci interface.
Multi-usage pci interface under the above-mentioned FPGA environment also comprises the configuration module that connects with described moderator, and reading the configuration space of pci interface, and response upper strata main frame is to the operation of configuration space.
Multi-usage pci interface under the above-mentioned FPGA environment disposes the storage space that is used for described register expansion.
Data transmission method according to multi-usage pci interface under a kind of FPGA environment of another aspect of the present invention, described pci interface comprises register, slave unit module and is connected to the main equipment module of the fifo interface that is used to be connected user side that this data transmission method may further comprise the steps:
A. it is ready to power on, and wait upper strata main frame disposes pci interface to be finished;
B. slave unit is received instruction, the size of DMA channel number that resolution data transmits and the data that will send and the start address of data to be sent deposit described register then in, if DMA will receive the data commentaries on classics step c1 that host memory sends over,, DMA then changes step c2 if writing data to host memory;
C1. if the transmission enable state that described register is deposited for allowing, is then changeed steps d 2; Otherwise change steps d 1;
D1., the temporary Interface status of described register is set for idle, changes step b;
D2. the channel number, size of data and the described start address that deposit in according to step b of main equipment module sent bus request simultaneously, if bus request success then change step e1, otherwise would change step e2;
E1. from upper strata host memory reading of data, every transmission primaries data are upgraded upper strata host memory start address once to the main equipment module, send the transmission ending signal up to described register according to described start address; If byte number waiting for transmission is non-vanishing, changes steps d 2, otherwise change step b;
E2. the temporary bus of register is a busy condition, changes steps d 2;
C2. the main equipment module is sent data and is arrived interruption, waits for that response of host interrupts; Have no progeny in the response of host to finish to be provided with and wait to transmit data storage to the start address of host memory and send the signal that allows the reception data; Main equipment sends the bus operation request then, if bus request is successfully changeed step f1, otherwise changes step f2;
F1. the main equipment module begins to store data in the start address of described main frame setting, sends the transmission ending signal up to described register; If byte number waiting for transmission is non-vanishing, then changes step c2, otherwise change step b;
F2., it is busy condition that bus is set, and changes step c2.
The data transmission method of multi-usage pci interface under the above-mentioned FPGA environment, described step f1 stores from the storage space that described start address begins to increase to the address.
The data transmission method of multi-usage pci interface under the above-mentioned FPGA environment, described channel number is by being temporarily stored in the binary number record in the register.
The data transmission method of multi-usage pci interface under the above-mentioned FPGA environment, the storage mode of data in FIFO are that unit stores with the bag, and represent interval between data block with packet header and bag tail.
The data transmission method of multi-usage pci interface under the above-mentioned FPGA environment, data transmission procedure are set to suspend and are interrupted, and described register will be noted down size of data and transfer address when suspending.
The data transmission method of multi-usage pci interface under the above-mentioned FPGA environment, the register of the size of storage transmission data adopts 32 bit registers.
Description of drawings
Below in conjunction with Figure of description in detail technical scheme of the present invention is described in detail, wherein:
Fig. 1 is according to multi-usage pci interface theory diagram under a kind of FPGA environment of technical solution of the present invention.
Fig. 2 is the data layout figure according to technical solution of the present invention.
Fig. 3 is PCI DMA host data transmission flow figure.
Fig. 4 is that PCI DMA network data receives process flow diagram.
Embodiment
With reference to multi-usage pci interface under the Figure of description 1 FPGA environment, it comprises:
Register is used for interruption status, address, order and the data of the equipment of temporary described pci interface;
The slave unit module connects described register, and the instruction of acceptance and parse upper layers main frame or DMA, to read and write the information that described register is deposited; And
The main equipment module, connect described register, and be connected to the FIFO read-write interface that is used to connect user side, be used for finishing the DMA interrupt request and data transmit, and echo-plex size and address are in described register according to the interruption status that information comprised, address and the order of the read-write of described slave unit module.
The PCI standard agreement of this programme institute foundation is a kind of by the standard agreement of industry-wide adoption, and its agreement is supported 33MHz and 66MHz bus frequency, supports 32 and 64 two kinds of highway widths; And 16 kinds of bus operation orders are arranged, support simultaneously bus is realized dma operation, realize the transmission of Large Volume Data; For most of system is 32 highway width online situations, recommends to realize under the 33MHz the basic pci interface of 32 bit wides.
The main equipment module functions is when there is the request that sends or receive data in system's (as upper strata main frame), sends interruption, and active request takies pci bus, starts the DMA transmission.In the pci interface, the DMA number of active lanes is set to 16, sends and receive to account for 8 respectively.The slave unit module functions is to realize reading and writing of register according to the instruction of upper strata main frame, changes or obtains the temporary content of register.Main number as the register of controlling is set at 8, and for the ease of later expansion, the storage space of predefine 256K is used for the later expansion of system.
(1) writes the target device operation
At address cycle, the PCI slave unit is oneself according to the target that bus address identifies current operation, and current operation is that IO writes or memory write operation.At cycle data, interface is deposited data to be written as the register of data register, as depositing the register address numbering that decoding is come out the register of address register, provides register write operation useful signal from interface simultaneously.
(2) read the target device operation
At address cycle, the target that the PCI slave unit decodes current operation is oneself, and current operation is that IO reads or memory read operation, sends read signal and reads the address according to the address of address cycle.At cycle data, data are delivered on the pci bus.
(3) DMA transmission control
When PCI equipment sends interrupt request singal and operating system response interruption, system can read the interrupt status register of PCI equipment, the decoding interrupt status register, and relevant register is set, PCI equipment is exactly the equipment that connects by aforesaid fifo interface.
(4) main equipment module operation
Whenever PCI equipment fifo interface receives a packet, will make the bag counting that receives add 1, whenever the PCI main equipment is delivered to pci bus fully with packet, wrap counting and will subtract 1.Needing only the bag counting is not 0 interrupt request of sending data arrival that just continues.
When bus is idle, if DMA receiving register lowest order is 1, then sends bus request signal, and write down the start address of the data that will receive and the size of the data block that will receive.When data of every transmission were to pci bus after the bus request success, the data block size subtracted 1, and the corresponding stored address adds 1; If receiving course interrupts, when bus is idle, ask bus once more and continue to receive data with the address and the data block size of record, be to finish a DMA at 0 o'clock to receive up to the big subtotal figure of data block.
When bus is idle, if the transmitter register lowest order is 1, then sends bus request signal, and write down the start address of the data that will send and the size of the data block that will send.Whenever when pci bus receives data, the data block size subtracts 1 after bus request success, and the address adds 1; If process of transmitting interrupts, when bus is idle, ask bus once more and continue to send data with the current address and the data block size of record, be to finish a DMA at 0 o'clock to send up to the big subtotal figure of data block.
Also comprise connect described main equipment module and slave unit module and with pci bus interconnected moderator, with the Access status of the equipment of controlling described pci interface.
Also comprise the configuration module that connects with described moderator, reading the configuration space of pci interface, and response upper strata main frame is to the operation of configuration space.
According to the data transmission method of multi-usage pci interface under a kind of FPGA environment of said structure,, may further comprise the steps so referring to Figure of description 3 and 4:
A. it is ready to power on, and wait upper strata main frame disposes pci interface to be finished;
B. slave unit is received instruction, the size of DMA channel number that resolution data transmits and the data that will send and the start address of data to be sent deposit described register then in, if DMA will receive the data commentaries on classics step c1 that host memory sends over,, DMA then changes step c2 if writing data to host memory;
C1. if the transmission enable state that described register is deposited for allowing, is then changeed steps d 2; Otherwise change steps d 1;
D1., the temporary Interface status of described register is set for idle, changes step b;
D2. the channel number, size of data and the described start address that deposit in according to step b of main equipment module sent bus request simultaneously, if bus request success then change step e1, otherwise would change step e2;
E1. from upper strata host memory reading of data, every transmission primaries data are upgraded upper strata host memory start address once to the main equipment module, send the transmission ending signal up to described register according to described start address; If byte number waiting for transmission is non-vanishing, changes steps d 2, otherwise change step b;
E2. the temporary bus of register is a busy condition, specially steps d 2;
C2. the main equipment module is sent data and is arrived interruption, waits for that response of host interrupts; Have no progeny in the response of host to finish to be provided with and wait to transmit data storage to the start address of host memory and send the signal that allows the reception data; Main equipment sends the bus operation request then, if bus request is successfully changeed step f1, otherwise changes step f2;
F1. the main equipment module begins to store data in the start address of described main frame setting, sends the transmission ending signal up to described register; If byte number waiting for transmission is non-vanishing, then changes step c2, otherwise change step b;
F2., it is busy condition that bus is set, and changes step c2.
Described step f1 stores from the storage space that described start address begins to increase to the address, and addressing forward just can be saved the resource consumption that the address search table upgrades so greatly.
Described channel number is by being temporarily stored in the binary number record in the register, just adopt the temporary binary data of register to represent channel number, the number that can save logical design, the especially channel number of interface circuit greatly depends on and is provided with the figure place of register very convenient.
Preferably, the storage mode of data in FIFO is that unit stores with the bag, and represents interval between data block to be convenient to the transmission of data and defining of size of data with packet header and bag tail, and decision data begins to transmit the state with end of transmission especially easily.
Data transmission procedure set to suspend interrupts, and described register will note down size of data and transfer address when suspending, is convenient to the response to other interruptions.
The register of the size of storage transmission data adopts 32 bit registers, supports the transmission of the packet of 4G, satisfies the needs of most data transmission.
The user side interface signal is described below so:
The PCI protocol interface module mainly is made up of 5 submodules: slave unit module, configuration space module, register module, main equipment module and moderator module.The signal relation of intermodule is shown in Figure of description 1:
The slave unit module is mainly finished the function of PCI slave unit, and the data that main frame mail to PCI MENORY space are carried out the setting of command analysis and control register;
The configuration space module is mainly finished the setting of pci configuration space, and respective host is to the operation of pci configuration space;
Register module is mainly stored the control signal of main equipment module, the host memory address that the DMA transmission time is used, and the size and the channel number of transmission data, and main equipment module feedack responded;
The main equipment module is mainly finished the function of PCI main equipment, comprises bus request, interrupt to produce, and the memory read of bus and memory write function, and be provided to the interactive signal of asynchronous read and write FIFO;
Arbitration modules is then being controlled the visit of pci interface, judge in all the other several modules which module can with the pci bus interaction data.
DMA (Direct Memory Access, i.e. direct memory visit).In the DMA file delivery procedure, information according to table 1 register can obtain transmitting the byte number of data and the start address of data, can determine to transmit the counting of counter according to these information, can determine according to the state in control register and the interrupt status register whether this data block can transmit again, so just can when transmit and finish according to the count value judgment data that transmits counter.
Table 1 PCI IP kernel register functions is described
| Register name | The address | Functional description |
| Intr_mask_reg | 0x00000A10 | The interrupt mask register is used for shielding some interruption status position of PCI |
| Intr_stat_reg | 0x00000A14 | Interrupt status register, the combination of the interrupt identification in the PCI equipment |
| Dma_start_t_reg | 0x00000A14 | DMA transmits the start address register, and this address is corresponding with host memory address |
| Dma_size_t_reg | 0x00000A1C | DMA sends the byte number register, and the PCI main equipment utilizes this information decision dma operation when to finish |
| Dma_ctrl_t_reg | 0x00000A24 | DMA transmit control register, PCI main equipment are initiated the pci bus read operation according to the control signal of this register.Data are read from the host memory data |
| Dma_start_r_reg | 0x00000A10 | DMA receives the start address register, and this address is corresponding with host memory address |
| Dma_size_r_reg | 0x00000A18 | DMA receives the byte number register, and the PCI main equipment utilizes this information decision dma operation when to finish |
| Dma_ctrl_r_reg | 0x00000A20 | DMA receives control register, and the PCI main equipment is initiated the write operation of pci bus according to the control signal of this register.Data are write host memory |
Operation steps and content that DMA transmits file comprise:
When PCI equipment sent interrupt request singal and operating system response interruption, operating system can read the interrupt status register of PCI equipment.
Equipment movement program decoding interrupt operation according to PCI equipment is provided with relevant register.
When system will send data, operating system writes the first address of data to be sent place host memory earlier to dma_start_t_reg, write the byte number of the data that the dma_size_t_reg register will send then, write DMA of dma_ctrl_t_reg control PCI device start at last and send request.
Can send one and be sent completely interrupt request after the DMA of PCI transmit operation is finished, the operating system response is interrupted.
When PCI receives the data that FIFO sends here, the dma_size_r_reg register is set, and sends interrupt request; The operating system response is interrupted, and the dma_start_r_reg register is set, and the dma_ctrl_r_reg register is set then starts a DMA reception operation.
After finishing, the reception operation sends interrupt request equally.Wherein, everybody functional description of interrupt status register (intr_stat_reg) is as shown in table 2:
Table 2 interrupt status register bit function is described
| The | Function | |
| 0 | The |
|
| 1 | The DMA error of transmission | |
| 2 | The DMA transmission is |
|
| 3 | Data arrive | |
| 4 | Data transmit and finish | |
| 5 | Data are sent completely | |
| 6 | Parity error | |
| 7-31 | Keep |
Concrete data layout is represented as shown in Figure 2:
As ctrl[7:0] when being 8 ' hFF, the beginning of a packet of expression, data[40:32] storing current data and be surrounded by how many words (32), data[12:0] then storing current data and be surrounded by how many words, data[19:16] channel number (16 passages are arranged) under the current data packet stored; Ctrl is 8 ' h00 then, and what expression was transmitted is normal data; At last, when having and having only one to be 1 among the ctrl, represent the end of a frame, and a last valid data byte has been indicated in 1 position.
According to as above data packet format, following operation steps is arranged at fifo interface:
Initialization FIFO is empty, waits pending data to arrive.
When the data Ctrl that receives was 8 ' hFF, expression packet head arrived, and begins data are write among the FIFO.
When any non-zero was arranged in finding Ctrl, expression arrived the packet end, stops to write data to FIFO.
Wait for the arrival of next packet head.
This fifo interface that is simple and easy to usefulness is applicable to that with bag or frame be the Data Transmission Controlling of unit, as the frame of data link layer in the network transmission process, and each frame video in the video data etc.
Whole PCI logic control interface uses the hardware programming language to realize, realizes the DMA data transmission of 16 passages, is easy to be integrated in the programmable chip, simplifies the control procedure of pci interface, shortens system development cycle.
First Input First Output (First Input First Output, FIFO) this is a kind of traditional manner of execution according to the order of sequence, the instruction that is introduced into is finished earlier and is retired from office, and and then just carries out the second instruction.FIFO generally is used for the data transmission between the different clock-domains, AD data acquisition during such as the end of FIFO, the pci bus of other end computer-chronograph, suppose that the speed that its AD gathers is 16 100K SPS, the data volume of per second is 100K * 16bit=1.6Mbps so, and the speed of pci bus is 33MHz, highway width 32bit, its peak transfer rate is 1056Mbps, just can adopt FIFO to be used as data buffering between two different clock zones.Also can use FIFO for the data-interface of different in width in addition, for example monolithic seat in the plane 8 bit data output, and DSP may be the inputs of 16 bit data, just can use FIFO to reach the purpose of Data Matching when single-chip microcomputer is connected with DSP.
Claims (10)
1. multi-usage pci interface under the FPGA environment is characterized in that it comprises:
Register is used for interruption status, address, order and the data of the equipment of temporary described pci interface;
The slave unit module connects described register, and the instruction of acceptance and parse upper layers main frame or DMA, to read and write the information that described register is deposited; And
The main equipment module, connect described register, and be connected to the FIFO read-write interface that is used to connect user side, be used for finishing the DMA interrupt request and data transmit, and echo-plex size and address are in described register according to the interruption status that information comprised, address and the order of the read-write of described slave unit module.
2. multi-usage pci interface under the FPGA environment according to claim 1 is characterized in that: also comprise connect described main equipment module and slave unit module and with pci bus interconnected moderator, with the Access status of the equipment of controlling described pci interface.
3. multi-usage pci interface under the FPGA environment according to claim 2 is characterized in that: also comprise the configuration module that connects with described moderator, reading the configuration space of pci interface, and response upper strata main frame is to the operation of configuration space.
4. according to multi-usage pci interface under the arbitrary described FPGA environment of claim 1 to 3, it is characterized in that: dispose the storage space that is used for described register expansion.
5. the data transmission method of multi-usage pci interface under the FPGA environment, it is characterized in that: described pci interface comprises register, slave unit module and is connected to the main equipment module of the fifo interface that is used to be connected user side that this data transmission method may further comprise the steps:
A. it is ready to power on, and wait upper strata main frame disposes pci interface to be finished;
B. slave unit is received instruction, the size of DMA channel number that resolution data transmits and the data that will send and the start address of data to be sent deposit described register then in, if DMA will receive the data commentaries on classics step c1 that host memory sends over,, DMA then changes step c2 if writing data to host memory;
C1. if the transmission enable state that described register is deposited for allowing, is then changeed steps d 2; Otherwise change steps d 1;
D1., the temporary Interface status of described register is set for idle, changes step b;
D2. the channel number, size of data and the described start address that deposit in according to step b of main equipment module sent bus request simultaneously, if bus request success then change step e1, otherwise would change step e2;
E1. from upper strata host memory reading of data, every transmission primaries data are upgraded upper strata host memory start address once to the main equipment module, send the transmission ending signal up to described register according to described start address; If byte number waiting for transmission is non-vanishing, changes steps d 2, otherwise change step b;
E2. the temporary bus of register is a busy condition, changes steps d 2;
C2. the main equipment module is sent data and is arrived interruption, waits for that response of host interrupts; Have no progeny in the response of host to finish to be provided with and wait to transmit data storage to the start address of host memory and send the signal that allows the reception data; Main equipment sends the bus operation request then, if bus request is successfully changeed step f1, otherwise changes step f2;
F1. the main equipment module begins to store data in the start address of described main frame setting, sends the transmission ending signal up to described register; If byte number waiting for transmission is non-vanishing, then changes step c2, otherwise change step b;
F2., it is busy condition that bus is set, and changes step c2.
6. the data transmission method of multi-usage pci interface under the FPGA environment according to claim 5 is characterized in that: described step f1, store from the storage space that described start address begins to increase to the address.
7. the data transmission method of multi-usage pci interface under the FPGA environment according to claim 5 is characterized in that: described channel number is by being temporarily stored in the binary number record in the register.
8. the data transmission method of multi-usage pci interface under the FPGA environment according to claim 5 is characterized in that: the storage mode of data in FIFO is that unit stores with the bag, and represents interval between data block with packet header and bag tail.
9. the data transmission method of multi-usage pci interface under the FPGA environment according to claim 5 is characterized in that: data transmission procedure is set to suspend and is interrupted, and described register will be noted down size of data and transfer address when suspending.
10. the data transmission method of multi-usage pci interface under the FPGA environment according to claim 5 is characterized in that: the register of the size of storage transmission data adopts 32 bit registers.
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| CN102497544B (en) * | 2011-12-15 | 2014-06-25 | 中国科学院自动化研究所 | Device for controlling access to video signals |
| CN102833131A (en) * | 2012-08-27 | 2012-12-19 | 济南大学 | System and method for test and comparison of remote database response performance |
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| CN103106166B (en) * | 2012-12-22 | 2016-02-17 | 中国船舶重工集团公司第七0九研究所 | A kind of agreement has nothing to do, can support the PCIE IP kernel user logic Interface Expanding method of target read-write operation |
| CN103106166A (en) * | 2012-12-22 | 2013-05-15 | 中国船舶重工集团公司第七0九研究所 | Peripheral component interface express (PCIE) internet protocol (IP) core user logic interface design method unrelated to protocol and capable of supporting target read-write operation |
| CN103530211A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE loop back self-test method based on UVM platform |
| CN103530211B (en) * | 2013-10-12 | 2017-10-03 | 丁贤根 | A kind of method of the PCIE winding Autonomous tests based on UVM platforms |
| CN103685578B (en) * | 2014-01-08 | 2017-08-04 | 珠海全志科技股份有限公司 | The data transmission method of master-slave equipment |
| CN103729165A (en) * | 2014-01-16 | 2014-04-16 | 哈尔滨工业大学 | PCI (peripheral component interconnect) slave unit core control module applied to high-speed motion control system |
| CN106557340A (en) * | 2015-09-29 | 2017-04-05 | 中兴通讯股份有限公司 | A kind of collocation method and device |
| CN109039329A (en) * | 2017-06-12 | 2018-12-18 | 株式会社村田制作所 | Retransmission unit and control system |
| CN108829622A (en) * | 2018-09-06 | 2018-11-16 | 易思维（杭州）科技有限公司 | Communication structure and the means of communication based on the FPGA host computer realized and InterBus module |
| CN112559402A (en) * | 2020-12-23 | 2021-03-26 | 广东高云半导体科技股份有限公司 | PCI slave interface control circuit based on FPGA and FPGA |
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