WO2023226845A1 - Image data transmission method and apparatus, and electronic device - Google Patents

Abstract

The present application belongs to the technical field of communications. Disclosed are an image data transmission method and apparatus, and an electronic device. The method comprises: acquiring image data format information; determining an address offset according to the image data format information; acquiring header address information for each instance of transmission of image data; and transmitting the image data according to the header address information for each instance of transmission and the address offset, wherein once each row of image data is transmitted, a header address of the row is used in combination with the address offset, so as to skip to the header address of the next row to transmit the next row of image data.

Description

Image data transmission method, device and electronic equipment

Cross-references to related applications

This application claims priority from Chinese Patent Application No. 202210573879.3 filed in China on May 24, 2022, the entire content of which is incorporated herein by reference.

Technical field

The present application belongs to the field of communication technology, and specifically relates to an image data transmission method, device and electronic equipment.

Background technique

In some scenarios, the image processing module processes image data in units of pixel blocks as needed, while the image data collected by the camera is transmitted and stored in rows. When using the high-performance scalable interface (Advanced eXtensible Interface, AXI) to transport image data, the first address of each burst transmission needs to be set according to the way the data in the memory is stored in rows, but at the same time it needs to be set according to the required Make necessary adjustments to the format of the data block.

In one method, it is assumed that a burst of data is transmitted for 8 clocks, which is equivalent to reading 64 pixels of data in a row each time. These data are stored in a continuous interval starting from the specified address, but this method requires the preparation of additional data. Storage space, back up the read data of 64 pixels per row, and then convert it into 8×8 data blocks for processing; in another way, assuming that a burst transmission only processes the data of 1 clock, which is equivalent to Read the data of 8 pixels in one row each time, then send the storage address of the next row of data through the address channel, and continue to read the data of 8 pixels in the next row, but this method requires sending the address information multiple times to read each row. The data of 8 pixels is composed of an 8×8 data block, causing the overall transmission efficiency to be too low.

It can be seen that in the related art, when image data blocks are transmitted, there is a problem of low transmission efficiency without increasing the cache storage space.

Contents of the invention

The purpose of the embodiments of the present application is to provide an image data transmission method, device and electronic equipment that can solve the problem of low transmission efficiency in the related art when image data blocks are transmitted without increasing cache storage space.

In a first aspect, embodiments of the present application provide an image data transmission method, which method includes:

Get image data format information;

Determine the address offset according to the image data format information;

Obtain the first address information of each transmission of image data;

The image data is transmitted according to the first address information and the address offset of each transmission, wherein, after each row of image data is transmitted, the first address of the row is added to the address offset to skip. Go to the first address of the next line and transmit the next line of image data.

In a second aspect, embodiments of the present application provide an image data transmission device, including:

The first acquisition module is used to acquire image data format information;

The first determination module is used to determine the address offset according to the image data format information;

The second acquisition module is used to obtain the first address information of each transmission of image data;

A transmission module, configured to transmit image data according to the first address information of each transmission and the address offset, wherein, after each row of image data is transmitted, the first address of the row plus the address offset is used. Shift to jump to the first address of the next line and transmit the next line of image data.

In a third aspect, embodiments of the present application provide an electronic device. The electronic device includes a processor and a memory. The memory stores programs or instructions that can be run on the processor. The programs or instructions are processed by the processor. When the processor is executed, the steps of the image data transmission method described in the first aspect are implemented.

In the fourth aspect, embodiments of the present application provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the programs or instructions are executed by a processor, the image data transmission as described in the first aspect is implemented. Method steps.

In a fifth aspect, embodiments of the present application provide a chip. The chip includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the first aspect. The image data transmission method.

In a sixth aspect, embodiments of the present application provide a computer program product. The program product is stored In the storage medium, the program product is executed by at least one processor to implement the image data transmission method as described in the first aspect.

In the embodiment of the present application, the image data format information is obtained; the address offset is determined according to the image data format information; the first address information of each transmission of the image data is obtained; and the first address information of each transmission is obtained and the The address offset is used to transmit image data. After each line of image data is transmitted, the first address of the line is added to the address offset to jump to the first address of the next line and the next line of image is transmitted. data. In this way, by determining the address offset, it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.

Description of the drawings

Figure 1a is one of the schematic diagrams of the AXI bus transmitting image data with different burst transmission lengths provided by the embodiment of the present application;

Figure 1b is the second schematic diagram of the AXI bus transmitting image data with different burst transmission lengths provided by the embodiment of the present application;

Figure 2 is an example diagram of image processing from the upper left to the lower right in units of 8×8 pixel blocks provided by the embodiment of the present application;

Figure 3 is an example diagram of the image data of the camera provided by the embodiment of the present application being transmitted and stored in units of one line;

Figure 4 is an example diagram in which the JPEG image compression provided by the embodiment of the present application is processed in units of 8×8 pixel blocks;

Figure 5 is an example diagram in which the AXI bus provided by the embodiment of the present application jumps in each row to transmit image data to meet the format requirements of the pixel block;

Figure 6 is a flow chart of an image data transmission method provided by an embodiment of the present application;

Figure 7 is a schematic diagram of the AXI address space mapping module in the data flow provided by the embodiment of this application;

Figure 8 is a schematic diagram of the AXI address space mapping module provided by the embodiment of this application;

Figure 9 The embodiment of this application provides address mapping based on AXI address information and continuously reads 8 lines. Example plot of image data;

Figure 10 is a schematic structural diagram of an image data transmission device provided by an embodiment of the present application;

Figure 11 is a schematic diagram of the module structure of the electronic device provided by the embodiment of the present application;

Figure 12 is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first," "second," etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the related objects are in an "or" relationship.

In order to make the embodiments of the present application clearer, the technical background of the embodiments of the present application is briefly introduced below in conjunction with several examples:

During the image processing process of the image processing chip, in some scenarios, image data needs to be processed in the form of image data blocks. For example, Figure 2 is an example of processing from the upper left to the lower right of the image in units of 8×8 data blocks.

The image data collected by the camera is transmitted in units of each line of data according to the Camera Serial Interface 2 (CSI-2) specification. When the image data transmitted from the camera is saved to the memory, it is generally saved line by line in the manner recommended by the specification. After all the data in one line is stored, the next line is saved. For example, in Figure 3, the entire row of data in the first row is processed first, then the data in the next row is processed, and then the data in the third row is processed, row by row from the upper left to the lower right.

During the processing of image data by the image processing chip, the image data will be transmitted and processed between different modules, as well as between modules and memories as needed.

The AXI bus is a widely used bus protocol for data transmission between the chip's internal processing module and memory. When image data blocks are transmitted between the image processing module and the memory, the AXI bus is often used for data transmission. For example, image data is read from the memory and sent to the image processing module for processing, or image data output by the image processing module is written into the memory.

The AXI bus has an address channel and a data channel. The address channel specifies the first address of the memory to be accessed. The data channel continuously writes or reads data in sequence from the first address set by the address channel. In burst transmission mode, data of multiple clock cycles can be transmitted on the data channel to improve the efficiency of data transmission.

Among them, the Joint Photographic Experts Group (JPEG) image processing module is an example of processing image data according to data blocks. JPEG is a widely used still image compression standard. In standard mode, as shown in Figure 4 As shown in the figure, the compressed image is processed in units of 8×8 pixel blocks, from the upper left to the lower right of the image. Color space YCbCr Depending on the image data type, the pixel block unit processed may also be 16×8 (YCbCr=4:2:2) or 16×16 (YCbCr=4:2:0), etc., but each component is Processing will be done in units of 8×8 pixel blocks. Of course, the method mentioned in this application is not only applicable to JPEG, but also to all modules that need to process data according to image data blocks.

When using the AXI bus to transport image data, the first address of each burst transmission needs to be set according to the way the data in the memory is stored in rows, but at the same time, necessary adjustments need to be made according to the format of the required data block. The following description takes an 8×8 data block as an example. Other data blocks can also be processed in a similar manner.

For example, when processing the 8×8 data block in the upper left corner in Figure 5, the AXI bus must first read the 8 pixel data in row 1 starting from column 1, and then jump to transmit the 8 pixels in row 2 starting from column 1. pixels of data, and so on until the 8 pixels of data starting from the 8th row and 1st column are transmitted. When the 8 pixel data of rows 1 to 8 are all transmitted, the data transmission of the 8×8 pixel block is completed.

The pixel depth of image data has various specifications such as 8, 10, 12, 14, and 16. AXI data channel The data bit width is currently 64 or 128 bits, and burst transmission can perform data transmission of multiple clocks such as 4, 8, 16, etc.

Figure 1a and Figure 1b are simple example diagrams of AXI reading image data. Taking the pixel depth of image data as an 8-bit depth as an example, the data of 8 pixels in a row is 64 bits. Assuming that the data bit width of AXI is 64 bits, then to transmit image data with 8 bit depth and 8 pixels per line, only one clock transmission is required for each burst transmission. In Figure 1a, AXI transmits 8 clocks of data in a burst, which is equivalent to reading 64 pixels of data in a row each time. These data are stored in the continuous interval starting from the specified address; while the burst transmission in Figure 1b only Processing the data of 1 clock is equivalent to reading the data of 8 pixels in one row at a time, then sending the storage address of the next row of data through the address channel, and continuing to read the data of the next row of 8 pixels.

From the examples in Figure 1a and Figure 1b, it can be seen that multiple data can be read in one burst transmission using the method in Figure 1a, which can improve the efficiency of AXI data transmission, but it requires additional data storage space to be read. The data of 64 rows of pixels is backed up, and then converted into 8×8 data blocks and sent to the image processing module for processing. If the method in Figure 1b is used, only 8 pixels of data in each row are read in each burst transmission, and the 8 pixels of data required in each row are read by sending address information multiple times to form an 8×8 Data block, but at this time each burst transmission only transmits one clock cycle and address information needs to be transmitted each time. The overall transmission efficiency is too low.

The embodiments of this application provide a solution for efficiently transmitting image data blocks based on the order in which the image data blocks are processed and stored in the memory, as well as the transmission characteristics of the AXI address and data channel, thereby achieving the goal of eliminating the need for additional cache storage. While using space, the purpose is to improve the efficiency of image data block transmission.

The image data transmission method provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.

Please refer to Figure 6. Figure 6 is a flow chart of an image data transmission method provided by an embodiment of the present application. As shown in Figure 6, the method includes the following steps:

Step 601: Obtain image data format information.

The embodiment of the present application can be applied to the scenario of transmitting image data blocks on the AXI bus.

In the embodiment of this application, according to the first address information specified by the AXI address channel, the actual access When memory is used, the address mapping space is converted. After reading the pixel data required for each row of data, the address jumps to the address of the next row of data and continues to read the pixel data required for the next row, thereby achieving continuous reading of image data processing. The data for the required data block.

Specifically, as shown in Figure 7, an AXI address space mapping module can be added between the AXI bus data transmission processing module and the register. When the AXI bus data transmission processing module accesses the memory, the address space mapping is performed, thereby continuously reading Get the data of the data block required by the image processing module. Among them, the internal structure diagram and data flow information of the AXI address space mapping module can be shown in Figure 8.

In order to realize the mapping of the address space, the image data format information can first be obtained to determine the address offset based on the image data format information. Specifically, relevant image data format information, such as the size of the transmitted image data block, pixel depth, and the number of pixels in each row, can be obtained during the initial configuration.

For example, when initializing and configuring related modules including the image processing module at the application layer, the AXI address space mapping module also obtains image data format information, including image data block size, data type, pixel depth, and pixels for each row. Number, address space to store each pixel component of each row, etc.

Step 602: Determine the address offset according to the image data format information.

Based on the obtained image data format information, the AXI address mapping module can calculate the number of clocks required to complete the transmission of pixel data required for each row, and the address offset of each row of image data in the memory, that is, the pixels required for each row After the data is transferred, the address required to jump to the next line is used. In addition, depending on the image data type, the Y/Cb/Cr components can be similarly processed by component.

Optionally, the image data format information includes pixel depth and the number of pixels in each line;

The step 602 includes:

The address offset is determined based on the product of the pixel depth and the number of pixels in each row.

That is, in one implementation, the image data format information includes the pixel depth and the number of pixels in each row, then the address offset can be determined based on the product of the pixel depth and the number of pixels in each row.

For example, if the pixel depth of the image is 8 bits, each row of the image has 128 pixels, the data of each pixel component is stored in a designated address space, and the pixels of each row are stored continuously, then It can be determined that the amount of data in one line of each pixel component is 8 bits Shift 1024 bits, that is, add 1024 bits to the first address, and then transmit the next line of image data.

In this way, through this implementation, when pixels in each row are stored continuously, the address offset can be quickly determined based on the product of the pixel depth and the number of pixels in each row, thereby achieving continuous transmission of multiple rows of image data.

Optionally, the image data format information includes address space information occupied by pixels in each row;

Determining the address offset according to the image data format information includes:

Determine the address space size of each row according to the address space information occupied by the pixels in each row;

The address space size of each row is determined as the address offset.

In another implementation, the image data format information may include address space information occupied by each row of pixels, that is, when the pixels of different rows of each component are not stored in continuous address intervals without interruption, but each row is designated. When the address space is one row, the address offset can be directly determined based on the address space size of each row.

For example, instead of storing pixels in different rows of each component in a 1024-bit continuous address range, each row is specified to have a 2048-bit address space, then each row will only occupy the specified 2048-bit address. The first 1024 bits of the space, so when jumping to the next line of transmission, an offset of 2048 bits needs to be added, and the address offset can be determined to be 2048 bits.

In this way, through this implementation, when the pixels in each row are not stored continuously, the address offset can be determined based on the specified address space size occupied by the pixels in each row, thereby achieving continuous transmission of multiple rows of image data.

Step 603: Obtain the first address information of each transmission of image data.

In this step, the AXI address space mapping module can obtain the first address of each burst transmission from the AXI bus address channel. The transmission includes reading memory data or writing data to the memory. It should be noted that in the embodiment of the present application, data of one or more clock cycles can be transmitted at a time. One image data block includes multiple lines of data. The transmission of one line of data requires one or more clock cycles. Depending on the number of clock cycles for one transmission, the number of times required to complete the transmission of an image data block is also different. When the number of clock cycles in one transmission can transmit one image data block, only one burst transmission is required to transmit one image data block. When the number of clock cycles in one transmission can only transmit several lines in one image data block, Transmitting a block of image data requires multiple burst transfers.

Optionally, before step 603, the method further includes:

Determine the number of clock cycles for each transmission and processing of image data;

The step 603 includes:

Determine the number of transmissions required to transmit one image data block according to the number of clock cycles and the image data block size and transmission data bit width in the image data format information;

Obtain the first address information of each transmission in the number of transmissions.

In one implementation, the number of transmissions required to transmit an image data block can be determined based on the number of clock cycles of each burst transmission, the size of the image data block and the transmission data bit width, and then the number of transmissions required for each transmission can be obtained based on the number of transmissions. First address information.

Specifically, the number of clock cycles for each burst transmission processing of AXI can be determined. This information can usually be preset by the system, and then the number of clock cycles for one transmission processing, image data block size information and transmission data bit width can be determined. The number of data lines that can be transmitted by burst transmission, and then the number of transmissions required to transmit an image data block is calculated.

For example, assume that the image data block size is 8×8, the data bit width of AXI and memory is 64 bits, and the image pixel depth is 8 bits. At this time, each clock cycle processes 64 bits of data, which is equivalent to 8 pixels of data. quantity, that is to say, one row of data can be processed in one clock cycle. If AXI handles 4 clock cycles per burst transfer, then 4 lines of data can be transferred at one time, and it takes 2 transfers to transfer an 8×8 image data block. In this way, starting from the first address specified by the first burst transmission, the first clock cycle transmits the data of 8 pixels of the specified row, then adds the 1024-bit offset to the first address, and reads the 8 pixels of the next row. of data, and so on to read 8 pixels each of 4 lines of data. After that, AXI sends the first address of the fifth row again through the address channel, starts the second transmission, continues to read the subsequent 4 rows of data, and completes the reading of the 8×8 data block.

If AXI processes 8 clock cycles for each burst transfer, then AXI only needs to send address information once to read 8 lines of data, that is, one image data block only needs to be transferred once.

In this way, through this implementation, the number of transmissions required to transmit an image data block can be determined, and the first address information of each transmission can be obtained to ensure the smooth progress of image data transmission.

Further, determining the number of transmissions required to transmit an image data block based on the number of clock cycles and the image data block size and transmission data bit width in the image data format information includes:

Determine the number of pixels processed in each clock cycle according to the pixel depth, the image data block size and the transmission data bit width in the image data format information;

The number of transmissions required to transmit one image data block is determined based on the number of pixels processed per clock cycle and the number of clock cycles.

In this embodiment, the image data format information may include pixel depth, image data block size and transmission data bit width, so that the processing of each clock cycle can be determined based on the pixel depth, image data block size and transmission data bit width. The number of pixels processed per clock cycle and the number of clock cycles processed in one transmission can be combined to determine the number of transmissions required to transmit an image data block.

For example, assuming that the image data block size is 8×8, the data bit width of AXI and memory is 64 bits, and the image pixel depth is 8 bits, each clock cycle can process 64 bits of data, which is equivalent to the amount of data of 8 pixels. , that is to say, one row of data can be processed in one clock cycle. If AXI handles 4 clock cycles per burst transfer, then 4 lines of data can be transferred at one time, and it takes 2 transfers to transfer an 8×8 image data block.

If the image pixel depth is 16 bits, then the 64-bit data processed by each clock is only equivalent to the amount of data of 4 pixels. At this time, each row of 8 pixels of data requires 2 clock cycles to be processed. If AXI handles 4 clock cycles per burst transfer, then only 2 lines of data can be transferred at a time, and 4 times are required to transfer an 8×8 image data block.

In this way, through this implementation, the number of transmissions required to transmit one image data block can be determined more accurately.

Step 604: According to the first address information of each transmission and the address offset, perform a graph Image data transmission, wherein after each line of image data is transmitted, the first address of the line plus the address offset is used to jump to the first address of the next line to transmit the next line of image data.

In this step, the image data transmission module in the AXI address space mapping module transmits image data according to the memory address specified by the address space mapping.

Specifically, in the embodiment of the present application, when actually accessing the memory, the address space mapping is performed according to the characteristics of the image data block being processed, and the data required by the current row is processed starting from the first address, instead of following the default continuous increment method of the AXI bus. After the pixel data, according to the address offset, jump to the address of the next row (that is, the address of the next row = the starting address of the previous row + the address offset of one row of data), and continue to process the pixel data required for the next row. Process all transfer clocks row by row until completion of a burst transfer. Then, based on the first address information and address offset of the next transmission, similar line-by-line processing is performed until the data of one image data block is transmitted.

Optionally, step 604 includes:

According to the first address information of the i-th transmission, the image data of the j-th row where the first address information is located is transmitted, i is an integer greater than or equal to 1, and j is a positive integer;

Add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row;

Transmit the image data of the j+1th row according to the first address information of the j+1th row;

Wherein, every time a row of image data is transmitted, the first address of the row is added to the address offset, and the image data transmission of the next row is started until the i-th transmission is completed.

That is, when transmitting image data based on the first address information and address offset of each transmission, for the i-th burst transmission, the row where the first address information is located can be transmitted based on the first address information of the i-th transmission. After completing the image data transmission of this row, you can add the address offset to the first address of the i-th transmission and jump to transmit the image data of the next row, and so on, each time a row of image data is transmitted , add the address offset to the address of the row, and transmit the image data of the next row until the i-th transmission is completed. In the case that the i-th transmission is not the last transmission, the first address information of the i+1th transmission can be obtained, and the i+1th transmission is completed in a similar manner to the i-th transmission until one image data block is completed. transmission.

In this way, through this implementation, it is ensured that each image data transmission is completed in order.

It should be noted that, for a scenario where multiple image data blocks need to be transmitted, each image data block can be transmitted in sequence according to the transmission method of one image data block introduced in the embodiment of this application.

Assume that the image data block size is 8×8, the data bit width of AXI and memory is 64 bits, the image is 8 bits deep, each line of the image has 128 pixels, and the data of each pixel component is stored in the specified address space. And the pixels of each row are stored continuously. At this time, each clock cycle processes 64 bits of data, which is equivalent to the amount of data of 8 pixels. The data amount of one row of each pixel component is 8 bits × 128 pixels = 1024 bits.

If AXI processes 4 clock cycles for each burst transfer, then starting from the specified first address, the first clock cycle transmits the data of 8 pixels of the specified row, then the first address is added to the 1024-bit offset, and the next read One line of 8 pixels of data, and so on, read 4 lines of data of 8 pixels each. After that, AXI sends the first address of the fifth row again through the address channel, continues to read the subsequent 4 rows of data, and completes the reading of the 8×8 data block.

If AXI handles 8 clock cycles per burst transfer, then AXI only needs to send address information once to read 8 rows of data.

If the depth of the image is 16 bits under the above conditions, and other conditions remain unchanged, then the 64-bit data processed by each clock is only equivalent to the amount of data of 4 pixels. At this time, 8 pixels of data per row require 2 clocks. Processing completed.

If in the above conditions, the pixels of different rows of each component are not stored uninterruptedly in a 1024-bit continuous address range, but each row is specified to have a 2048-bit address space, then each row will occupy only The first 1024 bits of the specified 2048-bit address space, so when jumping to the next line, an offset of 2048 bits needs to be added.

It should be noted that the actual address mapping control can be adjusted in more combinations according to system needs, but the idea of address mapping to jump by row to read the required data block unit is consistent. There is no additional explanation on the right edge, bottom edge of the image, etc. The system can be adjusted as needed during system implementation. If the image processing module and the AXI bus have an asynchronous clock relationship, the data caching required for the intermediate cross-clock domain processing is not described here.

In conjunction with Figure 9, an example diagram of 8×8 data block processing is used to illustrate the difference between the implementation of the embodiment of the present application and the existing technology. It is assumed here that the data bit width of AXI and memory is 64 bits, and the image is 8 bits deep. , burst transfer reads data for 8 clock cycles each time. In the example in Figure 9, starting from the address of the first row, AXI will increase the address by default and continuously read the data of 64 pixels in the first row. In the example in Figure 9, through address mapping processing, after reading the data of 8 pixels in the first row, the next clock cycle will jump to the address of the second row to read the 8 pixels in the second row. By analogy, 8 pixels of each of the 8 rows of data are read to form an 8×8 data block. In this way, only one burst transmission is needed to complete the processing of an 8×8 data block, and the transmission efficiency is greatly improved.

The embodiment of the present application adds an AXI address space mapping module between the AXI bus data transmission processing module and the memory, and performs address space mapping when the AXI bus processing module accesses the memory, thereby achieving continuous reading of the data of the data blocks required for image processing. , to achieve the purpose of improving the efficiency of image data block transmission based on AXI bus transmission without increasing the storage space for cache.

The image data transmission method in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address of each transmission. The address information and the address offset are used to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row. Transfer the next line of image data. In this way, by determining the address offset, it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.

For the image data transmission method provided by the embodiments of the present application, the execution subject may be an image data transmission device. In the embodiment of the present application, an image data transmission device performing an image data transmission method is used as an example to illustrate the image data transmission device provided by the embodiment of the present application.

Please refer to Figure 10, which is a schematic structural diagram of an image data transmission device provided by an embodiment of the present application. As shown in Figure 10, the image data transmission device 1000 includes:

The first acquisition module 1001 is used to acquire image data format information;

The first determination module 1002 is used to determine the address offset according to the image data format information;

The second acquisition module 1003 is used to acquire the first address information of each transmission of image data;

The transmission module 1004 is used to transmit image data according to the first address information of each transmission and the address offset. Wherein, after each row of image data is transmitted, the first address of the row is added to the address. Offset to jump to the first address of the next line and transmit the next line of image data.

Optionally, the image data format information includes pixel depth and the number of pixels in each line;

The first determining module 1002 is configured to determine the address according to the product of the pixel depth and the number of pixels in each row.

Optionally, the image data format information includes address space information occupied by pixels in each row;

The first determination module 1002 includes:

A first determination unit configured to determine the address space size of each row based on the address space information occupied by the pixels of each row;

A second determination unit is configured to determine the address space size of each row as the address offset.

Optionally, the image data transmission device 1000 also includes:

The second determination module is used to determine the number of clock cycles for each transmission and processing of image data;

The second acquisition module 1003 includes:

A third determination unit configured to determine the number of transmissions required to transmit an image data block based on the number of clock cycles and the image data block size and transmission data bit width in the image data format information;

The obtaining unit is used to obtain the first address information of each transmission in the number of transmissions.

Optionally, the third determining unit includes:

A first determination subunit configured to determine the number of pixels processed in each clock cycle based on the pixel depth in the image data format information, the image data block size and the transmission data bit width;

The second determination subunit is configured to determine the number of transmissions required to transmit an image data block based on the number of pixels processed per clock cycle and the number of clock cycles.

Optionally, the transmission module 1004 includes:

The first transmission unit is used to transmit the image data of the j-th row where the first address information is located according to the first address information transmitted in the i-th time, where i is an integer greater than or equal to 1, and j is a positive integer;

The second transmission unit is used to add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row;

Transmit the image data of the j+1th row according to the first address information of the j+1th row;

Wherein, every time a row of image data is transmitted, the first address of the row is added to the address offset, and the image data transmission of the next row is started until the i-th transmission is completed.

The image data transmission device in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address of each transmission. The address information and the address offset are used to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row. Transfer the next line of image data. In this way, by determining the address offset, it can automatically jump to the transmission address of the next line of image data based on the first address information and address offset during transmission, thereby achieving continuous transmission of multiple lines of image data without increasing cache storage. While saving space, it improves the transmission efficiency of image data blocks.

The image data transmission device in the embodiment of the present application may be an electronic device or a component in the electronic device, such as an integrated circuit or chip. The electronic device may be a terminal or other devices other than the terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle-mounted electronic device, a mobile Internet device (MID), or an augmented reality (Augmented Reality, AR)/virtual reality (Virtual Reality, VR) ) equipment, robots, wearable devices, ultra-mobile personal computers (Ultra-Mobile Personal Computer, UMPC), netbooks or personal digital assistants (Personal Digital Assistant, PDA), etc., and can also be servers, network attached storage (Network Attached Storage, NAS), personal computer (Personal Computer, PC), television (Television, TV), teller machine or self-service machine, etc., the embodiments of this application are not specifically limited.

The image data transmission device in the embodiment of the present application may be a device with an operating system. The operating system can be an Android operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of this application.

The image data transmission device provided by the embodiment of the present application can implement the method embodiment in Figure 6 To avoid repetition, the various processes will not be described here.

Optionally, as shown in Figure 11, this embodiment of the present application also provides an electronic device 1100, including a processor 1101 and a memory 1102. The memory 1102 stores programs or instructions that can be run on the processor 1101. When the program or instruction is executed by the processor 1101, each step of the above image data transmission method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, the details will not be described here.

It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

Figure 12 is a schematic diagram of the hardware structure of an electronic device that implements an embodiment of the present application.

The electronic device 1200 includes but is not limited to: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, processor 1210, etc. part.

Those skilled in the art can understand that the electronic device 1200 may also include a power supply (such as a battery) that supplies power to various components. The power supply may be logically connected to the processor 1210 through a power management system, thereby managing charging, discharging, and function through the power management system. Consumption management and other functions. The structure of the electronic device shown in Figure 12 does not constitute a limitation of the electronic device. The electronic device may include more or less components than shown in the figure, or combine certain components, or arrange different components, which will not be described again here. .

Among them, processor 1210 is used for:

Get image data format information;

Determine the address offset according to the image data format information;

Obtain the first address information of each transmission of image data;

The image data is transmitted according to the first address information and the address offset of each transmission, wherein, after each row of image data is transmitted, the first address of the row is added to the address offset to skip. Go to the first address of the next line and transmit the next line of image data.

Optionally, the image data format information includes pixel depth and the number of pixels in each line;

The processor 1210 is further configured to determine the address offset based on the product of the pixel depth and the number of pixels in each row.

Optionally, the image data format information includes address space information occupied by pixels in each row;

Processor 1210, also used for:

Determine the address space size of each row according to the address space information occupied by the pixels in each row;

The address space size of each row is determined as the address offset.

Optionally, processor 1210 is also used to:

Determine the number of clock cycles for each transmission and processing of image data;

Determine the number of transmissions required to transmit one image data block according to the number of clock cycles and the image data block size and transmission data bit width in the image data format information;

Obtain the first address information of each transmission in the number of transmissions.

Optionally, processor 1210 is also used to:

Determine the number of pixels processed in each clock cycle according to the pixel depth, the image data block size and the transmission data bit width in the image data format information;

The number of transmissions required to transmit one image data block is determined based on the number of pixels processed per clock cycle and the number of clock cycles.

Optionally, processor 1210 is also used to:

According to the first address information of the i-th transmission, the image data of the j-th row where the first address information is located is transmitted, i is an integer greater than or equal to 1, and j is a positive integer;

Add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row;

Transmit the image data of the j+1th row according to the first address information of the j+1th row;

Wherein, every time a row of image data is transmitted, the first address of the row is added to the address offset, and the image data transmission of the next row is started until the i-th transmission is completed.

The electronic device in the embodiment of the present application obtains image data format information; determines the address offset according to the image data format information; obtains the first address information of each transmission of image data; and obtains the first address information of each transmission according to the first address information of each transmission. and the address offset, to transmit image data. After each row of image data is transmitted, the first address of the row is added to the address offset to jump to the first address of the next row, and the next row is transmitted. A row of image data. In this way, by determining the address offset, the During transmission, it automatically jumps to the transmission address of the next line of image data based on the first address information and address offset, thereby achieving continuous transmission of multiple lines of image data, which can improve the transmission efficiency of image data blocks without increasing the storage space for cache. .

It should be understood that in the embodiment of the present application, the input unit 1204 may include a graphics processor (Graphics Processing Unit, GPU) 12041 and a microphone 12042. The graphics processor 12041 is responsible for the image capture device (GPU) in the video capture mode or the image capture mode. Process the image data of still pictures or videos obtained by cameras (such as cameras). The display unit 1206 may include a display panel 12061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 1207 includes at least one of a touch panel 12071 and other input devices 12072 . Touch panel 12071, also known as touch screen. The touch panel 12071 may include two parts: a touch detection device and a touch controller. Other input devices 12072 may include but are not limited to physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be described again here.

Memory 1209 may be used to store software programs as well as various data. The memory 1209 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, Image playback function, etc.) etc. Additionally, memory 1209 may include volatile memory or nonvolatile memory, or memory 1209 may include both volatile and nonvolatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically removable memory. Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synch link DRAM, SLDRAM) and Direct Rambus RAM (DRRAM). Memory 1209 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

The processor 1210 may include one or more processing units; optionally, the processor 1210 integrates an application processor and a modem processor, where the application processor mainly handles operations related to the operating system, user interface, application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the above modem processor may not be integrated into the processor 1210.

Embodiments of the present application also provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the program or instructions are executed by a processor, each process of the above image data transmission method embodiment is implemented, and can achieve The same technical effects are not repeated here to avoid repetition.

Wherein, the processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage media, such as computer read-only memory ROM, random access memory RAM, magnetic disk or optical disk, etc.

An embodiment of the present application further provides a chip. The chip includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the above embodiments of the image data transmission method. Each process can achieve the same technical effect. To avoid repetition, we will not go into details here.

It should be understood that the chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.

Embodiments of the present application provide a computer program product. The program product is stored in a storage medium. The program product is executed by at least one processor to implement each process of the above image data transmission method embodiment, and can achieve the same technology. The effect will not be described here to avoid repetition.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. without further restrictions In this case, an element defined by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved. Functions may be performed, for example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. implementation. Based on this understanding, the technical solution of the present application can be embodied in the form of a computer software product that is essentially or contributes to the existing technology. The computer software product is stored in a storage medium (such as ROM/RAM, disk , optical disk), including several instructions to cause a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of this application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Inspired by this application, many forms can be made without departing from the purpose of this application and the scope protected by the claims, all of which fall within the protection of this application.

Claims (17)

An image data transmission method, including: Get image data format information; Determine the address offset according to the image data format information; Obtain the first address information of each transmission of image data; The image data is transmitted according to the first address information and the address offset of each transmission, wherein, after each row of image data is transmitted, the first address of the row is added to the address offset to skip. Go to the first address of the next line and transmit the next line of image data. The method according to claim 1, wherein the image data format information includes pixel depth and the number of pixels in each row; Determining the address offset according to the image data format information includes: The address offset is determined based on the product of the pixel depth and the number of pixels in each row. The method according to claim 1, wherein the image data format information includes address space information occupied by each row of pixels; Determining the address offset according to the image data format information includes: Determine the address space size of each row according to the address space information occupied by the pixels in each row; The address space size of each row is determined as the address offset. The method according to claim 1, wherein before obtaining the first address information for each transmission of image data, the method further includes: Determine the number of clock cycles for each transmission and processing of image data; The method of obtaining the first address information for each transmission of image data includes: Determine the number of transmissions required to transmit one image data block according to the number of clock cycles and the image data block size and transmission data bit width in the image data format information; Obtain the first address information of each transmission in the number of transmissions. The method according to claim 4, wherein said based on said number of clock cycles and said The image data block size and transmission data bit width in the image data format information determine the number of transmissions required to transmit an image data block, including: Determine the number of pixels processed in each clock cycle according to the pixel depth, the image data block size and the transmission data bit width in the image data format information; The number of transmissions required to transmit one image data block is determined based on the number of pixels processed per clock cycle and the number of clock cycles. The method according to any one of claims 1 to 5, wherein the transmission of image data based on the first address information of each transmission and the address offset includes: According to the first address information of the i-th transmission, the image data of the j-th row where the first address information of the i-th transmission is located is transmitted, i is an integer greater than or equal to 1, and j is a positive integer; Add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row; Transmit the image data of the j+1th row according to the first address information of the j+1th row; Wherein, every time a row of image data is transmitted, the first address of the row is added to the address offset, and the image data transmission of the next row is started until the i-th transmission is completed. An image data transmission device, including: The first acquisition module is used to acquire image data format information; The first determination module is used to determine the address offset according to the image data format information; The second acquisition module is used to obtain the first address information of each transmission of image data; A transmission module, configured to transmit image data according to the first address information of each transmission and the address offset, wherein, after each row of image data is transmitted, the first address of the row plus the address offset is used. Shift to jump to the first address of the next line and transmit the next line of image data. The image data transmission device according to claim 7, wherein the image data format information includes pixel depth and the number of pixels in each line; The first determining module is configured to determine the address based on the product of the pixel depth and the number of pixels in each row. The image data transmission device according to claim 7, wherein the image data format The information includes the address space information occupied by each row of pixels; The first determination module includes: A first determination unit configured to determine the address space size of each row based on the address space information occupied by the pixels of each row; A second determination unit is configured to determine the address space size of each row as the address offset. The image data transmission device according to claim 7, wherein the image data transmission device further includes: The second determination module is used to determine the number of clock cycles for each transmission and processing of image data; The second acquisition module includes: A third determination unit configured to determine the number of transmissions required to transmit an image data block based on the number of clock cycles and the image data block size and transmission data bit width in the image data format information; The obtaining unit is used to obtain the first address information of each transmission in the number of transmissions. The image data transmission device according to claim 10, wherein the third determining unit includes: A first determination subunit configured to determine the number of pixels processed in each clock cycle based on the pixel depth in the image data format information, the image data block size and the transmission data bit width; The second determination subunit is configured to determine the number of transmissions required to transmit an image data block based on the number of pixels processed per clock cycle and the number of clock cycles. The image data transmission device according to any one of claims 7 to 11, wherein the transmission module includes: The first transmission unit is used to transmit the image data of the j-th row where the first address information is located according to the first address information transmitted in the i-th time, where i is an integer greater than or equal to 1, and j is a positive integer; The second transmission unit is used to add the first address information of the i-th transmission to the address offset to obtain the first address information of the j+1th row; Transmit the image data of the j+1th row according to the first address information of the j+1th row; Wherein, every time a row of image data is transmitted, the first address of the row is added to the address offset, and the image data transmission of the next row is started until the i-th transmission is completed. An electronic device, including a processor and a memory. The memory stores programs or instructions that can be run on the processor. When the program or instructions are executed by the processor, any one of claims 1 to 6 is implemented. The steps of the image data transmission method described in the item. A readable storage medium on which a program or instructions are stored. When the program or instructions are executed by a processor, the steps of the image data transmission method according to any one of claims 1 to 6 are implemented. A chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the image data transmission method according to any one of claims 1 to 6 A step of. A computer program product, the program product is stored in a non-volatile storage medium, and the program product is executed by at least one processor to implement the image data transmission method as claimed in any one of claims 1 to 6 A step of. A communication device configured to perform the steps of the image data transmission method according to any one of claims 1 to 6.