CN116400290A

CN116400290A - Harmonic signal source generating circuit

Info

Publication number: CN116400290A
Application number: CN202310291118.3A
Authority: CN
Inventors: 姜洪浪; 王磊; 王晓东; 王爽; 张江涛; 赵婷; 黄洪涛; 张玉冠; 潘仙林; 左嘉; 陈方方; 王晔; 罗冉冉
Original assignee: National Institute of Metrology; China Electric Power Research Institute Co Ltd CEPRI
Current assignee: National Institute of Metrology; China Electric Power Research Institute Co Ltd CEPRI
Priority date: 2023-03-23
Filing date: 2023-03-23
Publication date: 2023-07-07
Anticipated expiration: 2043-03-23
Also published as: CN116400290B

Abstract

The application discloses a harmonic signal source generating circuit. Comprising the following steps: the system comprises a main control CPU, an A-phase RAM, a phase-locked loop, a CPLD counter, a scanning circuit and a D/A converter, wherein the main control CPU sends out a command for outputting harmonic signals to the A-phase CPU, the command mainly comprises harmonic frequency, harmonic amplitude and harmonic phase information, the A-phase CPU decodes the transmission command and outputs reference frequencies corresponding to the harmonic frequency to the scanning circuit through the phase-locked loop and the CPLD counter circuit, the scanning circuit addresses according to the received reference frequencies, reads the corresponding harmonic frequencies in the A-phase RAM, and outputs harmonic signals with different frequencies through the D/A converter.

Description

Harmonic signal source generating circuit

Technical Field

The invention relates to the technical field of power quality detection of power systems, and in particular relates to a harmonic signal source generation circuit.

Background

The complexity and uncertainty of the harmonics will seriously affect the accurate metering of the electrical energy. The national power grid company has put forward a new requirement for a new generation of internet of things electric energy meter that has a harmonic detection function, and the harmonic electric energy meter calibrating device is an indispensable device for tracing the electric energy meter. The reference standard JJF 1245.1-mounted alternating current energy meter type evaluation outline active energy meter report examination manuscript 2018.11.08 requires the detection of higher harmonics, and the verification device can instantly change the harmonic frequency after source lifting, namely zero time waiting is achieved. However, the existing method for generating the harmonic signal source in the calibrating device is generally considered only from how to correctly generate the signal waveforms containing different harmonics, and there is no method for generating the harmonic signal source capable of realizing correct output of the higher harmonics and fast change of the higher harmonics.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a harmonic signal source generating circuit.

According to an aspect of the present application, there is provided a harmonic signal source generating circuit including: a main control CPU, an A phase RAM, a phase-locked loop, a CPLD counter, a scanning circuit and a D/A converter, wherein

The main control CPU sends out the command of the harmonic signal to the A-phase CPU, the command mainly contains the harmonic frequency, the harmonic amplitude and the harmonic phase information, the A-phase CPU decodes the transmission command, outputs the reference frequency corresponding to the harmonic frequency to the scanning circuit through the phase-locked loop and the CPLD counting circuit, the scanning circuit addresses according to the received reference frequency, reads the corresponding harmonic frequency in the A-phase RAM, and outputs the harmonic signals of different frequencies through the D/A converter.

Optionally, the phase a CPU is connected to the CPLD counter of the phase locked loop through a preset number of address lines.

Optionally, the CPLD counter is provided with counting software for inserting counting points, and the lower the harmonic number is, the more counting points are inserted.

Optionally, the a-phase RAM includes: data RAM and address RAM, wherein

The data RAM comprises a RAM0 area and a RAM1 area, and is used for realizing the change of harmonic phases;

the address RAM is a dual-port RAM and corresponds to the RAM0 area and the RAM1 area.

Optionally, the RAM0 region and the RAM1 region implementing the change in harmonic phase includes:

sequentially copying waveform amplitude data stored in a RAM0 area into a RAM1 area, and switching the level of AN in AN address line from 0 to 1; or alternatively

Waveform amplitude data stored in the RAM1 area is sequentially copied to the RAM0 area, and the level of "AN" in the address line is switched from "1" to "0".

Therefore, the harmonic current source generating circuit provided by the invention is characterized in that the main control CPU sends out a command of outputting harmonic signals to the A-phase CPU, wherein the command mainly comprises information such as harmonic frequency, harmonic amplitude, harmonic phase and the like. After decoding the transmission command, the CPU of the A phase outputs the reference frequency of the corresponding harmonic frequency to the scanning circuit through the phase-locked loop and the CPLD counting circuit, the scanning circuit reads the corresponding harmonic frequency in the RAM according to the received reference frequency addressing, and outputs the harmonic signals of different frequencies after passing through the D/A converter. If the output phase of the higher harmonic wave needs to be changed, the A-phase CPU sends a RAM area switching signal to the dual-port RAM, if the current output waveform is stored in the RAM0 area, the CPU inquires and obtains the higher harmonic wave waveform data after the phase adjustment through the background, and stores the higher harmonic wave waveform data in the RAM1 area, and when the output is needed, the purpose of changing the higher harmonic wave output phase in an instantaneous mode can be achieved by only changing the highest bit of the address line of the dual-port RAM. Thereby realizing the correct output of the higher harmonic wave and the generation of a harmonic signal source with the rapid change of the higher harmonic wave.

The above, as well as additional objectives, advantages, and features of the present application will become apparent to those skilled in the art from the following detailed description of a specific embodiment of the present application when read in conjunction with the accompanying drawings.

Drawings

Some specific embodiments of the present application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. It will be appreciated by those skilled in the art that the drawings are not necessarily drawn to scale. In the accompanying drawings:

FIG. 1 is a schematic diagram of a harmonic signal source generation circuit according to an embodiment of the present application;

fig. 2 is a method of implementing a rapid change in harmonic frequency according to an embodiment of the present application.

Detailed Description

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order that those skilled in the art will better understand the present disclosure, a technical solution in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure, shall fall within the scope of the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and claims of the present disclosure and in the foregoing figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in connection with other embodiments. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

Fig. 1 is a schematic diagram of a harmonic signal source generating circuit according to one embodiment of the present application, and referring to fig. 1, the harmonic signal source generating circuit includes: a main control CPU, an A phase RAM, a phase-locked loop, a CPLD counter, a scanning circuit and a D/A converter, wherein

Optionally, the a-phase RAM includes: data RAM and address RAM, wherein

Specifically, the invention aims to solve the technical problems: the harmonic signal source generating circuit is used for detecting the harmonic electric energy meter and can quickly change the higher harmonic output. The dynamic response capability of the harmonic electric energy meter calibrating device to harmonic tracing is further improved by instantaneously changing the output of higher harmonics while ensuring the accurate output of each harmonic.

Fig. 1 is a schematic circuit diagram of a harmonic signal source for generating a phase, which only includes a main control CPU, an a-phase CPU, a dual-port RAM, a phase-locked loop, a CPLD counter, a scanning circuit, a D/a converter, and the like.

Principle of harmonic signal generation: the main control CPU sends out the command of the harmonic signal to the A-phase CPU, and the command mainly contains the information of harmonic frequency, harmonic amplitude, harmonic phase and the like. After decoding the transmission command, the CPU of the A phase outputs the reference frequency of the corresponding harmonic frequency to the scanning circuit through the phase-locked loop and the CPLD counting circuit, the scanning circuit reads the corresponding harmonic frequency in the RAM according to the received reference frequency addressing, and outputs the harmonic signals of different frequencies after passing through the D/A converter.

If the output phase of the higher harmonic wave needs to be changed, the A-phase CPU sends a RAM area switching signal to the dual-port RAM, if the current output waveform is stored in the RAM0 area, the CPU inquires and obtains the higher harmonic wave waveform data after the phase adjustment through the background, and stores the higher harmonic wave waveform data in the RAM1 area, and when the output is needed, the purpose of changing the higher harmonic wave output phase in an instantaneous mode can be achieved by only changing the highest bit of the address line of the dual-port RAM.

Furthermore, the harmonic current source generating circuit provided by the invention can realize the instantaneous change and output of higher harmonics while ensuring the accurate output of each harmonic, and is mainly improved and improved from two aspects of rapid change of harmonic frequency and rapid change of harmonic phase.

The specific implementation method is as follows:

1. method for realizing rapid change of harmonic frequency

The harmonic waveform is that the reference frequency pulse generates address signal scanning output through the external frequency doubling circuit of the phase-locked loop. If the 1 standard sine wave waveform is divided into n points, when m harmonics need to be output, the reference frequency is 50×mHz, and the output frequency is 50×mXnHz. Thus, two problems are brought about, namely, the adjustment fineness of the reference frequency is seriously sacrificed, and the phase-locked loop frequency tracking pressure is aggravated. The solution of the invention is as follows:

1) On hardware: the CPU adds 5 address line control lines to the phase-locked loop external counter to identify the times of harmonic wave output, so that the reference frequency output by the CPU is still kept at the 50Hz frequency point of the fundamental wave, and the frequency adjustment fineness is ensured.

2) Counting software program: and a plurality of counting points are inserted, and the lower the harmonic frequency is, the more the harmonic frequency is inserted, so that the high-frequency output of the phase-locked loop is maintained in a smaller fluctuation range, and the effectiveness and rapidity of phase locking are ensured.

A specific implementation is shown in fig. 2. Wherein: m: harmonic frequency (2-50); n: standard waveform count (fixed); and p: points are inserted.

2. Method for realizing rapid change of harmonic phase

In order to simplify the hardware circuit and save the hardware cost, and simultaneously to improve the rapidity and the flexibility of the phase shift, the invention adopts a software phase shift mode to realize the rapid change of the harmonic phase.

1) The waveform amplitude data are stored in the RAM in a form of a table, so that the calculation time of the waveform data is saved;

2) By changing the amplitude data order, the output phase of the waveform can be changed. The standard waveform can be generally divided into an integer number of points, such as 360 points, then shifted by one point, i.e., by 1 degree, and the following table is a case of phase shift by 4 degrees, i.e., by 4 points, see the following table "RAM data" for column red data.

3) The RAM space is divided into 2 areas, RAM0 and RAM1 areas. Zone 0 when the highest address an=0, zone 1 when the highest address an=1; see in particular the "AN" column of the table below.

4) When phase shifting, the data in the area 0 is copied to the area 1 in turn according to the requirement, and the output waveform of the signal source is still a waveform which is not phase shifted and is not interfered.

5) After the data is copied, the CPU only needs to switch the level of the address line AN from 0 to 1, and then 1-step rapid phase shifting is completed.

6) If phase shifting is continued, the above process may be repeated, the only being copying of data from zone 1 to zone 0.

Table 1RAM addressing and data table

The implementation effect of the invention is as follows:

1) The output of the higher harmonic wave is controlled by 5 address lines of the CPU in real time, and the switching is free from waiting;

2) The higher harmonic frequency fine tuning is realized by changing the output reference frequency by a CPU, software enables one-bit control, and the frequency fine tuning has no waiting;

3) The mode of software phase shifting is adopted to realize the rapid change of harmonic phase. The hardware circuit is simplified, and the hardware cost is saved;

4) The harmonic electric energy meter calibrating device is used for ensuring accurate output of higher harmonic waves, simultaneously realizing instantaneous change and output of the higher harmonic waves, and effectively improving dynamic response capability of the harmonic electric energy meter calibrating device to harmonic tracing.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the description of the present disclosure, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and to simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be configured and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present disclosure; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.

The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A harmonic signal source generation circuit, comprising: a main control CPU, an A phase RAM, a phase-locked loop, a CPLD counter, a scanning circuit and a D/A converter, wherein

The main control CPU sends out a command of outputting harmonic signals to the A-phase CPU, wherein the command mainly comprises harmonic frequency, harmonic amplitude and harmonic phase information, the A-phase CPU decodes the transmission command, outputs reference frequencies corresponding to the harmonic frequency to a scanning circuit through the phase-locked loop and the CPLD counting circuit, the scanning circuit addresses according to the received reference frequencies, reads corresponding harmonic frequencies in the A-phase RAM, and outputs harmonic signals with different frequency after passing through the D/A converter.

2. The harmonic signal source generation circuit according to claim 1, wherein the a-phase CPU is connected to the CPLD counter of the phase locked loop through a preset number of address lines.

3. The harmonic signal source generation circuit according to claim 2, wherein the preset number is 5 for achieving switching of harmonic phases.

4. The harmonic signal source generating circuit according to claim 1, wherein the CPLD counter is provided with counting software for inserting counting points, and the lower the number of harmonics, the more counting points are inserted.

5. The harmonic signal source generation circuit according to claim 2, wherein the a-phase RAM comprises: data RAM and address RAM, wherein

6. The harmonic-signal-source generating circuit according to claim 5, wherein the RAM0 region and the RAM1 region realize the change of the harmonic phase comprising:

sequentially copying waveform amplitude data stored in the RAM0 area to the RAM1 area, and switching the level of AN in the address line from 0 to 1; or alternatively

The waveform amplitude data stored in the RAM1 area is copied to the RAM0 area in turn, and the level of the AN in the address line is switched from 1 to 0.