JPH10174272A - Tester for protective relay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the automatic setting of a computed value by making the slip velocity between a fundamental wave and a higher harmonic wave the velocity where the slip angle does not get over the tolerable value, and besides, making the sweep velocity of the higher harmonic wave the velocity where the signal level variation value does not get over the tolerable value. SOLUTION: In case the fundamental wave is 50Hz, the oscillatory frequency f1 of a fundamental frequency generator 1 is set to 50Hz, and a signal adjuster 1a is set so that the output current of a current amplifier 1b may come to a stipulated value. Next, the oscillatory frequency f2 of a higher harmonic wave signal generator 2 is set, but it is set, being slid a little from the oscillatory frequency f1 of the fundamental wave signal generator 1, and a series of operations such as operation, etc., are computed with CPU4, using the value of operation/return time of a protective relay 3 to be tested, stored in a storage 4b. Moreover, in the case of automatically measuring the operation/return value by automatically sweeping the current value thereby changing it, this automatically reduces the applied current value with its current sweeping function from nonoperation state, and indicates the applied current value on a display 4c at the point when a contact S operates. As a result, the automatic computation and setting of the slip velocity and the sweep velocity become possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for testing a protection relay having a harmonic suppression function by an asynchronous method.

[0002]

2. Description of the Related Art Ratio differential protection relays are protection relays used to protect transformers, generators, and the like. In order to detect internal faults in a protection section, currents flowing into the protection section and currents flowing out of the protection section are detected. This is a protection relay that operates by judging the difference current from the current. If this ratio differential protection relay is used for transformer protection purposes, when the transformer is powered on, an inrush current will initially flow through this transformer, and it is therefore assumed that this is an accident inside the transformer. Malfunction may occur. Therefore, it is necessary to distinguish between such an exciting inrush current when the power is turned on and a current due to an actual failure. It is generally known that the excitation inrush current contains a large amount of second harmonic components, and by utilizing this phenomenon, the ratio of the second harmonic component to the basic component is equal to or higher than a certain set value (for example, 1%).
5%) to provide a harmonic suppression function that operates when
When the ratio of the second harmonic component is equal to or higher than a certain set value, this harmonic suppression function operates to lock the operation of the ratio differential protection relay, thereby preventing the relay from malfunctioning.

FIG. 7 shows a conventional test apparatus using an asynchronous method for testing characteristics of a harmonic suppression function. In the figure, reference numeral 31 denotes a fundamental wave signal generator. The fundamental wave signal f1 output from the fundamental wave signal generator is adjusted in signal amplitude by a controller 32 and applied to the input side of a current amplifier 33. The harmonic signal generator 34 generates a second harmonic signal f2, and its frequency f2 can be set slightly different from twice the frequency f1 of the fundamental signal generator 31. The signal is set so as to have a slip so that the phase changes continuously with respect to the signal. The signal amplitude is adjusted by the signal adjuster 35 and applied to the input side of the current amplifier 36. The outputs of the current amplifiers 33 and 36 are connected together via ammeters 37 and 38 and supplied to a protection relay 39 under test. The operation / recovery state of the protection relay under test 39 is performed by monitoring the output of the output contact S.

[0004] A test method using the test apparatus thus configured will be described. First, the signal controller 35 for the second harmonic
And the frequency f of the fundamental signal generator 31 is reduced.
1 is set to, for example, 50 Hz, the required test current If1 is passed while reading the ammeter 37 by adjusting the signal conditioner 32, and the protection relay under test 39 is activated. Next, the frequency of the harmonic signal generator 34 is set to, for example, 101 Hz in order to perform a test at an arbitrary phase, and then the signal controller 35 is adjusted to apply a relatively large second harmonic component to the protection relay under test. 39 is returned to the return state. From the return state, the signal controller 35 is adjusted to gradually reduce the second harmonic component, and the current value at which the output contact S of the protection relay 39 under test is operated again is set as the operation value Im. Next, the protection relay under test 39 is set in the operating state, and the signal controller 35 is adjusted from this state to gradually increase the second harmonic component, and the second harmonic when the protection relay 39 under test returns is restored. The return value Ir of the wave component is measured. The above-described measurement of the operation value / return value is performed by variously changing the value of the magnitude If1 of the fundamental wave.
The value of / Ifr is measured. Based on the test result based on this measurement, the quality of the protection relay 39 under test is determined.

As described above, according to the test method of the harmonic suppression measurement by the asynchronous method, since the frequency of the second harmonic is slightly shifted from the true second harmonic, the second harmonic is theoretically not used. The superposition phase of the harmonics can range from 0 degrees to 360 degrees, however, if the sliding speed between the two frequencies is faster than the operation or return time of the protection relay 39 under test, an erroneous test will occur. Since the result may be generated, it is necessary to set the slip speed of the asynchronous method in consideration of the operation / recovery time of the relay.

Therefore, in the conventional test method, the operation / recovery time of the protection relay to be tested is known in advance during the test, and the frequency of the second harmonic component that can guarantee a predetermined slip speed from the value, that is, the slip speed, is determined. There was a problem that had to be calculated and determined with a calculator or the like. For this reason, the operation is troublesome, and an incorrect setting may be made. When measuring the operation / return point, an automatic test apparatus that automatically sweeps the current value applied to the protection relay under test 39 to automate the measurement may be used. Accordingly, it was necessary to calculate the sweep speed and set it in the automatic test apparatus. Further, as another problem, since the fundamental frequencies of the fundamental wave signal generator 31 and the harmonic signal generator 34 as the signal generators are extremely close to each other, the clock signals of the respective signal generators interfere with each other, Since there is a possibility that the test operation may be adversely affected due to a frequency pull-in phenomenon or the like, it is necessary to pay close attention to the arrangement of components and the like.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has an object to automatically determine a sliding speed and an automatic sweep based on a known operation / recovery time of a protection relay under test. Calculates the sweep speed in the case, enables the automatic setting of the calculated value, and tests the protective relay that can generate two signals equivalent to the fundamental wave and harmonics necessary for the test from a single clock source. It is intended to provide equipment.

[0008]

According to the protection relay testing apparatus of the present invention, the slip speed generated between the phase of the fundamental signal and the signal corresponding to the harmonic is determined by the operation time or the recovery time of the protection relay under test, whichever is longer. The speed at which the slip angle does not exceed a predetermined allowable value in time, and the speed at which the signal level of the harmonic equivalent signal is swept is a speed at which the signal level change value does not exceed a predetermined allowable value. With this configuration, the protection relay can be tested efficiently and in a short time.

The signal source corresponding to the fundamental wave and the harmonic includes a single clock generation source, first counting means for counting clocks, and means for generating a fundamental wave signal based on the output of the clock source. Frequency dividing means for counting at a predetermined frequency dividing ratio,
Frequency dividing ratio setting means for setting the frequency dividing ratio, second counting means for counting the divided output, adding / subtracting means for adding / subtracting the outputs of the first and second counting means, and output of the adding / subtracting means. It is configured to generate a harmonic equivalent signal. With this configuration, a single clock generation source can generate a fundamental signal and a harmonic-equivalent signal having a phase relationship and a harmonic frequency close to the fundamental signal. It is possible to provide a stable protection relay testing device that does not cause a drop-in phenomenon or the like.

In addition, a signal source corresponding to the fundamental wave and the harmonics is provided as a separate means such as a single clock generation source, a first counting means for counting clocks, and a means for generating a fundamental signal based on the output. A cumulative addition means including an integer part and a decimal part which are incremented by a clock; a cumulative value setting means for setting a cumulative value including a decimal number in the cumulative addition means; and a harmonic based on an output of the integer part of the cumulative addition means. A configuration including means for generating a corresponding signal may be adopted. With this configuration, as in the case of the previous section, a single clock generation source can generate a fundamental signal and a harmonic equivalent signal having a phase relationship and a harmonic frequency close to the fundamental signal. In addition, it is possible to provide a stable protection relay test device that does not cause a pull-in phenomenon between the two signal generators.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a protection relay tester having a harmonic suppression function according to the first embodiment. Reference numeral 1 denotes a fundamental wave signal generator for generating a fundamental wave signal (f1). Signal conditioner 1a to be adjusted
After the amplitude is adjusted by the above, the signal is input to the current amplifier 1b. Reference numeral 2 denotes a harmonic signal generator for generating a signal corresponding to the second harmonic (hereinafter referred to as a second harmonic signal). The harmonic signal (f2) is the frequency of the fundamental signal generated by the fundamental signal generator 1. The fundamental wave signal is slipped (slipped) with respect to the fundamental wave signal by deliberately slightly deviating from twice the value of (f1).
) And the second harmonic signal (f2) are continuously changed. This output is adjusted in amplitude by a signal adjuster 2a for adjusting the signal amplitude, and then output from the current amplifier 2a.
b. The respective outputs of the current amplifiers 1b, 2b are current transformers (CT) 1c, 2c for detecting a current value.
Are connected to each other via an output terminal, where the output currents of the two current amplifiers are superimposed, and the combined current is applied to the current terminal of the protection relay 3 under test.

4 is a CPU for controlling the test circuit described above.
The CPU 4 is connected to an input / output circuit 4a, a storage unit 4b, a display unit 4c, and an operation unit 4d.
Each part of the test circuit is controlled via a. The signal lines connected to the fundamental signal generator 1 and the harmonic signal generator 2 control the oscillation frequencies of these signal generators. The signal lines connected to the signal conditioners 1a and 2a set the output of the signal conditioner 1a to a predetermined output level and control the output level of the signal conditioner 2a for a predetermined time (sweep time) under the control of the CPU 4. It is also possible to automatically change the signal amplitude. Thus, the current applied to the protection relay under test 3 can be swept. The signal lines connected to the current transformers (CT) 1c and 2c take current values into the CPU 4,
The signal line connected to the output contact S of the protection relay 3 under test sends the operation state of the protection relay 3 under test to the CPU 4 from the output contact S via the input / output circuit 4a.

A method of testing the harmonic suppression characteristic of the protection relay 3 under test by the test apparatus having the above-described configuration will be described for a case where the fundamental wave is 50 Hz. Prior to this test, the operation / recovery time of the protection relay 3 under test is measured in advance, and its data is stored in the storage unit 4b.

First, the oscillation frequency f of the fundamental wave signal generator 1
1 is set to 50 Hz via the CPU 4 and the signal conditioner 1
a is set so that the output current of the current amplifier 1b becomes a specified value. In this case, the output current can be read from the output of the current transformer 1c via the input / output circuit 4a. Next, the oscillation frequency f2 of the harmonic signal generator 2 is set. In this setting, the phase between the oscillation frequency f1 of the fundamental signal generator 1 and the oscillation frequency f2 of the harmonic signal generator 2 is continuously set. Therefore, the slip frequency is set to be slightly shifted from n times between these two frequencies (twice in the case of the second harmonic) by the slip frequency so that slip (slip) is intentionally generated. .

Assuming that the fundamental wave is sin (2πf · t) and the slip frequency of the nth harmonic is nΔf, the instantaneous value of the harmonic is sinｎ2πn (f + Δf) ｆt ｛= sin ｛(2πnf 瞬時 t).
t) + (2πnΔf · t), and an instantaneous phase difference Δθ = 2πnΔf · t with respect to the original harmonic is generated.
Therefore, in order to keep the phase change (slip angle) within the allowable angle p (degree) or less within the longer time Tr of the operation or the recovery time of the protection relay 3 under test from this equation, the n-th harmonic Must satisfy the following condition.

NΔf ≦ p / (360Tr) (1) From this condition, the slip time (= slip cycle) Ts is as follows. Ts ≧ (360Tr) / p (2) From these equations, the slip frequency nΔf or the slip time Ts can be determined. These numerical values are set in the harmonic signal generator 2 via the CPU 4. Taking the harmonic as the second harmonic and, from the above equation, assuming that the slip frequency of the second harmonic is 2Δf, 2Δf is higher or lower than 2f1 in order to obtain the required slip time. The second harmonic f
The upper and lower limits of 2 are: f2 = 2f1 ± 2Δf = 2f1 ± p / (360Tr)
Becomes

As an example, p = 10 degrees and Tr = 50 msec
Suppose that f1 = 50 Hz and the slip frequency 2Δf = ±
Since the frequency is 0.56 Hz, the upper limit of f2 is 100.56H
z, and the lower limit is 99.44 Hz.

A series of operations, such as an operation associated with the setting of the oscillation frequency f2 of the harmonic signal generator 2, is performed by using the value of the operation / return time of the protection relay 3 under test stored in the storage unit 4b in advance. It is calculated by the CPU 4 by a program, set in the harmonic signal generator 2, and displayed on the display unit 4c.

Next, the sweep time in the case where the current value applied to the protection relay under test 3 is changed by automatic sweeping (sweep) and the operation / return value of the protection relay under test 3 is automatically measured. The method will be described. In order to obtain the operating value of the protection relay 3 under test, first, a large number of second harmonic signals are caused to flow so that the protection relay 3 under test is inactive. Next, the applied current value is automatically reduced from the non-operation state by using a current sweep function (sweep), and the operation state of the protection relay 3 under test is monitored via the contact S by the CPU.
4, the sweep operation is stopped at the time when the contact S is operated, the applied current value at this time is stored in the storage unit 4b, and the stored value is displayed on the display unit 4c.

In this current sweep, if the current change speed is faster than one slip time, the current value greatly changes (in this case, decreases) during one slip time, so that the operation value is measured lower and an erroneous test is performed. Since there is a possibility of obtaining the result, it is necessary to set the current change speed in consideration of one slip time required for the slip occurring between the fundamental wave f1 and the harmonic f2 to make a round.

Now, the start current value of the sweep current is Ii, the stop current value is Ie, the sweep time from Ii to Ie is Tw, the rated value of the operation or return current of the protection relay 3 under test is Ia, and Ia of this rated value is Ia. , During one slip time Ts, d
Is allowed, the current sweep time Tw must satisfy the following relationship.

Tw ≧ k (Ii−Ie) Ts / d · Ia (3) As an example, the sweep current change width (Ii−Ie) = 10
A, the allowable rate of current change d = 3%, the operating current Ia = 5A,
Assuming that one slip time Ts = 1.8 seconds, k = 100 from the unit dimension of each numerical value. If these values are introduced into the equation (3), it is necessary to set the sweep time to 120 seconds or more.

As described above, (1) or (2)
If the slip speed and the sweep speed suitable for the protection relay under test 3 are obtained and programmed according to the equations (3) and
The protection relay under test 3 can be tested automatically and efficiently with a measurement error within an allowable value.

In this embodiment, the second harmonic has been described, but the same can be applied to the third and higher harmonics. In the test of the reset value, contrary to the test of the operation value, first, the protection relay under test 3 is set to the operation state, and from this state, the applied current of the harmonic signal is automatically increased, and the test is performed. The current value at which the test protection relay 3 returns is measured. In the above-mentioned test, the operation / recovery time of the protection relay under test 3 was measured. However, in practice, the specification of the target test protection relay is often known. What is necessary is just to set a value slightly larger than the standard value of the specification.

In the above-described embodiment, the test method in which the operation point of the protection relay 3 under test or the return operation point when the second harmonic is applied is determined by the sweep operation (sweep) has been described. When the operation state of the protection relay under test 3 is tested by applying a predetermined value of the fundamental wave and the harmonic, the sweep operation is unnecessary.

FIG. 2 is a block circuit diagram of a signal source of a tester of a protection relay according to a second embodiment of the present invention. In this embodiment, a single clock source generates a fundamental wave and a frequency corresponding to a harmonic that is not synchronized with the fundamental wave. In the figure, a reference clock 10 is an oscillator using a crystal oscillator, and its output is applied to a 12-bit fundamental wave counter 11, and a parallel binary output of the fundamental wave counter 11 is a 12-bit address of a fundamental wave ROM 12. Connected to input. This ROM 12
Stores the data of one cycle of the sine wave of the fundamental wave for the test, and the data output of the ROM 12 is a 12-bit D
Is input to the digital input side of the A / A converter 13 and the D /
A fundamental wave signal f1 converted into an analog value is generated from the output of the A converter 13.

A harmonic which is not synchronous with the fundamental wave is generated by a circuit described below. The output of the reference clock 1 is input to a 12-bit frequency dividing counter 14, and the parallel output of the frequency dividing counter 14 is connected to one input of a 12-bit comparator 15. The other input of the comparator 15 is connected to the output of a frequency division ratio input 15a for setting a numerical value necessary for setting a frequency division ratio of N corresponding to the generated harmonic. The output of the comparator 15 is the frequency division counter 1
4 (CLR) terminal and an input side of a 12-bit frequency dividing counter 16. The circuit composed of the frequency division counter 14, the comparator 15, and the frequency division ratio input 15a thus connected constitutes a frequency division circuit.
The frequency dividing counter 14 operates as an N-ary counter that is cleared every N pulses, and the frequency dividing counter 16 performs a counting operation that repeats with N times the number of pulses of the fundamental wave counter 11. The 12-bit parallel output of the frequency dividing counter 16 is connected to one input B of the adder / subtractor 17. The other input A of the adder / subtracter 17 is connected to a 12-bit parallel output of the fundamental counter 11. The adder / subtracter 17 operates as an adder when the MODE terminal is set to 0, and operates as a subtractor when the MODE terminal is set to 1.

The harmonic ROM 18 stores data for two cycles of a sine wave, and the parallel output of the adder / subtractor 17 is input to the address input side of the harmonic ROM 18 to specify an address. The waveform data of the harmonics for two cycles are sequentially read out, input to the D / A converter 19 in the next stage, and output the analog harmonic signal f2 to the output side of the D / A converter 19.

In the circuit thus constructed, the A input and the B input of the addition / subtraction circuit 17 for generating a signal corresponding to a harmonic are connected to the fundamental wave counter 11 as described above.
And the output of the frequency dividing counter 16 are input. Here, assuming that the B input is zero, the fundamental wave ROM2
And the address input values of the harmonic ROM 18 are the same, the phases of the fundamental wave and the harmonic wave coincide, and the frequency is twice as high as the fundamental wave, that is, 2f1. When a numerical value is set at the B input in this state, a phase difference occurs between the fundamental wave and the harmonic according to the value. In this embodiment, the B input is taken from the frequency dividing counter 16 to be changed over time so that the phase relationship between the fundamental wave and the harmonic wave is always changed so that no error occurs in the test.

FIG. 3 is a time chart for explaining the operation of this embodiment. FIG. 3A shows the temporal change of the address information for one cycle of the fundamental wave sent to the fundamental wave ROM 12 of the fundamental wave counter 11, and more precisely, changes stepwise. (The same applies hereinafter.) FIG.
2 shows a sine waveform of a fundamental wave read out from the reference numeral 2. FIG. 3C shows the output of the frequency dividing counter 16 which is repeated at N times the cycle of the fundamental wave counter 11 and is inputted to the input B of the adder / subtractor 17, and FIG.
1 shows the output of the adder / subtractor 17 to which the output of the frequency divider 16 has been added. Since the output of the fundamental wave counter 11 and the output of the frequency divider 16 are added, the repetition cycle of the adder / subtractor 17 is fast ( In this case, N = 5 and the number of repetitions is 6), and as shown in FIG.
9 transmits a signal corresponding to the second harmonic having a frequency higher than twice the fundamental frequency. (2 in the harmonic ROM 18
Waveform data for a cycle is stored. ) In addition, FIG.
And g are waveforms when the MODE terminal of the adder / subtractor 17 is set to 1 and operated as a subtractor. The repetition period of the adder / subtractor 17 is delayed, and the D / A converter 19 outputs a waveform that is more than twice the fundamental frequency. A signal corresponding to a low frequency second harmonic is transmitted.

As described above, the cycle of the address data of the harmonic ROM 18 is (1 ± 1 / N) times the cycle of the address data of the fundamental ROM 12, and the harmonic ROM 18 has two cycles.
Since the waveform data for the period is stored, the D / A converter 19 outputs an output having a frequency represented by the following equation.

F2 = (2 ± 2 / N) f1 (4) When this equation is solved for the absolute value of N ignoring the sign of ±, N = 2 / ({f2 / f1} -2) , F2 / f
If 1 = n, then N = | 2 / (n−2) | (5) FIG. 4 shows the relationship between the harmonic order n calculated from the equation (5) and the frequency division ratio N.

In the above description, the order of the harmonics is limited to the second harmonic, but higher harmonics can be generated by selecting the value of N.
For example, if N = 2, the third harmonic is N = 1.
Then, the fourth harmonic is obtained. In this embodiment, the adder / subtracter 17 is also used as a subtractor, but an adder and a two's complement generator may be used. In this embodiment, the harmonic ROM 18 stores two cycles of a sine wave. However, if three cycles and four cycles of data are stored, higher harmonics can be generated. Becomes easier. The clock applied to the frequency division counter 14 may be obtained from another clock source different from the reference clock 10.

Next, a third embodiment will be described. FIG. 5 is a block circuit diagram of an oscillator used in the tester of the protection relay according to this embodiment. In the figure, one output of a reference clock 21 is a 12-bit fundamental wave counter 2.
2, the output of the fundamental wave counter 22 is a fundamental wave ROM 2 in which data for one cycle of a sine wave is stored.
3 and the fundamental wave ROM 23
Is connected to the input of a D / A converter 24, from the output side of which a sine wave of a fundamental wave is read out and a fundamental wave f1 is sent to an output terminal.

The branched output of the reference clock 21 is 24
The bit (upper 12 bits are an integer part, lower 12 bits is a decimal part) is connected to the clock (CK) input of the latch 25. The latch 25 and the 24-bit adder 26 constitute an accumulator (accumulator). Every time a clock is input to the latch 25, the added value of the B input is added to the accumulated value of the latch 25 and stored. It performs an operation like going. The latch 25 and the adder 26 repeatedly perform the operation in a cycle of the reference clock × 4096, although there are differences depending on the value of the input B since the integer part is 12 bits (= 4096). In a cumulative adder having such a configuration, for example, assuming that the data given to the B input of the adder 26 is α, the value in the latch 25 is α, 2α for each clock input to the latch 25. , 3α,
4α,... Changes to a cumulative addition value obtained by adding α to the previous numerical value. In this embodiment, data calculated by the following equation is input to the input B of the adder 26 as a unit step amount.

1+ (n / m) (6) m: division factor of fundamental wave n: variable for determining frequency of harmonic The data calculated from equation (6) includes integers and decimals. The latch 25 and the adder 26 operate as a cumulative adder for numerical values including decimal numbers. The 24-bit output of the adder 26 is connected to the data input of the next-stage latch 25. The 24-bit output of the latch 25 is again applied to the adder 2
It returns to 6 and is input to the A input. Then, only the upper 12-bit integer part of the output of the latch 25 is applied to the address input of the harmonic ROM 27. The harmonic ROM 27 stores sine wave data for two cycles of the second harmonic. The output of the harmonic ROM 27 is the D / A converter 2
The output of the D / A converter 28 outputs a second harmonic signal corresponding to two cycles of a sine wave with respect to one cycle of the fundamental wave.

In the harmonic signal generating circuit thus configured, when a clock from the reference clock 21 is applied to the latch 25, the latch 2
The content of 5 is obtained by adding 1+ (n / m) from the B input of the adder 26 to the content at that time. In this embodiment, m = 4096 (the maximum value of 12 bits) and n is 41
Is set to an integral multiple of. By setting n in this way, it is possible to set the frequency of the harmonic in steps of approximately 1 Hz. In this embodiment, the adder 26
Can be set to 1- (n / m), in which case the frequency of the harmonics decreases with the value of n. FIG.
(a) and (b) show how the frequency of the harmonic changes depending on the positive / negative n value (a multiple of 41).

In this embodiment, B of the adder 26
Although a step amount of 1+ (n / m) is given to the input, if this step amount is changed to 2+ (n / m), the latch 2
Since an output of twice the frequency appears in the output of No. 5, the data of one cycle of the sine wave only needs to be stored in the harmonic ROM 27. Therefore, the same ROM as the fundamental ROM 23 can be used. Further, the clock applied to the latch 25 may be obtained from another clock source different from the reference clock 21.

The present invention is not limited to the above-described embodiments, and can be implemented with modifications without departing from the scope of the invention. If the target signal is at about the power supply frequency,
If a recent high-speed CPU is used without preparing special hardware for the oscillator, the creation of the fundamental wave and the harmonics can all be processed by software.

[0040]

According to the present invention, when testing the harmonic suppression characteristics of the protection relay under test by the asynchronous method, the slip speed is automatically calculated based on the known operation / recovery time of the protection relay under test. Calculated values can be set. Also, in the case of automatic sweep, calculation and setting of the sweep speed are enabled.
Further, it is possible to provide a test device for a protective relay capable of generating a fundamental wave signal and a signal corresponding to a harmonic by a single clock source.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram according to a second embodiment;

FIG. 3 is an output change diagram and a waveform diagram of each unit for explaining the embodiment.

FIG. 4 is a diagram showing a relationship between a division ratio N and a harmonic order in the embodiment.

FIG. 5 is a block circuit diagram according to a third embodiment;

FIG. 6 is a diagram showing a relationship between an input value n of cumulative addition and a harmonic frequency in the embodiment.

FIG. 7 is a block circuit diagram of a conventional protection relay testing apparatus.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 fundamental wave signal generator 1 a signal regulator 1 b current amplifier 1 c current transformer 2 harmonic signal generator 2 a signal regulator 2 b current transformer 2 c current transformer 3 protective relay under test 4 ... CPU 4a ... input / output circuit 4b ... storage unit 4c ... display unit 4d ... operation unit 10 ... reference clock 11 ... fundamental wave counter 12 ... fundamental wave ROM 13 ... D / A converter 14 ... frequency division counter 15 ... comparator 15a: Frequency division ratio input 16: Frequency divider counter 17: Adder / subtractor 18: Harmonic ROM 19: D / A converter 21: Reference clock 22: Fundamental wave counter 23: Fundamental ROM 24: D / A converter 25 ... Latch 26 ... Adder 27 ... Harmonic ROM 28 ... D / A converter.

Claims (3)

[Claims] 1. A signal equivalent to a harmonic is superimposed on a fundamental signal by sliding it in time, and the signal level of the signal equivalent to the harmonic is swept over time and applied to a protection relay under test. In a protective relay tester for testing wave suppression characteristics, the slip speed generated between the phase of the fundamental signal and the signal corresponding to the harmonic wave is such that the slip angle is longer in the longer of the operation or the return time of the protective relay under test. A speed that does not exceed a predetermined allowable value, and a speed at which the signal level of the harmonic equivalent signal is swept is a speed at which the signal level change value does not exceed a predetermined allowable value. Testing equipment for protective relays. A clock generation source; first counting means for counting the clock; fundamental wave generation means for generating a fundamental wave signal based on an output of the first counting means; Frequency dividing means for counting at the frequency dividing ratio, frequency dividing ratio setting means for setting the frequency dividing ratio to the frequency dividing means, second counting means for adding the output of the frequency dividing means, An addition / subtraction unit for adding or subtracting an output of the first counting unit and an output of the second counting unit, and a harmonic generation unit for generating a harmonic equivalent signal based on the output of the addition / subtraction unit. Test equipment for protective relay. 3. A clock generating source, first counting means for counting the clock, and fundamental wave generating means for generating a fundamental wave signal based on an output of the first counting means. Accumulating means including an integer part and a decimal part to be advanced, accumulative value setting means for setting an accumulative value including a decimal to the accumulating means, and generating a harmonic equivalent signal based on an output of the integer part of the accumulating means. A protection relay testing device comprising a harmonic generation means.