CN112559430B

CN112559430B - CPU and FPGA data interaction method and system suitable for narrow-band channel unit

Info

Publication number: CN112559430B
Application number: CN202011554701.1A
Authority: CN
Inventors: 季锦杰; 周峰; 沈乙鸥
Original assignee: Shanghai Institute of Microwave Technology CETC 50 Research Institute
Current assignee: Shanghai Institute of Microwave Technology CETC 50 Research Institute
Priority date: 2020-12-24
Filing date: 2020-12-24
Publication date: 2022-07-05
Anticipated expiration: 2040-12-24
Also published as: CN112559430A

Abstract

The invention provides a CPU and FPGA data interaction method and system suitable for a narrow-band channel unit, which comprises the following steps: step 1: at the CPU end, a processor is configured through a bottom driver by using an SPI interface of the CPU to receive and transmit data, and the SPI interface of the CPU end is set as a main end; step 2: at the FPGA end, data receiving and sending are completed by compiling an SPI interface program, and an SPI interface at the FPGA end is set as a slave end; and step 3: an SPI data packet protocol is formulated, data interaction takes a data packet as a unit, a master end actively sends the data packet, and a slave end sends the data packet in an interrupt mode; and 4, step 4: and formulating a channel processing flow, and ensuring the real-time property of voice and the reliability of data according to the type of the narrow-band channel. The invention fully considers the characteristics of the narrow-band channel, carries out special processing aiming at the channel type and the channel transmission content, and can ensure the real-time property of voice and the reliability of data.

Description

CPU and FPGA data interaction method and system suitable for narrow-band channel unit

Technical Field

The invention relates to the technical field of narrow-band communication systems, in particular to a method and a system for data interaction between a CPU (central processing unit) and an FPGA (field programmable gate array) suitable for a narrow-band channel unit.

Background

The narrow-band communication system comprises narrow-band communication control equipment and various narrow-band channel equipment (such as an ultra-short wave radio station, a flow residue, scattering, transmitted and the like). The narrow-band communication control equipment is a special router and mainly provides routing, switching and forwarding functions for various channel equipment. The narrowband channel unit is one of core boards of the communication control equipment and is responsible for processing a channel interconnection interface and data transmission service between the narrowband channel unit and the communication control equipment. The narrow-band channel unit is provided with a plurality of channel interfaces, and specifically comprises an asynchronous serial port, a K port, a baseband port and a four-wire audio port, wherein the serial port is used for transmitting data and packet speech, the K port is used for transmitting data and time slot speech, the baseband port is used for transmitting data, and the four-wire audio port is used for transmitting analog speech.

The narrow-band channel unit adopts a CPU + FPGA structure, the FPGA processes the time sequence and logic control of an interface, and the CPU processes a protocol stack. For the above, the FPGA needs to send the data stream received by the channel end to the CPU, and for the next, the CPU needs to send the data stream to the FPGA and finally send the data stream to the designated channel. Since the narrowband channels are of a wide variety and the transmission content contains both data and voice, there are reliability requirements for data and real-time requirements for voice. Most of the traditional multi-channel transmission protocols are based on IP protocols, and because the protocols mainly aim at broadband channels, the protocols have a large amount of redundancy and cannot meet the requirements of narrow-band channel communication systems.

Patent document CN109388597B (application number: CN201811160055.3) discloses a data interaction method and device based on FPGA, the method includes: a virtual P2P in the FPGA module receives a TLP-type data packet sent by the first terminal in a bridging manner and stores the data packet in a cache unit; the service unit in the FPGA module analyzes the data packet, acquires a destination terminal address and an address route corresponding to the data packet, and determines a second terminal according to the destination terminal address; judging the state of a bus connected between the second terminal and the FPGA module; when the state of the bus is determined to be in an idle state, the packet is read from the buffer unit and sent to the second terminal through the virtual P2P bridge.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a method and a system for data interaction between a CPU (central processing unit) and an FPGA (field programmable gate array) which are suitable for a narrow-band channel unit.

The data interaction method of the CPU and the FPGA, which is suitable for the narrow-band channel unit, provided by the invention comprises the following steps:

step 1: at the CPU end, a processor is configured through a bottom driver by using an SPI interface of the CPU to receive and transmit data, and the SPI interface at the CPU end is set as a main end;

step 2: at the FPGA end, data receiving and sending are completed by compiling an SPI interface program, and an SPI interface at the FPGA end is set as a slave end;

and 3, step 3: making an SPI data packet protocol, wherein data interaction takes a data packet as a unit, a master end actively sends the data packet, and a slave end sends the data packet in an interrupt mode;

and 4, step 4: and formulating a channel processing flow, and ensuring the real-time property of voice and the reliability of data according to the type of the narrow-band channel.

Preferably, the step 1 comprises:

step 1.1: configuring an SPI (serial peripheral interface) of a processor through a driver, and setting SPI parameters including a frequency division coefficient and master-slave setting;

step 1.2: and configuring processor interrupt, and receiving the data packet from the slave end in an interrupt response mode.

Preferably, the step 2 comprises:

and according to the SPI time sequence, writing an SPI slave end interface program at the FPGA end, and interconnecting the SPI interface pin of the slave end and the SPI interface pin of the main end.

Preferably, the step 3 comprises:

step 3.1: formulating an SPI data packet protocol, wherein the 1 st byte is a data packet header 0xEA, the 2 nd byte is a data packet length low byte, the 3 rd byte is a data packet length high byte, the 4 th byte is a command byte, the 5 th byte is a reserved byte, the following bytes are effective data packet bytes, and two CRC16 check bytes are added behind the effective data packet bytes;

step 3.2: dividing command bytes according to transmission contents;

step 3.3: setting an interaction mode, wherein a master terminal actively generates a clock and a chip selection signal during sending, actively sends data, and receives the data in an interruption mode during receiving; the slave end transmits data in an interrupt mode during transmission, and receives data according to a clock and a chip selection signal during reception.

Preferably, the step 4 comprises:

step 4.1: the narrowband channel types comprise serial port data, packet words, K port data, time slot words, baseband data and analog words; the processing priority is: grouping words, time slot words, analog words, serial port data, K port data and baseband data;

step 4.2: according to the narrow channel bandwidth, the voice uses a PCM coding mode, 160 bytes are used as a data packet, and the SPI occupation resource is saved by a mode of timing transmission every 20 ms;

step 4.3: in order to ensure the reliability of data transmission, data is processed according to the characteristics of different channels, a SLIP protocol is added to serial port data, an HDLC protocol is added to K port data, and RS + BCH codes are added to baseband data.

The CPU and FPGA data interaction system suitable for the narrow-band channel unit provided by the invention comprises:

module M1: at the CPU end, a processor is configured through a bottom driver by using an SPI interface of the CPU to receive and transmit data, and the SPI interface of the CPU end is set as a main end;

module M2: at the FPGA end, data receiving and sending are completed by compiling an SPI interface program, and an SPI interface at the FPGA end is set as a slave end;

module M3: making an SPI data packet protocol, wherein data interaction takes a data packet as a unit, a master end actively sends the data packet, and a slave end sends the data packet in an interrupt mode;

module M4: and formulating a channel processing flow, and ensuring the real-time property of voice and the reliability of data according to the type of the narrow-band channel.

Preferably, the module M1 includes:

module M1.1: configuring an SPI (serial peripheral interface) of a processor through a driver, and setting SPI parameters including a frequency division coefficient and master-slave setting;

module M1.2: and configuring processor interrupt, and receiving the data packet from the slave end in an interrupt response mode.

Preferably, the module M2 includes:

and according to the SPI time sequence, writing an SPI slave end interface program at the FPGA end, and interconnecting a slave end SPI interface pin and a master end SPI interface pin.

Preferably, the module M3 includes:

module M3.1: formulating an SPI data packet protocol, wherein the 1 st byte is a data packet header 0xEA, the 2 nd byte is a data packet length low byte, the 3 rd byte is a data packet length high byte, the 4 th byte is a command byte, the 5 th byte is a reserved byte, the following bytes are effective data packet bytes, and two CRC16 check bytes are added behind the effective data packet bytes;

module M3.2: dividing command bytes according to transmission contents;

module M3.3: setting an interaction mode, wherein a master terminal actively generates a clock and a chip selection signal during sending, actively sends data, and receives the data in an interruption mode during receiving; the slave end transmits data in an interrupt mode during transmission, and receives data according to a clock and a chip selection signal during reception.

Preferably, the module M4 includes:

module M4.1: the narrowband channel types comprise serial port data, packet words, K port data, time slot words, baseband data and analog words; the processing priority is: grouping words, time slot words, analog words, serial port data, K port data and baseband data;

module M4.2: according to the narrow channel bandwidth, the voice uses a PCM coding mode, 160 bytes are used as a data packet, and the SPI occupation resource is saved by a mode of timing transmission every 20 ms;

module M4.3: in order to ensure the reliability of data transmission, data is processed according to the characteristics of different channels, a SLIP protocol is added to serial port data, an HDLC protocol is added to K port data, and RS + BCH codes are added to baseband data.

Compared with the prior art, the invention has the following beneficial effects:

1. compared with the traditional IP protocol, the invention has 8 lead code bytes, 14 Ethernet header bytes, 20 IP header bytes and 4 CRC32 check bytes, and total 48 redundant bytes, the invention only has 7 redundant bytes, thus greatly saving the transmission bandwidth;

2. the voice of the invention adopts PCM coding mode, carries out timing transmission of voice in the form of data packet, and carries out priority arrangement of voice, thus effectively ensuring real-time property of voice transmission in narrow-band channel;

3. the invention adopts different protocols or coding modes for serial port data, K port data and baseband data aiming at the characteristics of the channel, thereby improving the reliable transmission of the data in the channel.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic diagram of exemplary connections;

FIG. 2 is a diagram of exemplary method steps;

FIG. 3 is a timing diagram of an example SPI;

FIG. 4 is a schematic diagram of the SPI protocol;

FIG. 5 is a flow chart for a lower implementation;

fig. 6 is a process flow of implementing the above.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will aid those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any manner. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the invention.

Example 1:

the invention provides a CPU and FPGA data interaction method, which is suitable for a narrow-band channel unit of communication control equipment and comprises the following steps:

step 1: at the CPU end, the SPI interface of the CPU is used, data receiving and transmitting of the bottom layer drive configuration processor end are carried out, and the SPI interface of the CPU end is set as a main end;

step 2: at the FPGA end, data receiving and sending are completed by compiling an SPI interface module, and an SPI interface at the FPGA end is set as a slave end;

and step 3: making an SPI data packet protocol, wherein data interaction takes a data packet as a unit, a master end actively sends the data packet, and a slave end sends the data packet in an interrupt mode;

and 4, step 4: a channel processing flow is formulated, and the real-time performance of voice and the reliability of data are ensured according to the type of a narrow-band channel;

wherein, step 1 includes the following steps:

step 1.1: configuring an SPI (serial peripheral interface) of a processor through a driver, and setting SPI parameters including frequency division coefficients, master-slave setting and the like;

step 1.2: the processor interrupt is configured, and the data packet receiving from the slave end is in an interrupt response mode.

The step 2 comprises the following steps:

and programming an SPI (serial peripheral interface) slave end interface module at the FPGA (field programmable gate array) end according to the SPI time sequence, and interconnecting a slave end SPI interface pin and a master end SPI interface pin.

The step 3 comprises the following steps:

step 3.1: and establishing an SPI data packet protocol. The 1 st byte is a data packet header 0xEA, the 2 nd byte is a data packet length low byte, the 3 rd byte is a data packet length high byte, the 4 th byte is a command byte, the 5 th byte is a reserved byte, the following bytes are effective data packet bytes, and two CRC16 check bytes are added behind the effective data bytes;

step 3.2: dividing command bytes according to transmission contents, wherein the command words occupy one byte in an SPI protocol and can accommodate 256 different transmission types at most;

step 3.3: and establishing an interactive mode. The master terminal actively generates a clock and a chip selection signal during sending, actively sends data, and receives the data in an interrupt mode during receiving. The slave end transmits data in an interrupt mode during transmission, and receives data according to a clock and a chip selection signal during reception.

The step 4 comprises the following steps:

step 4.1: the narrow-band channel comprises serial port data (asynchronous serial port), a packet telephone (asynchronous serial port), K port data (K port), a time slot telephone (K port), baseband data (baseband port) and an analog telephone (four-wire audio port);

step 4.2: to ensure voice real-time performance, the processing priority is set as: grouping words, time slot words, analog words, serial port data, K port data and baseband data. In addition, considering the narrow channel bandwidth, the voice uses the PCM coding mode, and uses 160 bytes as a data packet, and the timing transmission is carried out every 20ms to save the resources occupied by the SPI;

Example 2:

the CPU model adopted in the embodiment of this example is loongson 1B, and the FPGA model is huawei HWD2V 6000. An actual connection schematic diagram is shown in fig. 1, four pin lines of an SPI interface of a Loongson 1B processor are connected to four common IO pins of an FPGA, where ss is a chip selection pin, sck is a clock pin, mosi is a master output slave input data pin, and miso is a master input slave output data pin; in addition, one external interrupt pin of the Loongson 1B is connected to one common IO pin of the FPGA.

Fig. 2 shows an implementation method of the present invention, which specifically comprises the following steps:

step 1:

and configuring an SPI interface at the B end of the Loongson 1. According to the content of the Loongson 1B manual, d4 of the SPCR register is set to be 1, and an SPI interface is set as a master end; d3 and d2 bits of the SPCR register are configured as 11, and the clock polarity and the phase of the SPI interface are set to be 1 in cpol mode and 1 in cpha mode; d1 and d0 bits of the SPCR register and d1 and d0 bits of the SPER register are configured to be 00 and 01, the frequency division coefficient of the SPI interface is set to be 8, and the clock frequency sck of the SPI in the example is 15.625Mhz as the source clock of the frequency division is half of DDR _ CLK (125 Mhz).

The external interruption of the Loongson 1B is configured. According to the manual contents of the Loongson 1B, the external interrupt enable used is set to be effective, and the interrupt trigger mode is set to the high level trigger mode.

Step 2:

at an FPGA (Huawei HWD2V6000) end, data receiving and sending of the FPGA end are completed by writing an SPI interface, and the SPI interface of the FPGA end is set as a slave end; due to the asynchronous transceiving mode, the triple frequency of sck (i.e. 62.5Mhz) is used as the asynchronous sampling clock for receiving data from the FPGA end.

And step 3:

and (3) establishing a data interaction protocol, wherein data interaction takes a data packet as a unit, the Loongson 1B actively sends the data packet, and the Huawei HWD2V6000 sends the data packet in an interrupt mode.

And establishing an interactive mode. When the master terminal sends the data, the clock signal sck and the chip selection signal ss are actively generated, and the data are actively sent on the data line mosi. When the main terminal receives the data, the data is received in an interruption mode. The slave end sends data in an interruption mode during sending, and after the master end receives the interruption, the two situations are that: when the master end sends data, namely a clock line and a data line exist, the slave end directly sends data on the data line miso; and secondly, the master end does not send data any more, the master end provides a clock signal sck and a chip selection signal ss after receiving the interrupt, and the slave end sends data on the data line miso after confirming that the sck and the ss exist. The slave receives data according to the clock and chip select signals upon reception. The specific timing diagram is shown in fig. 3.

And establishing a data packet interaction protocol. The Loongson 1B and the Huawei HWD2V6000 carry out data interaction in the form of data packets through an SPI interface, and a specific data packet protocol is shown in FIG. 4. The SPI protocol includes:

(1) the master end sends: the first byte is data packet header 0xEA, the second and third bytes are effective data length bytes, the fourth byte is command byte, the fifth byte is reserved byte, the latter is effective byte stream data, and the last two bytes are CRC16 check bytes;

(2) and the slave side sends: triggered by an interrupt. The first byte is a data packet header 0xEA, the second byte and the third byte are effective data length bytes, the fourth byte is a command byte, the fifth byte is a reserved byte, the following bytes are effective byte stream data, and the last two bytes are CRC16 check bytes;

(3) when the master and slave have one valid and one invalid, the invalid side sends the IDLE byte (0 x 00). The command bytes in the SPI protocol are shown in table 1.

Command word	Means of	Remarks for note
			0x01	Packet speech 1
0x02	Packet voice	2
			0x11	Time slotted speech 1
0x12	Time slotted speech 2
			0x21	Analog speech 1
0x22	Analog voice	2
			0x31	Serial port data 1
0x32	Serial portData 2
			0x41	K port data 1
0x42	K port data 2
			0x51	Baseband data 1
0x52	Baseband data	2

Table 1 command bytes

And 4, step 4:

the embodiment example has 2 serial ports, 2K ports, 2 roadbed band ports and 2 four-wire audio ports. Therefore, the device can be subdivided into two paths of serial port data (asynchronous serial ports), two paths of packet phones (asynchronous serial ports), two paths of K-port data (K ports), two paths of time slot phones (K ports), two paths of baseband data (baseband ports) and two paths of analog phones (four-wire audio ports).

In order to meet the real-time requirement of voice, the processing priority is set as grouping speech 1, grouping speech 2, time slot speech 1, time slot speech 2, analog speech 1, analog speech 2, serial data 1, serial data 2, K port data 1, K port data 2, baseband data 1 and baseband data 2. All voices use a PCM coding mode, the voice transmission rate of PCM is 64Kbps, and in order to match the transmission rate of PCM and improve the voice packet interaction efficiency, 160 bytes are used as a packet and are transmitted at a timing of every 20ms to save resources occupied by SPI.

In the data part, a SLIP protocol is added to serial port data, an HDLC protocol is added to K port data, and RS + BCH coding is added to baseband data. The reason for increasing the protocol and the code is that the bit stream of the narrow-band channel is converted into bytes, so that the transmission efficiency is improved, and the channel error rate is reduced, so that the transmission reliability is improved.

The whole processing flow is divided into a lower part and an upper part. The downward direction is from the CPU end to the FPGA end to the channel end, and the upward direction is from the channel end to the FPGA end to the CPU end. For the next description, the CPU encapsulates the SPI protocol according to the transmission content and sends it to the FPGA, the FPGA distinguishes the channel content according to the command word, and directly forwards the packet speech, packetizes the slotted speech, performs PCM decoding and packetizing on the analog speech, performs SLIP protocol encapsulation on the serial data, performs HDLC protocol encapsulation on the K-port data, performs RS + BCH encoding on the baseband data, and sends the processed content to the channel, specifically, the next implementation flow is shown in fig. 5. In the above, the FPGA receives channel contents from different channel interfaces, directly forwards packet sessions, performs PCM encoding and packet combining on slotted sessions, performs SLIP protocol analysis on serial port data, performs HDLC protocol analysis on K port data, performs RS + BCH decoding on baseband data, and encapsulates the processed contents into an SPI protocol, and sends the SPI protocol to the CPU. In addition, when the multi-channel interface receives the content at the same time, the FPGA needs to perform backoff processing to preferentially process the high-priority content, store the sub-optimal content in the buffer area for waiting, determine the priority of the content to be processed again after the high-priority content is processed, select high processing, repeat this until all the channel contents are processed, and the specific implementation flow is shown in fig. 6.

The SPI transmission protocol of the embodiment only adds 7 redundant bytes, while the traditional IP protocol has 48 redundant bytes of 8 lead codes, 14 Ethernet headers, 20 IP headers and 4 CRC32 for verification, thereby increasing the transmission effectiveness and being very suitable for the transmission of narrow-band channels. In addition, aiming at voice, the method transmits in a PCM data packet mode, uses a priority processing mode, encapsulates different protocols and codes aiming at data by combining the channel characteristics, and meets the requirements of multi-channel, narrow bandwidth, low delay and high efficiency in a narrow-band communication system.

Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A CPU and FPGA data interaction method suitable for a narrow-band channel unit is characterized by comprising the following steps:

step 1: at the CPU end, a processor is configured through a bottom driver by using an SPI interface of the CPU to receive and transmit data, and the SPI interface of the CPU end is set as a main end;

and step 3: an SPI data packet protocol is formulated, data interaction takes a data packet as a unit, a master end actively sends the data packet, and a slave end sends the data packet in an interrupt mode;

the step 4 comprises the following steps:

step 4.1: the narrow-band channel type comprises serial port data, packet speech, K port data, time slot speech, baseband data and analog speech; the processing priority is: grouping words, time slot words, analog words, serial port data, K port data and baseband data;

2. The method for CPU and FPGA data interaction applicable to narrowband channel unit according to claim 1, wherein the step 1 comprises:

3. The method for CPU and FPGA data interaction applicable to narrowband channel unit of claim 1, wherein the step 2 comprises:

4. The method for CPU and FPGA data interaction applicable to narrowband channel unit of claim 1, wherein the step 3 comprises:

step 3.2: dividing command bytes according to transmission contents;

5. A CPU and FPGA data interaction system suitable for a narrow-band channel unit is characterized by comprising:

module M4: a channel processing flow is formulated, and the real-time performance of voice and the reliability of data are ensured according to the type of a narrow-band channel;

the module M4 includes:

6. The CPU and FPGA data interaction system applicable to the narrowband channel unit of claim 5, wherein the module M1 comprises:

7. The CPU and FPGA data interaction system applicable to narrowband channel units of claim 5, wherein the module M2 comprises:

8. The CPU and FPGA data interaction system applicable to the narrowband channel unit of claim 5, wherein the module M3 comprises:

module M3.2: dividing command bytes according to transmission contents;

module M3.3: setting an interaction mode, wherein a master terminal actively generates a clock and a chip selection signal during sending, actively sends data, and receives the data in an interruption mode during receiving; the slave end transmits data in an interrupt mode during transmission, and receives data according to the clock and the chip selection signal during receiving.