CN112835847B - Distributed interrupt transmission method and system for interconnected bare core - Google Patents
Distributed interrupt transmission method and system for interconnected bare core Download PDFInfo
- Publication number
- CN112835847B CN112835847B CN202110159838.5A CN202110159838A CN112835847B CN 112835847 B CN112835847 B CN 112835847B CN 202110159838 A CN202110159838 A CN 202110159838A CN 112835847 B CN112835847 B CN 112835847B
- Authority
- CN
- China
- Prior art keywords
- interrupt
- peer
- interface
- data packet
- distributed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a method for transmitting an interrupt request, and more particularly, to a method and a system for transmitting a distributed interrupt for an interconnected die. A distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node. The distributed interrupt transmission method for the interconnected bare core transmits the interrupt request in the form of the data packet in the network, gives the interrupt signal in a distributed interrupt mode after reaching the destination node, can reduce the consumption of wiring resources, and each master device can independently make judgment according to the fed-back information and perform corresponding exception handling, thereby reducing the dependence between different transmission events.
Description
Technical Field
The present invention relates to a method for transmitting an interrupt request, and more particularly, to a method and a system for transmitting a distributed interrupt for an interconnected die.
Background
In a monolithic asic, all components are designed and fabricated in the same process on a single silicon wafer. As process dimensions shrink, the cost and development cycle for developing such integrated circuits becomes extremely high. In this case, multi-die integration is a necessary option, i.e., a plurality of functional and verified unpackaged chip components are interconnected and assembled together, and packaged as a whole chip in the same Package, thereby forming a Package-level network NoP (network Package). These dies can be made by different processes and from different manufacturers, thus greatly shortening and reducing the development cycle and difficulty. The difficulty of multi-die integration is how to efficiently interconnect the dies and ensure that higher performance of the micro-system is realized under the constraint of power consumption. The existing communication protocol facing multi-die integration is a special protocol or has poor universality; or the technical system is too bulky and difficult to use. Under the condition that a multi-die interconnection bus protocol is immature, how to define the multi-die interconnection bus protocol which meets the development requirement of the current integrated circuit in China is a key problem for breaking through a new generation of integrated microsystem based on the actual condition and the current technical level of China.
From the view of system level division, the micro system is formed by cascading a plurality of micro assemblies, and each micro assembly is composed of an interconnected bare chip and other bare chips. The interconnected bare chip is a bare chip which is actually used and is formed by taking NoD (Network on Die) as a core and adding various standard protocol interface conversion, configuration units, clock management and other circuits. To improve the operating efficiency and real-time performance of the system, the interconnect die needs to provide interrupt service for the interconnect device. However, since the NoD is mainly used for interconnection, the interconnection network occupies most of the wiring space inside the chip, and the wiring difficulty is increased sharply if the conventional point-to-point interruption is continuously used.
Disclosure of Invention
In order to solve the above problems, the present invention provides a distributed interrupt transmission method for interconnected dies, in which an interrupt request is transmitted in a network in the form of a data packet, and an interrupt signal is given in a distributed interrupt manner after reaching a destination node, so that the consumption of wiring resources can be reduced, and each master device can independently make a judgment according to the fed back information and perform corresponding exception handling, so as to reduce the dependence between different transmission events, and the specific technical scheme is as follows:
a distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node.
Preferably, the distributed interrupt includes a master device accepting and sending an interrupt request, a slave device sending an interrupt request, and a peer device accepting and sending an interrupt request.
Preferably, the protocol conversion modules between the master device and the slave device are provided with interrupt interfaces for transmitting interrupts.
Preferably, the interrupt requests of the peer devices are all transmitted through the protocol conversion module.
A distributed interrupt system for interconnected bare chips is provided, wherein protocol conversion modules between master equipment and slave equipment on the interconnected bare chips are respectively provided with an interrupt interface for transmitting interrupt.
Compared with the prior art, the invention has the following beneficial effects:
the NoD is mainly used for interconnection, an interconnection network occupies most of wiring space in a chip, and the wiring difficulty is increased rapidly when the traditional point-to-point interruption is continuously used, so that an interruption request is transmitted in the network in a data packet mode, an interruption signal is given out in a distributed interruption mode after the interruption request reaches a destination node, the consumption of wiring resources can be reduced, meanwhile, the dependence between different events is reduced, and the overall operation efficiency is improved.
The NoD adopts distributed interruption to provide a set of independent interruption for each main equipment interface to assist read-write operation, and the interruption request is generated by a protocol conversion interface to the main equipment, and mainly comprises read/write failure (an external interface is not prepared or a read-write address is incorrect, etc.), read success (read data is input into a Buffer), read/write overtime, etc. Each master device can independently make judgment according to the fed back information and carry out corresponding exception handling, so that the stability of the system is improved.
Drawings
FIG. 1 is a diagram of a host interrupt interface receiving an interrupt request packet;
FIG. 2 is a master interrupt interface generating an interrupt to a master;
FIG. 3 is a diagram of a master writing interrupt information to an interrupt address through a data interface;
FIG. 4 is a block diagram of an interrupt interface packaging interrupt information into packets;
FIG. 5 is a slave device interrupt signal received from the slave device interrupt interface;
FIG. 6 is a slave device interrupt interface packaging an interrupt request into an interrupt event data packet;
FIG. 7 is a peer device interface receiving an interrupt request packet;
FIG. 8 is an interrupt generated by a peer interface to a peer;
FIG. 9 is a diagram of a peer device generating an interrupt signal to a peer to peer protocol conversion interface;
FIG. 10 is a diagram of a peer-to-peer protocol conversion interface packaging raw interrupt information into an interrupt event packet;
fig. 11 is a schematic diagram of a structure of an interconnect die.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
And transmitting the interrupt request in a data packet form in the network by adopting a feedback mechanism of distributed interrupt response, and giving an interrupt signal in a distributed interrupt mode after the interrupt request reaches a destination node.
A distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node.
Distributed interrupts include master accepting and sending interrupt requests, slave sending interrupt requests, and peer accepting and sending interrupt requests.
And the protocol conversion modules between the master equipment and the slave equipment are provided with interrupt interfaces for transmitting interrupt.
The interrupt requests of the peer devices are all transmitted through the protocol conversion module.
A protocol conversion module between a master device and a slave device on an interconnected bare chip is provided with an interrupt interface for transmitting interrupt.
As shown in fig. 11, an interconnect die includes: the protocol conversion circuit comprises a plurality of protocol conversion modules and is used for providing a plurality of standard mainstream protocol interfaces connected with the outside; the external interconnection interface comprises a pair of synchronous controllers and is used for communicating with other interconnection bare cores; and the internal bare chip level network comprises a transmission bus and a router, and the synchronous controller and the protocol conversion module are respectively connected with the boundary nodes of the internal bare chip level network and are used for transmitting data packets from interfaces or other interconnected bare chips.
The function bare chip is connected with the protocol conversion module through a standard protocol bus.
The interconnected bare cores are connected through an expansion bus (CIBP).
The interconnection bare chip mainly comprises an internal bare chip level Network (NoD), a protocol conversion circuit and an external interconnection interface. Nods are used for data routing and high-speed transmission. The protocol conversion circuit provides a plurality of standard mainstream protocol interfaces connected with the outside, and comprises a plurality of protocol conversion modules for converting the NoD protocol into the mainstream protocol and connecting with other functional bare cores. The external interconnection interface mainly comprises a pair of synchronous controllers, and the external interconnection interface is controlled by the synchronous controllers to realize data transmission of different clock domains inside and outside the bare chip. The external interconnection interface and each conversion module of the protocol conversion circuit are respectively connected with one boundary node in the NoD, so that a data transmission path is formed.
The interconnect die transmits the interrupt request in the form of a data packet over the network.
Because the NoD is used as an interconnection chip, the wiring space in the chip of the NoD is already occupied by the interconnection network, and the continuous use of the traditional point-to-point interruption can cause the wiring difficulty to be increased sharply, the interruption event is adopted, the interruption request is encoded and transmitted in the form of a data packet through the network, an interruption signal is given in a distributed interruption mode after the interruption request reaches a destination node, and no additional wiring resource is consumed.
The distributed interrupt refers to a set of independent interrupts provided by the NoD for each host device interface to assist read-write operations, and interrupt requests are generated by the protocol conversion interface to the host device, and mainly include read/write failures (external interfaces are not ready or read-write addresses are incorrect, etc.), read successes (read data are input into buffers), read/write timeouts, and the like. Each master device can independently make judgment according to the fed back information and perform corresponding exception handling. The interrupt mechanism needs the master device, the network and the slave device interface to be matched with each other, and is realized together.
The NoD is mainly used for interconnection, and an interconnection network occupies most of wiring space in a chip, so the NoD adopts a feedback mechanism of distributed interrupt response, transmits an interrupt request in a network in a data packet form, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node, thereby reducing the consumption of wiring resources.
The reception and transmission of interrupts may be classified according to different devices as follows:
first, the master device may receive and send interrupt requests. Because the read-write delay is larger after the NoD is adopted, for an interface adopting a master-slave relationship, the overall operation efficiency of the system cannot be reduced by leading the master device to wait for the read-write result excessively, and a set of distributed interrupt system needs to be designed for each master device to ensure that the master device responds in time and handles the abnormity. And simultaneously, the NoD ensures that each read-write of the main equipment can be smoothly completed, otherwise, an interrupt response is provided to remind the main equipment of exception handling. An independent interrupt interface is specially set in the main equipment interface to be responsible for processing the interrupt event, and the main equipment interrupt interface not only realizes responding to the interrupt event, but also realizes sending the interrupt event.
Second, the slave device may send an interrupt request. The slave device interface also has a special interrupt interface in addition to the data interface. The interrupt interface in the slave device interface can be used for collecting the interrupt generated by the slave device, and the interrupt interface packages the interrupt request into an interrupt event data packet after receiving the interrupt signal, then sends the interrupt event data packet into the network, and finally receives the interrupt by the destination master device.
Third, the peer may receive and send interrupt requests. The peer-to-peer protocol conversion interface has no special interrupt interface, when the peer-to-peer device is used as a virtual master device or a virtual slave device and needs to receive and transmit the interrupt event, the interrupt event data packet is still received and transmitted through the data input and output channel of the peer-to-peer protocol conversion interface, but at the moment, the transmission of the interrupt original information and the analysis of the interrupt information are realized by software.
The interrupt request is transmitted in the network in the form of data packets, and an interrupt signal is given in a distributed interrupt mode after the interrupt request reaches a destination node, so that the consumption of wiring resources can be reduced. And each master device can independently make judgment according to the fed back information and perform corresponding exception handling, so that the dependence between different transmission events is reduced.
Example one
The master device receives the interrupt request: the host device interface receives an interrupt request packet from another device in the network, and distributes the interrupt request packet to an interrupt interface in the host device interface, as shown in step 1 in fig. 1, and then as shown in step 2 in fig. 2, the interrupt interface unpacks the interrupt request packet according to a specified packet format, and parses the packet into an interrupt signal, and sends the interrupt signal to the host device.
The master device sends an interrupt request: a fixed space is used as an interrupt address in an address space of the host device, the host device writes interrupt information into its own interrupt address through a data interface (DDR), as shown in step 1 in fig. 3, the host device interface receives the interrupt information, packages the interrupt information into an interrupt data packet, sends the interrupt data packet to the network, and sends the interrupt data packet to other devices, as shown in step 2 in fig. 4.
Example two
Sending an interrupt request from the device: an interrupt interface in the slave device interface may be used to collect interrupts generated by the slave device, as shown in step 1 in fig. 5; the interrupt interface packages the interrupt request into an interrupt event data packet after receiving the interrupt signal, and then sends the interrupt event data packet to the network, as shown in step 2 in fig. 6.
EXAMPLE III
The peer may receive an interrupt request: when the peer device is used as a virtual master device, the peer-to-peer protocol conversion interface may receive an interrupt request packet from another device in the network, as shown in fig. 7, the peer-to-peer protocol conversion interface unpacks the packet according to a specified packet format, translates the packet into interrupt information raw data with an interrupt address, an interrupt number and other peer-to-peer device protocol formats, and sends the interrupt information raw data to the peer device, and the peer device uses software to implement analysis and response of the interrupt data, as shown in fig. 8.
The peer may send an interrupt request: when the peer device is used as a virtual slave device, the peer-to-peer protocol conversion interface may be used to collect the original interrupt information sent by the peer device using software, as shown in step 1 in fig. 9; the peer-to-peer protocol conversion interface receives the interrupt origination information and passively packages it into an interrupt event packet, which is then sent to the network, as shown in step 2 of fig. 10.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive step, which shall fall within the scope of the appended claims.
Claims (4)
1. A distributed interrupt transmission method for interconnected bare chips is characterized in that an interrupt request is coded and transmitted in a data packet form through a network, and an interrupt signal is given out in a distributed interrupt mode after the interrupt request reaches a destination node;
the distributed interrupt comprises a master device accepting and sending an interrupt request, a slave device sending an interrupt request and a peer device accepting and sending an interrupt request;
the master device receives the interrupt request: the main equipment interface receives interrupt request data packets from other equipment in the network and distributes the interrupt request data packets to the interrupt interface in the main equipment interface, and the interrupt interface unpacks the interrupt request data packets according to a specified data packet format, analyzes the data packets into interrupt signals and sends the interrupt signals to the main equipment;
the master device sends an interrupt request: the address space of the main device is provided with a fixed space as an interrupt address, the main device writes interrupt information into the interrupt address of the main device through a data interface, the interrupt information received by the main device interface is packaged into an interrupt data packet, and the interrupt data packet is sent to a network and sent to other devices;
sending an interrupt request from the device: the interrupt interface in the slave equipment interface can be used for collecting the interrupt generated by the slave equipment, and the interrupt interface packages the interrupt request into an interrupt event data packet after receiving the interrupt signal and then sends the interrupt event data packet to the network;
the peer may receive an interrupt request: when the peer-to-peer equipment is used as virtual master equipment, the peer-to-peer protocol conversion interface can receive an interrupt request data packet from other equipment in a network, the peer-to-peer protocol conversion interface unpacks the data packet according to a specified data packet format, translates the data packet into interrupt information original data with the protocol format of the peer-to-peer equipment such as an interrupt address, an interrupt number and the like, and sends the interrupt information original data to the peer-to-peer equipment, and the peer-to-peer equipment realizes the analysis and response of the interrupt data by using software;
the peer may send an interrupt request: when the peer-to-peer device is used as a virtual slave device, the peer-to-peer protocol conversion interface can be used for collecting original interrupt information sent by the peer-to-peer device by using software; the peer-to-peer protocol conversion interface receives the interrupt original information, passively packages the interrupt original information into an interrupt event data packet, and then sends the interrupt event data packet into a network.
2. The distributed interrupt transmission method for interconnected dies according to claim 1, wherein the protocol conversion modules between the master device and the slave devices are each provided with an interrupt interface for transmitting interrupts.
3. The distributed interrupt delivery method for interconnected dies of claim 1 wherein interrupt requests of the peer devices are each delivered through a protocol conversion module.
4. A distributed interrupt system for interconnected dies, for a distributed interrupt transmission method for interconnected dies according to any one of claims 1 to 3, characterized in that, the protocol conversion modules between the master device and the slave devices on the interconnected dies are each provided with an interrupt interface for transmitting interrupts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110159838.5A CN112835847B (en) | 2021-02-05 | 2021-02-05 | Distributed interrupt transmission method and system for interconnected bare core |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110159838.5A CN112835847B (en) | 2021-02-05 | 2021-02-05 | Distributed interrupt transmission method and system for interconnected bare core |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112835847A CN112835847A (en) | 2021-05-25 |
| CN112835847B true CN112835847B (en) | 2023-03-10 |
Family
ID=75932327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110159838.5A Active CN112835847B (en) | 2021-02-05 | 2021-02-05 | Distributed interrupt transmission method and system for interconnected bare core |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112835847B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168547A (en) * | 1989-12-29 | 1992-12-01 | Supercomputer Systems Limited Partnership | Distributed architecture for input/output for a multiprocessor system |
| JP2542460B2 (en) * | 1990-10-31 | 1996-10-09 | 富士通株式会社 | Data transfer interrupt control method |
| JPH0773059A (en) * | 1993-03-02 | 1995-03-17 | Tandem Comput Inc | Fault-tolerant computer system |
| US20020083254A1 (en) * | 2000-12-22 | 2002-06-27 | Hummel Mark D. | System and method of implementing interrupts in a computer processing system having a communication fabric comprising a plurality of point-to-point links |
| CN103685292A (en) * | 2013-12-20 | 2014-03-26 | 哈尔滨工业大学 | Universal device and method for protocol conversion |
| CN104468035B (en) * | 2014-11-13 | 2018-08-17 | 北京航空航天大学 | A kind of distribution POS data reliability transmission system and method |
| CN107248900A (en) * | 2017-06-30 | 2017-10-13 | 同济大学 | A kind of double relaying distribution LT code coding/decodings and transmission method |
-
2021
- 2021-02-05 CN CN202110159838.5A patent/CN112835847B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112835847A (en) | 2021-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112860612B (en) | Interface system for interconnecting bare core and MPU and communication method thereof | |
| WO2022166427A1 (en) | Data transmission events for use in interconnection die | |
| CN101753388B (en) | Router and interface device suitable for the extending on and among sheets of polycaryon processor | |
| JP2008522526A (en) | Data processing system and method for synchronizing data traffic | |
| CN110837486B (en) | FlexRay-CPCIe communication system based on FPGA | |
| US20220276677A1 (en) | An Inter-Die High-Speed Expansion System And An Expansion Method Thereof | |
| CN112817897B (en) | Communication method and communication system for interconnecting bare chip and DSP/FPGA | |
| CN112817906B (en) | Clock domain system of interconnected bare cores and management method thereof | |
| CN112835848B (en) | Inter-chip interconnection bypass system of interconnection bare chip and communication method thereof | |
| CN112817905A (en) | Interconnection bare chip, interconnection micro assembly, interconnection micro system and communication method thereof | |
| CN110635985A (en) | FlexRay-CPCIe communication module | |
| CN110971542A (en) | SRIO data transmission system based on FPGA | |
| CN114756493A (en) | Interface design and communication method for expandable interconnected bare core and peer-to-peer equipment | |
| JP2007534052A (en) | Integrated circuit and transaction withdrawal method | |
| US8260994B2 (en) | Interface for prototyping integrated systems | |
| CN112835847B (en) | Distributed interrupt transmission method and system for interconnected bare core | |
| CN114756494A (en) | Conversion interface of standard communication protocol and on-chip packet transmission protocol of multi-die interconnection | |
| CN113676253A (en) | FlexRay bus optical fiber communication module based on FPGA | |
| US20090327539A1 (en) | Multiple Die System Status Communication System | |
| US6912210B1 (en) | Data communication system and communication device used | |
| US11971446B2 (en) | Interface system for interconnected die and MPU and communication method thereof | |
| CN111813726B (en) | Method for converting control signal from high-speed bus to low-speed bus | |
| CN203102275U (en) | Peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card | |
| CN103198044A (en) | PCI (Peripheral Component Interconnect) dual redundancy CAN (Controller Area Network) bus card | |
| CN116974970A (en) | USB2.0 speed reduction bridge and data transmission system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |