CN203102275U - Peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card - Google Patents
Peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card Download PDFInfo
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- CN203102275U CN203102275U CN 201320110534 CN201320110534U CN203102275U CN 203102275 U CN203102275 U CN 203102275U CN 201320110534 CN201320110534 CN 201320110534 CN 201320110534 U CN201320110534 U CN 201320110534U CN 203102275 U CN203102275 U CN 203102275U
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Abstract
A peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card comprises a PCI interface chip, a field programmable gate array (FPGA) chip, an isolating power source chip, an isolating chip, a driving chip and a DB9 connector which are connected with each other in sequence, wherein the PCI interface chip is a PCI9030 chip, the FPGA chip is an X3C400 chip, the isolating power source chip is a DCP010505 chip, the isolating chip is an HCPL0611 chip, the driving chip is a PCA82C250 chip, and the DB9 connector is a standard DB9 pore type connector. The PCI dual-redundancy CAN bus card realizes a real dual-redundancy switching network, does not need software to interfere with the redundancy function management, only needs a simple read-write register, realizes redundancy management completely through hardware, and fills the blank of redundancy management through hardware.
Description
Technical field:
The utility model relates to a kind of PCI dual-redundant CAN bus card, belongs to CAN bus network control technology and two redundant handoff technique field.
Background technology:
Based on the control system of bus network, the error detecing capability of system and reliability become a kind of gordian technique.This has been carried out a lot of researchs both at home and abroad, redundancy is exactly one of them.
Present technology adopts the software administration redundancy, and comprehensive current various Redundancy Management schemes are summarized and got up to have three kinds:
First kind is bus driver level redundancy, i.e. a CPU, a CAN controller and two physical bus drivers;
Second kind is CAN bus controller level redundancy, i.e. a CPU, two CAN controllers, two physical bus drivers;
The third is system-level redundancy, i.e. two CPU, two CAN controllers, two physical bus drivers.
The dual-redundant CAN bus control system generally comprises a plurality of dual-redundant CAN bus nodes, and each node has two Physical layer line channels.
The utility model content
The dual-redundant CAN bus handover network that the utility model proposes, filled up the blank of hardware redundancy management, realized real two redundant handover network, need not software and interfere the redundancy feature management, only need simple read-write register to get final product, Redundancy Management is realized by hardware fully.
The utility model proposes a kind of two redundant communication systems, the node of PCI dual-redundant CAN bus card of the present utility model is installed, have the function of two redundancy communications based on the CAN bus.
The utility model provides PCI dual-redundant CAN bus card, and the second kind of redundancy scheme that is based in the background technology is the redundant solution that CAN bus controller level redundancy is proposed, and different is that Redundancy Management is realized by hardware logic in the utility model.CAN controller in second kind of scheme and CAN physical bus driver are realized by PCI dual-redundant CAN bus card, and the computing machine that PCI dual-redundant CAN bus card has been installed is as the CPU in second kind of scheme.The core of PCI dual-redundant CAN bus card is to realize CAN bus controller and Redundancy Management with fpga chip.
The functional character of above-mentioned Redundancy Management is that automatic channel status is judged, the automatic message sendaisle is selected, latchs the transmit status of two sendaisles automatically.
Described automatic channel status judges it is that the secondary status machine sends heartbeat message by the cycle and realizes, if when sending heartbeat message and causing the passive activation of CAN bus node mistake, then judges this channel failure.The transmission cycle and the content of described heartbeat message are set by register, and the maximum default transmission cycle is 20ms.
It is the channel status realization that host state machine provides by judging two secondary status machines that described automatic message sendaisle is selected.The transmission of a message is to begin from the state of judging the main channel, if the main channel state normally then sends from the main channel, otherwise the state of judgement alternate channel if the alternate channel state normally then sends from alternate channel, otherwise sends failure.Passage is randomly dispersed in several microseconds between the cycle transmitting time switching time.
The described transmit status that latchs two sendaisles automatically comprises that the successful channel number of transmission, transmission failure channel number, message send elapsed time, message is switched elapsed time and message transmit status.
A kind of PCI dual-redundant CAN bus of the utility model card, its structure as shown in Figure 1, it comprises pci interface chip, fpga chip, insulating power supply chip, isolating chip, chip for driving and DB9 joint, they are interconnected with one another according to the order of sequence.
Described pci interface chip links to each other with golden finger on the plate by the wiring on the pcb board on the one hand, is connected on the fpga chip by the wiring on the pcb board on the other hand.This pci interface chip adopts the PCI9030 chip of PLX company, and this chip can become the local address data bus to the pci bus protocol translation.PCI9030 have 132MB/s volume of transmitted data, local bus maximum clock 60MHz, support 5 local address scopes, 4 local bus gating signals, have big word of byte format and small character translation function, support to interrupt generation and 3.3V, 5V signal compatibility IO.Use PCI9030 can significantly reduce the development risk of pci bus, shortens the R﹠D cycle of product.
Described fpga chip is connected on the pci interface chip by the wiring on the pcb board on the one hand, is connected on the isolating chip by the wiring on the pcb board on the other hand.This fpga chip adopts the X3C400 chip of the SPARTAN3 series of XILINX company, finishes PCI local interface and dual-redundant CAN bus controller.X3C400 has 400,000 system doors, 56K position distributed RAM, the integrated block RAM in 288K position, 16 special multiplier, 4 Clock Managing Units and 141 available IO quantity of maximum, and have cheap, characteristics such as be widely used, become optimal selection of the present utility model.
Described insulating power supply chip, the power supply input of insulating power supply chip is provided by the wiring connection by the 5V golden finger on the pci bus, and the power supply output of insulating power supply chip provides power supply to isolating chip and chip for driving.This insulating power supply chip adopts the 1W insulating power supply chip DCP010505 of TI company, has the characteristics such as work efficiency, 1000V effective value voltage isolation and technical grade operating temperature range of output short circuit protection, overheating protection, full load maximum 75%.
Described isolating chip is connected on the fpga chip by the wiring on the pcb board on the one hand, is connected on the chip for driving by the wiring on the pcb board on the other hand.This isolating chip adopts the HCPL0611 of Fairchild Semiconductor company, its function is to receive the signal that fpga chip sends, pass to chip for driving after isolating then, perhaps receive the signal that chip for driving is sent, pass to fpga chip after isolating then.HCPL0611 is small-sized 8 pin Surface Mounts encapsulation, and the 10Mbit/s transmission speed of its superelevation and good common-mode rejection ratio can satisfy the anti-interference environment needs of severe rugged environment.The superelevation transmission speed of HCPL0611 is to improve the key condition of CAN bus baud rate and decision route bus length.The technical grade temperature range of HCPL0611 also can satisfy the needs of industry spot environment.
Described chip for driving is connected on the isolating chip by the wiring on the pcb board on the one hand, is connected on the DB9 joint by the wiring on the pcb board on the other hand.This chip for driving adopts the PCA82C250 of Philips Semiconductors, and conversion CAN bus signals becomes the TTL signal, and perhaps changing the TTL signal becomes the CAN bus signals.PCA82C250 has the bus protection measure of the highest 1M baud rate signal transmission capabilities, anti-mutation current, controls, has the receiver and the overheating protection of wide common mode range differential signal for the signal slope that reduces Radio frequency interference (RFI); the most important thing is cheap, be widely used, thereby become the optimal selection of CAN bus driver.
Described DB9 joint is that CAN bus driver chip signal output is connected on two DB9 connectors through PCB layout.Employing standard DB9 pass connector.
Advantage and effect: a kind of PCI dual-redundant CAN bus of the utility model card, its advantage is:
(1) the utility model adopts the parallel pci bus of universal high speed that computing machine and dual-redundant CAN bus controller soft nuclear are coupled together, and effectively improves system stability, can have good user interface simultaneously.
(2) the utility model utilizes FPGA to realize the hardware redundancy management, effectively reduces the intervention of upper layer software (applications), further enhanced system stability.
(3) in the utility model the FPGA code adopt can be comprehensive, the modular language design, be convenient to realize commercialization.
Description of drawings
The structural drawing of PCI dual-redundant CAN bus card among Fig. 1 the utility model embodiment;
FPGA code structure block diagram among Fig. 2 the utility model embodiment;
The two Redundancy Management controller external interface figure of the CAN of FPGA code structure among Fig. 3 the utility model embodiment;
The two Redundancy Management controller data address bus interfaces of the CAN of FPGA code structure are read sequential chart among Fig. 4 the utility model embodiment;
The two Redundancy Management controller data address bus interfaces of the CAN of FPGA code structure are write sequential chart among Fig. 5 the utility model embodiment;
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, the utility model embodiment is described in further detail below in conjunction with accompanying drawing.
Embodiment
The utility model proposes a kind of PCI dual-redundant CAN bus card, its structure as shown in Figure 1, it comprises pci interface chip, fpga chip, insulating power supply chip, isolating chip, chip for driving and DB9 joint.They are interconnected with one another according to the order of sequence.
Described pci interface chip links to each other with golden finger on the plate by the wiring on the pcb board on the one hand, is connected on the fpga chip by the wiring on the pcb board on the other hand.Pci interface chip adopts the PCI9030 chip of PLX company, and this chip can become the local address data bus to the pci bus protocol translation.PCI9030 have 132MB/s volume of transmitted data, local bus maximum clock 60MHz, support 5 local address scopes, 4 local bus gating signals, have big word of byte format and small character translation function, support to interrupt generation and 3.3V, 5V signal compatibility IO.Use PCI9030 can significantly reduce the development risk of pci bus, shortens the R﹠D cycle of product.
Described fpga chip is connected on the pci interface chip by the wiring on the pcb board on the one hand, is connected on the isolating chip by the wiring on the pcb board on the other hand.This fpga chip adopts the X3C400 chip of the SPARTAN3 series of XILINX company, finishes PCI local interface and dual-redundant CAN bus controller.X3C400 has 400,000 system doors, 56K position distributed RAM, the integrated block RAM in 288K position, 16 special multiplier, 4 Clock Managing Units and 141 available IO quantity of maximum, and have cheap, characteristics such as be widely used, become optimal selection of the present utility model.
Described insulating power supply chip, the power supply input of insulating power supply chip is provided by the wiring connection by the 5V golden finger on the pci bus, and the power supply output of insulating power supply chip provides power supply to isolating chip and chip for driving.This insulating power supply chip adopts the 1W insulating power supply chip DCP010505 of TI company, has the characteristics such as work efficiency, 1000V effective value voltage isolation and technical grade operating temperature range of output short circuit protection, overheating protection, full load maximum 75%.
Described isolating chip is connected on the fpga chip by the wiring on the pcb board on the one hand, is connected on the chip for driving by the wiring on the pcb board on the other hand.This isolating chip adopts the HCPL0611 of Fairchild Semiconductor company, its function is to receive the signal that fpga chip sends, pass to chip for driving after isolating then, perhaps receive the signal that chip for driving is sent, pass to fpga chip after isolating then.HCPL0611 is small-sized 8 pin Surface Mounts encapsulation, and the 10Mbit/s transmission speed of its superelevation and good common-mode rejection ratio can satisfy the anti-interference environment needs of severe rugged environment.The superelevation transmission speed of HCPL0611 is to improve the key condition of CAN bus baud rate and decision route bus length.The technical grade temperature range of HCPL0611 also can satisfy the needs of industry spot environment.
Described chip for driving is connected on the isolating chip by the wiring on the pcb board on the one hand, is connected on the DB9 joint by the wiring on the pcb board on the other hand.This chip for driving adopts the PCA82C250 of Philips Semiconductors, and conversion CAN bus signals becomes the TTL signal, and perhaps changing the TTL signal becomes the CAN bus signals.PCA82C250 has the bus protection measure of the highest 1M baud rate signal transmission capabilities, anti-mutation current, controls, has the receiver and the overheating protection of wide common mode range differential signal for the signal slope that reduces Radio frequency interference (RFI); the most important thing is cheap, be widely used, thereby become the optimal selection of CAN bus driver.
Described DB9 joint is that CAN bus driver chip signal output is connected on two DB9 connectors through PCB layout.Employing standard DB9 pass connector.
The utility model proposes a kind of PCI dual-redundant CAN bus card, the two Redundancy Management controllers of the CAN of its FPGA code can be as the standalone feature module application in the middle of large-scale FPGA Code Design, i.e. Fig. 2 dotted portion.
It comprises register 1 module, connects pci interface to Redundancy Management System.The running status of the duty of Redundancy Management System, the duty that CAN bus run 1 is set, record CAN bus run 1 is set.
It comprises register 2 modules, connects pci interface to Redundancy Management System.The duty of CAN bus run 2, the running status of record CAN bus run 2 are set.
It comprises Redundancy Management System, connects pci interface module, register 1 module and register 2 modules to two a CAN bus bit stream processor.Redundancy Management System comprises 3 state machines and some other combinational logics.
Its host state machine function that comprises in the Redundancy Management System comprises: passage switches, latchs passage switching time, latch data transmitting time, latch the message transmit status, latch the channel number that sends failure, latch and send successful channel number.
Its secondary status machine function that comprises in the Redundancy Management System comprises: the transmission of message, the transmission of heartbeat message, supervision channel status reach with host state machine and control exchange.
It comprises the bit stream processor module, connects Redundancy Management System and register module to FPGA serial input and output.Management CAN bus protocol, for example message transmission, message sink, fault processing, message format generation and identification, message filtering and message stores management etc.
The external interface of the two Redundancy Management controllers of described CAN as shown in Figure 3, in the present embodiment, external interface is divided into 5 major parts, is respectively: overall signal, data address bus, first passage signal, second channel signal and test signal.
Described overall signal comprises global reset signal, and the high level input resets, and clock signal, the input of 16MHz standard clock signal.
Described data address bus comprise read input signal, write input signal, bus begins input signal, bus acknowledge output signal, data bus input signal, data bus output signal and address bus input signal.
The two Redundancy Management controller data address bus interfaces of the CAN of described FPGA inner structure are read sequential chart as shown in Figure 4, each bus read cycle, begin by ads, and ack finishes.
The two Redundancy Management controller data address bus interfaces of the CAN of described FPGA inner structure are write sequential chart as shown in Figure 5, and each bus write cycle is begun by ads, and ack finishes.
Described first passage signal comprises: channel selecting signal chan_a_cs, CAN bus physical layer signal input chan_a_rx_i, CAN bus physical layer signal output chan_a_tx_o, look-at-me output chan_a_irq_on, clock signal output chan_a_clkout_o, status signal output chan_a_status.
Described second channel signal comprises: channel selecting signal chan_b_cs, CAN bus physical layer signal input chan_b_rx_i, CAN bus physical layer signal output chan_b_tx_o, look-at-me output chan_b_irq_on, clock signal output chan_b_clkout_o, status signal output chan_b_status.
Test signal, system's real-time clock signal input sysrtc, 32 of width, minimum resolution 50 μ s, test signal group 1 output test1,32 of width, test signal group 2 output test2,32 of width.
Claims (1)
1. PCI dual-redundant CAN bus card, it is characterized in that: it comprises pci interface chip, fpga chip, insulating power supply chip, isolating chip, chip for driving and DB9 joint, and they are interconnected with one another according to the order of sequence;
Described pci interface chip links to each other with golden finger on the plate by the wiring on the pcb board on the one hand, is connected on the fpga chip by the wiring on the pcb board on the other hand; This pci interface chip is the PCI9030 chip, and it becomes the local address data bus to the pci bus protocol translation;
Described fpga chip is connected on the pci interface chip by the wiring on the pcb board on the one hand, is connected on the isolating chip by the wiring on the pcb board on the other hand; This fpga chip is the X3C400 chip, finishes PCI local interface and dual-redundant CAN bus controller;
Described insulating power supply chip is the DCP010505 chip, and its power supply input is provided by the wiring connection by the 5V golden finger on the pci bus, and its power supply output provides power supply to isolating chip and chip for driving;
Described isolating chip is connected on the fpga chip by the wiring on the pcb board on the one hand, is connected on the chip for driving by the wiring on the pcb board on the other hand; This isolating chip is the HCPL0611 chip, and it receives the signal that fpga chip sends, and passes to chip for driving after isolating then, perhaps receives the signal that chip for driving is sent, and passes to fpga chip after isolating then;
Described chip for driving is connected on the isolating chip by the wiring on the pcb board on the one hand, is connected on the DB9 joint by the wiring on the pcb board on the other hand; This chip for driving is the PCA82C250 chip, and its conversion CAN bus signals becomes the TTL signal, and perhaps changing the TTL signal becomes the CAN bus signals;
Described DB9 joint is that CAN bus driver chip signal output is connected on two DB9 connectors through PCB layout, adopts standard DB9 pass connector.
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| CN 201320110534 CN203102275U (en) | 2013-03-12 | 2013-03-12 | Peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card |
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| CN 201320110534 CN203102275U (en) | 2013-03-12 | 2013-03-12 | Peripheral component interconnect (PCI) dual-redundancy controller area network (CAN) bus card |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198044A (en) * | 2013-03-12 | 2013-07-10 | 首都师范大学 | PCI (Peripheral Component Interconnect) dual redundancy CAN (Controller Area Network) bus card |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198044A (en) * | 2013-03-12 | 2013-07-10 | 首都师范大学 | PCI (Peripheral Component Interconnect) dual redundancy CAN (Controller Area Network) bus card |
| CN103198044B (en) * | 2013-03-12 | 2015-09-09 | 首都师范大学 | A kind of PCI dual-redundant CAN bus card |
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Granted publication date: 20130731 Termination date: 20150312 |
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