CN210780877U

CN210780877U - Embedded multi-CPU interconnection circuit based on SDIO interface

Info

Publication number: CN210780877U
Application number: CN202020042239.6U
Authority: CN
Inventors: 索艳滨; 邹式论; 卿辉; 刘鸿宇
Original assignee: Sichuan Weishitong Information Security Platform Technology Co ltd
Current assignee: CHENGDU 30JAVEE MICROELECTRONICS Co.,Ltd.
Priority date: 2020-01-09
Filing date: 2020-01-09
Publication date: 2020-06-16
Anticipated expiration: 2030-01-09

Abstract

The utility model provides an embedded many CPU interconnection circuit based on SDIO interface, the circuit includes the CPU group and an isolation accelerating unit that constitute by the multi-disc CPU, receive, send independent SDIO passageway and dedicated receipts, send and interrupt the connection through two sets of receipts between each CPU and the isolation accelerating unit, CPU group be connected with host computer, intranet and extranet; the circuit has the characteristics of simple structure, strong expansibility and high transmission performance, and avoids the defects of large I/O occupation quantity caused by adopting a parallel bus and low interconnection performance caused by a low-speed interconnection interface; the problem of high CPU occupancy rate caused by multiplexing of a transmitting-receiving bus and adopting of query processing at an embedded CPU end is avoided, and the defects of low bus utilization rate and channel congestion are overcome.

Description

Embedded multi-CPU interconnection circuit based on SDIO interface

Technical Field

The utility model relates to a network isolation field especially relates to embedded many CPU interconnection circuit based on SDIO interface.

Background

With the deep application of network technology, in order to meet the special requirements of a novel network attack means and a high-security network on security, the network isolation technology is applied, and the interaction of data information in a credible network is guaranteed by isolating harmful network security threats; at present, the general network isolation technology is based on the access control idea as a strategy and physical isolation; the special embedded hardware isolation technology is the core of the network isolation technology and mainly comprises an internal network processing unit, an external network processing unit and a special isolation switching unit; the hardware design relates to information interaction among multiple embedded CPUs, and how to realize high-speed performance with minimum hardware resource occupation is the key of the design.

A special embedded CPU or FPGA is generally adopted as a main processing unit of a network isolation service, necessary data channel routing and service acceleration functions are provided, and a plurality of embedded CPUs interconnected with the special embedded CPU or FPGA complete the management and control functions of an internal network, an external network and a security policy; although the traditional low-speed embedded interconnection mode such as I2C, SPI and the like is adopted, although the interconnection structure is simple, the interconnection performance is too low to meet the application requirement of a general network, and the interconnection mode adopting parallel synchronous and asynchronous buses has higher performance, but the interconnection of a plurality of groups of signals including chip selection, addresses and data needs to be completed, the interconnection structure of hardware is complex, the high requirement on the IO number of users for isolating a CPU or FPGA is provided, and in addition, the crosstalk between the signals also provides higher requirement on board-level wiring.

The high-speed serial interface is the current main trend, such as pcie, xaui, rgmii and the like, the interconnection is simple, the communication rate is high, but the premise is that an isolation CPU or FPGA has a controller or an IP resource supporting the high-speed protocol, and the protocol stack processing related to the high-speed protocol is complex, the realization difficulty is high, and the debugging workload is large; the 4-wire SDIO interface serving as a lightweight medium-low-speed storage and network interconnection interface has the advantages of simple hardware connection, good expansibility and higher transmission performance. In addition, the interface also supports CRC check, and the reliability of data communication is improved. However, the standard SDIO protocol employs multiplexing of the transceiving interface, which reduces the data transmission performance to a certain extent.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to the above-mentioned problem, provide embedded many CPU interconnection circuit based on SDIO interface, include the CPU group and an isolation accelerating unit that constitute by multi-disc CPU, each CPU with keep apart through two sets of receipts, send independent SDIO passageway and dedicated receipts, send the interrupt connection between the single, CPU group be connected with host computer, intranet and extranet.

Preferably, the isolation acceleration unit is a CPU or an FPGA.

Preferably, the CPU is an embedded CPU.

The CPU group comprises a first CPU, a second CPU and a third CPU, and the first CPU is communicated with the host machine through a USB interface to complete a policy management function; the second CPU establishes a main body secure network service channel with the internal network through the network channel; the third CPU is connected with the external network and establishes a channel.

The SDIO channels with independent receiving and sending comprise mutually independent sending interconnection unit groups and receiving interconnection unit groups.

The sending interconnection unit group comprises a sending channel clock signal, a sending channel command signal, a sending channel data transmission line and a sending channel interrupt signal.

The receiving interconnection unit group comprises a receiving channel clock signal, a receiving channel command signal, a receiving channel data transmission line and a receiving channel interrupt signal.

Further, the data transmission line of the sending channel is a bidirectional 4-way transmission line.

Further, the receiving channel data transmission line is a bidirectional 4-way transmission line.

The utility model has the advantages that: the interconnection device of the embedded multi-CPU network isolation access equipment has the characteristics of simple structure, strong expansibility and high transmission performance, and the circuit device completes network data routing and transceiving adaptation based on a 4-wire SDIO interface, thereby avoiding the defects of large I/O occupation quantity caused by adopting a parallel bus and low interconnection performance caused by a low-speed interconnection interface; and based on the design of a special interrupt mechanism matched with a data receiving and transmitting channel, the problems of multiplexing of a receiving and transmitting bus and high CPU occupancy rate caused by adopting query processing at an embedded CPU end are avoided, and the defects of low bus utilization rate and channel congestion are overcome.

By adopting the independent design of the transmitting and receiving channels, when the CLK is the standard 25Mhz transmission frequency, the bidirectional 100Mbps transmission performance can be achieved; the SDIO service has an independent receiving and sending interruption mechanism, so that the occupancy rate of the SDIO service to a CPU is low, CPU resources can be effectively released for other service processing, interconnection is realized based on an SDIO protocol, a built-in CRC (cyclic redundancy check) function of the protocol is well utilized, and the reliability of a data transmission channel is ensured; two SDIO channels which are independent in receiving and sending are adopted in a full duplex mode, network messages can be processed at high speed, network delay is avoided, the service function of the network messages is completed, and the network messages are suitable for embedded network security equipment.

Drawings

Fig. 1 is a circuit connection block diagram of the present invention;

fig. 2 is a connection diagram of the basic interconnection unit group of the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

The embedded multi-CPU interconnection circuit based on the SDIO interface shown in FIG. 1 comprises a CPU group consisting of a plurality of CPUs and an isolation acceleration unit, wherein each CPU is connected with the isolation acceleration unit through two groups of SDIO channels with independent receiving and sending and special receiving and sending interrupts, and the CPU group is connected with a host machine, an internal network and an external network.

The isolation acceleration unit is an isolation acceleration CPU or FPGA; the CPU is an embedded CPU, the CPU group comprises a CPU-0, a CPU-1 and a CPU-2, and the CPU-0 and the host machine are communicated through a USB interface to complete a strategy management function; CPU-1 establishes main body safety network service channel with inner network through network channel; CPU-2 connects to the external network and establishes a channel.

The network interconnection design between the three embedded CPUs and the isolated CPU or FPGA is a basic framework, and each embedded CPU and the isolated CPU or FPGA adopt SDIO channel design with independent receiving and sending and are matched with special receiving and sending interrupt connection; the host machine is communicated with the CPU-0 through a USB2.0 interface; the intranet establishes a main body secure network service channel with the CPU-1 through a network channel, the CPU-2 establishes a channel with an external unprotected network, and the CPU-1 and the CPU-2 complete network adaptation.

As shown in fig. 2, an SDIO 4-bit mode is used as a basic interconnection unit group, and two sets of SDIO channels which are independent in transmission and reception are arranged between each embedded CPU and the isolated CPU or FPGA and share VDD and VSS; and CLK, CMD, DAT0-3 are connected separately; in addition, the two special interrupt signals respectively correspond to the receiving and transmitting channels, and a high-performance transmission mechanism is provided for the system.

The sending interconnection unit group comprises a sending channel clock signal, a sending channel command signal, a sending channel data transmission line and a sending channel interrupt signal; the receiving interconnection unit group comprises a receiving channel clock signal, a receiving channel command signal, a receiving channel data transmission line and a receiving channel interrupt signal.

The data transmission line of the sending channel is a bidirectional 4-way transmission line and comprises DATt 0-3; the receiving channel data transmission line is a bidirectional 4-way transmission line and comprises DATr 0-3.

Specifically, CPUx is used as a reference to introduce each signal in the basic interconnection unit group:

sending an interconnection unit group:

the CLKt signal: transmitting a channel clock signal;

CMDt signal: sending channel command signals for transmitting commands and responses, bi-directional;

DATt 0-3 signal: 4 data transmission lines of a sending channel are bidirectional;

INTt signal: a channel-specific interrupt signal is sent.

Receiving an interconnection unit group:

the CLKr signal: receiving a channel clock signal;

CMDr signals: receiving channel command signals for transmitting commands and responses, bi-directional;

DATr 0-3 Signal: 4 data transmission lines of a receiving channel are bidirectional;

INTr signal: a channel-specific interrupt signal is received.

The basic principles and the main features of the invention and the advantages of the invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims.

Claims

1. The embedded multi-CPU interconnection circuit based on the SDIO interface is characterized by comprising a CPU group and an isolation accelerating unit, wherein the CPU group is composed of a plurality of CPUs, each CPU is connected with the isolation accelerating unit through two groups of SDIO channels which are independent in receiving and transmitting and special receiving and transmitting interrupt, and the CPU group is connected with a host machine, an internal network and an external network.

2. The embedded multi-CPU interconnect circuit based on SDIO interface of claim 1, wherein the isolation acceleration unit is a CPU or FPGA.

3. The SDIO interface based embedded multi-CPU interconnect circuit of claim 1 wherein the CPU is an embedded CPU.

4. The SDIO interface-based embedded multi-CPU interconnection circuit of claim 3, wherein the CPU group comprises a first CPU, a second CPU and a third CPU, and the first CPU and the host machine are communicated with each other through a USB interface to complete a policy management function; the second CPU establishes a main body secure network service channel with the internal network through the network channel; the third CPU is connected with the external network and establishes a channel.

5. The embedded multi-CPU interconnect circuit based on SDIO interface of claim 1 wherein the SDIO channels with independent transmission and reception comprise mutually independent transmission and reception interconnect unit groups.

6. The SDIO interface based embedded multi-CPU interconnect circuit of claim 5, wherein the set of transmit interconnect units comprises a transmit channel clock signal, a transmit channel command signal, a transmit channel data transfer line, and a transmit channel interrupt signal.

7. The SDIO interface based embedded multi-CPU interconnect circuit of claim 5, wherein the set of accept interconnect units comprises a receive channel clock signal, a receive channel command signal, a receive channel data transfer line, and a receive channel interrupt signal.

8. The SDIO interface-based embedded multi-CPU interconnect circuit of claim 6, wherein the transmit channel data transmission line is a bidirectional 4-way transmission line.

9. The SDIO interface-based embedded multi-CPU interconnect circuit of claim 7 wherein the receive channel data transmission line is a bidirectional 4-way transmission line.