CN112835847A - Distributed interrupt transmission method and system for interconnected bare core - Google Patents

Distributed interrupt transmission method and system for interconnected bare core Download PDF

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Publication number
CN112835847A
CN112835847A CN202110159838.5A CN202110159838A CN112835847A CN 112835847 A CN112835847 A CN 112835847A CN 202110159838 A CN202110159838 A CN 202110159838A CN 112835847 A CN112835847 A CN 112835847A
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interrupt
distributed
interconnected
interface
peer
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CN112835847B (en
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于宗光
魏敬和
黄乐天
冯敏刚
孙晓冬
田青
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CETC 58 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to a method for transmitting an interrupt request, and more particularly, to a method and a system for transmitting a distributed interrupt for an interconnected die. A distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node. The distributed interrupt transmission method for the interconnected bare chip transmits the interrupt request in the form of the data packet in the network, gives the interrupt signal in a distributed interrupt mode after reaching the destination node, can reduce the consumption of wiring resources, and each master device can independently make judgment according to the fed back information and carry out corresponding exception handling, thereby reducing the dependence between different transmission events.

Description

Distributed interrupt transmission method and system for interconnected bare core
Technical Field
The present invention relates to a method for transmitting an interrupt request, and more particularly, to a method and a system for transmitting a distributed interrupt for an interconnected die.
Background
In a monolithic asic, all components are designed and fabricated in the same process on a single silicon wafer. As process dimensions shrink, the cost and development cycle for developing such integrated circuits becomes extremely high. In this case, multi-die integration is a necessary choice, i.e., a plurality of functional and verified, unpackaged chip components are interconnected and assembled together, and packaged as a whole chip in the same package, thereby forming a package-level network nop (network package). These dies can be made by different processes and from different manufacturers, thus greatly shortening and reducing the development cycle and difficulty. The difficulty of multi-die integration is how to efficiently interconnect the dies and ensure that higher performance of the micro-system is realized under the constraint of power consumption. The existing communication protocol facing multi-die integration is a special protocol or has poor universality; or the technical system is too bulky and difficult to use. Under the condition that a multi-die interconnection bus protocol is immature, how to define the multi-die interconnection bus protocol which meets the development requirement of the current integrated circuit in China is a key problem for breaking through a new generation of integrated microsystems based on the practical situation and the current technical level in China.
From the view of system level division, the micro system is formed by cascading a plurality of micro assemblies, and each micro assembly is composed of an interconnected bare chip and other bare chips. The interconnection Die is a Die that is practically usable and is formed by using NoD (Network on Die) as a core and adding various standard protocol interface conversion, configuration units, clock management and other circuits. In order to improve the operating efficiency and real-time performance of the system, the interconnection die needs to provide interrupt service for the interconnection device. However, since NoD is primarily used for interconnection, the interconnection network occupies most of the wiring space inside the chip, and the wiring difficulty is increased dramatically if the conventional point-to-point interrupt is continuously used.
Disclosure of Invention
In order to solve the above problems, the present invention provides a distributed interrupt transmission method for interconnected dies, in which an interrupt request is transmitted in a network in the form of a data packet, and an interrupt signal is given in a distributed interrupt manner after reaching a destination node, so that the consumption of wiring resources can be reduced, and each master device can independently make a judgment according to the fed back information and perform corresponding exception handling, so as to reduce the dependence between different transmission events, and the specific technical scheme is as follows:
a distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node.
Preferably, the distributed interrupt includes a master device accepting and sending an interrupt request, a slave device sending an interrupt request, and a peer device accepting and sending an interrupt request.
Preferably, the protocol conversion modules between the master device and the slave device are provided with interrupt interfaces for transmitting interrupts.
Preferably, the interrupt requests of the peer devices are all transmitted through the protocol conversion module.
A distributed interrupt system for interconnected bare chips is provided, wherein protocol conversion modules between master equipment and slave equipment on the interconnected bare chips are respectively provided with an interrupt interface for transmitting interrupt.
Compared with the prior art, the invention has the following beneficial effects:
1, NoD is mainly used for interconnection, and the interconnection network has occupied most wiring space in the chip, continues to use traditional point-to-point interrupt can lead to the wiring degree of difficulty increase sharply, consequently transmits the interrupt request in the form of data packet in the network, gives the interrupt signal through the mode of distributed interrupt after reaching the destination node, can reduce the consumption of wiring resources, has also reduced the dependence between different events simultaneously, has improved whole operating efficiency.
2, NoD adopts distributed interrupt to provide a set of independent interrupt for each main device interface to assist read-write operation, the interrupt request is generated by the protocol conversion interface to the main device, which mainly includes read/write failure (external interface is not ready or read-write address is incorrect, etc.), read success (read data has been input into Buffer), read/write overtime, etc. Each master device can independently make judgment according to the fed back information and carry out corresponding exception handling, so that the stability of the system is improved.
Drawings
FIG. 1 is a diagram of a host interrupt interface receiving an interrupt request packet;
FIG. 2 is a master interrupt interface generating an interrupt to a master;
FIG. 3 is a diagram of a master writing interrupt information to an interrupt address through a data interface;
FIG. 4 is a block diagram of an interrupt interface packaging interrupt information into packets;
FIG. 5 is a slave interrupt signal received from a slave interrupt interface;
FIG. 6 is a slave device interrupt interface packaging an interrupt request into an interrupt event data packet;
FIG. 7 is a peer device interface receiving an interrupt request packet;
FIG. 8 is an interrupt generated by a peer interface to a peer;
FIG. 9 is a diagram of a peer device generating an interrupt signal to a peer to peer protocol conversion interface;
FIG. 10 is a diagram of a peer-to-peer protocol conversion interface packaging raw interrupt information into an interrupt event packet;
fig. 11 is a schematic diagram of a structure of an interconnect die.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
And transmitting the interrupt request in a data packet form in the network by adopting a feedback mechanism of distributed interrupt response, and giving an interrupt signal in a distributed interrupt mode after the interrupt request reaches a destination node.
A distributed interrupt transmission method for interconnected bare cores encodes an interrupt request, transmits the interrupt request in a data packet form through a network, and gives an interrupt signal in a distributed interrupt mode after reaching a destination node.
Distributed interrupts include master accepting and sending interrupt requests, slave sending interrupt requests, and peer accepting and sending interrupt requests.
And the protocol conversion modules between the master equipment and the slave equipment are provided with interrupt interfaces for transmitting interrupt.
The interrupt requests of the peer devices are all transmitted through the protocol conversion module.
A protocol conversion module between a master device and a slave device on an interconnected bare chip is provided with an interrupt interface for transmitting interrupt.
As shown in fig. 11, an interconnect die includes: the protocol conversion circuit comprises a plurality of protocol conversion modules and is used for providing a plurality of standard mainstream protocol interfaces connected with the outside; the external interconnection interface comprises a pair of synchronous controllers and is used for communicating with other interconnection bare chips; and the internal bare chip level network comprises a transmission bus and a router, and the synchronous controller and the protocol conversion module are respectively connected with the boundary nodes of the internal bare chip level network and are used for transmitting data packets from interfaces or other interconnected bare chips.
The function bare chip is connected with the protocol conversion module through a standard protocol bus.
The interconnected bare cores are connected through an expansion bus (CIBP).
The interconnection bare chip mainly comprises an internal bare chip level Network (NoD), a protocol conversion circuit and an external interconnection interface. NoD for data routing and high speed transport. The protocol conversion circuit provides a plurality of standard mainstream protocol interfaces connected with the outside, and comprises a plurality of protocol conversion modules for converting NoD protocol to mainstream protocol, and is used for being connected with other functional bare cores. The external interconnection interface mainly comprises a pair of synchronous controllers, and the external interconnection interface is controlled by the synchronous controllers to realize data transmission of different clock domains inside and outside the bare chip. The external interconnection interface and each conversion module of the protocol conversion circuit are respectively connected with one boundary node in NoD, thereby forming a data transmission path.
The interconnect die transmits the interrupt request in the form of a data packet over the network.
NoD is used as an interconnection chip, the wiring space in the chip is already occupied by most of the interconnection network, and the continuous use of the traditional point-to-point interruption can lead to the rapid increase of the wiring difficulty, so the interruption event is adopted, the interruption request is coded and transmitted through the network in the form of data packets, and the interruption signal is given out in the distributed interruption mode after reaching the destination node, thus no additional wiring resource is consumed.
The distributed interrupt refers to NoD providing a set of independent interrupts for each host device interface to assist read/write operations, and the interrupt request is generated by the protocol conversion interface to the host device, and mainly includes read/write failure (external interface is not ready or read/write address is incorrect, etc.), read success (read data has been input into Buffer), read/write timeout, etc. Each master device can independently make judgment according to the fed back information and perform corresponding exception handling. The interrupt mechanism needs the master device, the network and the slave device interface to be matched with each other, and is realized together.
NoD is mainly used for interconnection, and the interconnection network occupies most of the wiring space inside the chip, so NoD adopts a feedback mechanism of distributed interrupt response to transmit the interrupt request in the form of data packets in the network, and after reaching the destination node, the interrupt signal is given out in a distributed interrupt manner, which can reduce the consumption of wiring resources.
The reception and transmission of interrupts may be classified according to different devices as follows:
first, the master device may receive and send interrupt requests. Because the NoD is adopted, the read-write delay is large, so for an interface adopting a master-slave relationship, the overall operation efficiency of the system cannot be reduced by leading the master device to wait for the read-write result excessively, and a set of distributed interrupt system needs to be designed for each master device to ensure that the master device responds in time and handles the abnormity. Meanwhile, NoD should ensure that each read/write operation of the host device can be successfully completed, otherwise an interrupt response should be provided to remind the host device to perform exception handling. An independent interrupt interface is specially set in the main equipment interface to be responsible for processing the interrupt event, and the main equipment interrupt interface not only realizes responding to the interrupt event, but also realizes sending the interrupt event.
Second, the slave device may send an interrupt request. The slave device interface also has a special interrupt interface in addition to the data interface. The interrupt interface in the slave device interface can be used for collecting the interrupt generated by the slave device, and the interrupt interface packages the interrupt request into an interrupt event data packet after receiving the interrupt signal, then sends the interrupt event data packet into the network, and finally receives the interrupt by the destination master device.
Third, the peer may receive and send interrupt requests. The peer-to-peer protocol conversion interface has no special interrupt interface, when the peer-to-peer device is used as a virtual master device or a virtual slave device and needs to receive and transmit the interrupt event, the interrupt event data packet is still received and transmitted through the data input and output channel of the peer-to-peer protocol conversion interface, but at the moment, the transmission of the interrupt original information and the analysis of the interrupt information are realized by software.
The interrupt request is transmitted in the form of data packets in the network, and an interrupt signal is given in a distributed interrupt mode after the interrupt request reaches a destination node, so that the consumption of wiring resources can be reduced. And each master device can independently make judgment according to the fed back information and carry out corresponding exception handling, so that the dependence between different transmission events is reduced.
Example one
The master device receives the interrupt request: the host device interface receives an interrupt request packet from another device in the network, and distributes the interrupt request packet to an interrupt interface in the host device interface, as shown in step 1 in fig. 1, and then as shown in step 2 in fig. 2, the interrupt interface unpacks the interrupt request packet according to a specified packet format, and parses the packet into an interrupt signal, and sends the interrupt signal to the host device.
The master device sends an interrupt request: a fixed space is used as an interrupt address in the address space of the master device, the master device writes interrupt information into its own interrupt address through a data interface (DDR), as shown in step 1 in fig. 3, the master device interface receives the interrupt information, packages the interrupt information into an interrupt data packet, sends the interrupt data packet to the network, and sends the interrupt data packet to other devices, as shown in step 2 in fig. 4.
Example two
Sending an interrupt request from the device: an interrupt interface in the slave device interface may be used to collect interrupts generated by the slave device, as shown in step 1 in fig. 5; the interrupt interface packages the interrupt request into an interrupt event data packet after receiving the interrupt signal, and then sends the interrupt event data packet to the network, as shown in step 2 in fig. 6.
EXAMPLE III
The peer may receive an interrupt request: when the peer device is used as a virtual master device, the peer-to-peer protocol conversion interface may receive an interrupt request packet from another device in the network, as shown in fig. 7, the peer-to-peer protocol conversion interface unpacks the packet according to a specified packet format, translates the packet into interrupt information raw data with an interrupt address, an interrupt number and other peer-to-peer device protocol formats, and sends the interrupt information raw data to the peer device, and the peer device uses software to implement analysis and response of the interrupt data, as shown in fig. 8.
The peer may send an interrupt request: when the peer device is used as a virtual slave device, the peer-to-peer protocol conversion interface may be used to collect the original interrupt information sent by the peer device using software, as shown in step 1 in fig. 9; the peer-to-peer protocol conversion interface receives the original interrupt information and passively packages it into an interrupt event packet, which is then sent to the network, as shown in step 2 in fig. 10.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive step, which shall fall within the scope of the appended claims.

Claims (5)

1. A distributed interrupt transmission method for interconnected bare cores is characterized in that an interrupt request is coded and transmitted through a network in the form of a data packet, and an interrupt signal is given out in a distributed interrupt mode after the interrupt request reaches a destination node.
2. The distributed interrupt delivery method for interconnected dies of claim 1 wherein the distributed interrupt includes master accept and send interrupt requests, slave send interrupt requests, and peer accept and send interrupt requests.
3. The distributed interrupt transmission method for interconnected dies according to claim 2, wherein the protocol conversion modules between the master device and the slave devices are each provided with an interrupt interface for transmitting interrupts.
4. The distributed interrupt delivery method for interconnected dies of claim 2 wherein interrupt requests of the peer devices are each delivered through a protocol conversion module.
5. A distributed interrupt system for interconnected bare chips is characterized in that protocol conversion modules between master equipment and slave equipment on the interconnected bare chips are provided with interrupt interfaces for transmitting interrupts.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04167842A (en) * 1990-10-31 1992-06-15 Fujitsu Ltd Data transfer interrupt control system
US5168547A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Distributed architecture for input/output for a multiprocessor system
US5845060A (en) * 1993-03-02 1998-12-01 Tandem Computers, Incorporated High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors
US20020083254A1 (en) * 2000-12-22 2002-06-27 Hummel Mark D. System and method of implementing interrupts in a computer processing system having a communication fabric comprising a plurality of point-to-point links
CN103685292A (en) * 2013-12-20 2014-03-26 哈尔滨工业大学 Universal device and method for protocol conversion
CN104468035A (en) * 2014-11-13 2015-03-25 北京航空航天大学 Distributed type POS data reliability transmission system and method
CN107248900A (en) * 2017-06-30 2017-10-13 同济大学 A kind of double relaying distribution LT code coding/decodings and transmission method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168547A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Distributed architecture for input/output for a multiprocessor system
JPH04167842A (en) * 1990-10-31 1992-06-15 Fujitsu Ltd Data transfer interrupt control system
US5845060A (en) * 1993-03-02 1998-12-01 Tandem Computers, Incorporated High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors
US20020083254A1 (en) * 2000-12-22 2002-06-27 Hummel Mark D. System and method of implementing interrupts in a computer processing system having a communication fabric comprising a plurality of point-to-point links
CN103685292A (en) * 2013-12-20 2014-03-26 哈尔滨工业大学 Universal device and method for protocol conversion
CN104468035A (en) * 2014-11-13 2015-03-25 北京航空航天大学 Distributed type POS data reliability transmission system and method
CN107248900A (en) * 2017-06-30 2017-10-13 同济大学 A kind of double relaying distribution LT code coding/decodings and transmission method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
薛志宏,刘建业: "TMS320C54XX系列DSP异步串行数据传输的研究与实现" *

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